1 /* 2 * Cherryview/Braswell pinctrl driver 3 * 4 * Copyright (C) 2014, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * 7 * This driver is based on the original Cherryview GPIO driver by 8 * Ning Li <ning.li@intel.com> 9 * Alan Cox <alan@linux.intel.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/dmi.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/types.h> 21 #include <linux/gpio.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/acpi.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinconf-generic.h> 28 #include <linux/platform_device.h> 29 30 #define CHV_INTSTAT 0x300 31 #define CHV_INTMASK 0x380 32 33 #define FAMILY_PAD_REGS_OFF 0x4400 34 #define FAMILY_PAD_REGS_SIZE 0x400 35 #define MAX_FAMILY_PAD_GPIO_NO 15 36 #define GPIO_REGS_SIZE 8 37 38 #define CHV_PADCTRL0 0x000 39 #define CHV_PADCTRL0_INTSEL_SHIFT 28 40 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 41 #define CHV_PADCTRL0_TERM_UP BIT(23) 42 #define CHV_PADCTRL0_TERM_SHIFT 20 43 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 44 #define CHV_PADCTRL0_TERM_20K 1 45 #define CHV_PADCTRL0_TERM_5K 2 46 #define CHV_PADCTRL0_TERM_1K 4 47 #define CHV_PADCTRL0_PMODE_SHIFT 16 48 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 49 #define CHV_PADCTRL0_GPIOEN BIT(15) 50 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 51 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 52 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 53 #define CHV_PADCTRL0_GPIOCFG_GPO 1 54 #define CHV_PADCTRL0_GPIOCFG_GPI 2 55 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 56 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 57 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 58 59 #define CHV_PADCTRL1 0x004 60 #define CHV_PADCTRL1_CFGLOCK BIT(31) 61 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 62 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 63 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 64 #define CHV_PADCTRL1_ODEN BIT(3) 65 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 66 #define CHV_PADCTRL1_INTWAKECFG_MASK 7 67 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 68 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 69 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 70 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 71 72 /** 73 * struct chv_alternate_function - A per group or per pin alternate function 74 * @pin: Pin number (only used in per pin configs) 75 * @mode: Mode the pin should be set in 76 * @invert_oe: Invert OE for this pin 77 */ 78 struct chv_alternate_function { 79 unsigned pin; 80 u8 mode; 81 bool invert_oe; 82 }; 83 84 /** 85 * struct chv_pincgroup - describes a CHV pin group 86 * @name: Name of the group 87 * @pins: An array of pins in this group 88 * @npins: Number of pins in this group 89 * @altfunc: Alternate function applied to all pins in this group 90 * @overrides: Alternate function override per pin or %NULL if not used 91 * @noverrides: Number of per pin alternate function overrides if 92 * @overrides != NULL. 93 */ 94 struct chv_pingroup { 95 const char *name; 96 const unsigned *pins; 97 size_t npins; 98 struct chv_alternate_function altfunc; 99 const struct chv_alternate_function *overrides; 100 size_t noverrides; 101 }; 102 103 /** 104 * struct chv_function - A CHV pinmux function 105 * @name: Name of the function 106 * @groups: An array of groups for this function 107 * @ngroups: Number of groups in @groups 108 */ 109 struct chv_function { 110 const char *name; 111 const char * const *groups; 112 size_t ngroups; 113 }; 114 115 /** 116 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 117 * @base: Start pin number 118 * @npins: Number of pins in this range 119 */ 120 struct chv_gpio_pinrange { 121 unsigned base; 122 unsigned npins; 123 }; 124 125 /** 126 * struct chv_community - A community specific configuration 127 * @uid: ACPI _UID used to match the community 128 * @pins: All pins in this community 129 * @npins: Number of pins 130 * @groups: All groups in this community 131 * @ngroups: Number of groups 132 * @functions: All functions in this community 133 * @nfunctions: Number of functions 134 * @gpio_ranges: An array of GPIO ranges in this community 135 * @ngpio_ranges: Number of GPIO ranges 136 * @nirqs: Total number of IRQs this community can generate 137 */ 138 struct chv_community { 139 const char *uid; 140 const struct pinctrl_pin_desc *pins; 141 size_t npins; 142 const struct chv_pingroup *groups; 143 size_t ngroups; 144 const struct chv_function *functions; 145 size_t nfunctions; 146 const struct chv_gpio_pinrange *gpio_ranges; 147 size_t ngpio_ranges; 148 size_t nirqs; 149 acpi_adr_space_type acpi_space_id; 150 }; 151 152 struct chv_pin_context { 153 u32 padctrl0; 154 u32 padctrl1; 155 }; 156 157 /** 158 * struct chv_pinctrl - CHV pinctrl private structure 159 * @dev: Pointer to the parent device 160 * @pctldesc: Pin controller description 161 * @pctldev: Pointer to the pin controller device 162 * @chip: GPIO chip in this pin controller 163 * @regs: MMIO registers 164 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 165 * offset (in GPIO number space) 166 * @community: Community this pinctrl instance represents 167 * 168 * The first group in @groups is expected to contain all pins that can be 169 * used as GPIOs. 170 */ 171 struct chv_pinctrl { 172 struct device *dev; 173 struct pinctrl_desc pctldesc; 174 struct pinctrl_dev *pctldev; 175 struct gpio_chip chip; 176 void __iomem *regs; 177 unsigned intr_lines[16]; 178 const struct chv_community *community; 179 u32 saved_intmask; 180 struct chv_pin_context *saved_pin_context; 181 }; 182 183 #define ALTERNATE_FUNCTION(p, m, i) \ 184 { \ 185 .pin = (p), \ 186 .mode = (m), \ 187 .invert_oe = (i), \ 188 } 189 190 #define PIN_GROUP(n, p, m, i) \ 191 { \ 192 .name = (n), \ 193 .pins = (p), \ 194 .npins = ARRAY_SIZE((p)), \ 195 .altfunc.mode = (m), \ 196 .altfunc.invert_oe = (i), \ 197 } 198 199 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 200 { \ 201 .name = (n), \ 202 .pins = (p), \ 203 .npins = ARRAY_SIZE((p)), \ 204 .altfunc.mode = (m), \ 205 .altfunc.invert_oe = (i), \ 206 .overrides = (o), \ 207 .noverrides = ARRAY_SIZE((o)), \ 208 } 209 210 #define FUNCTION(n, g) \ 211 { \ 212 .name = (n), \ 213 .groups = (g), \ 214 .ngroups = ARRAY_SIZE((g)), \ 215 } 216 217 #define GPIO_PINRANGE(start, end) \ 218 { \ 219 .base = (start), \ 220 .npins = (end) - (start) + 1, \ 221 } 222 223 static const struct pinctrl_pin_desc southwest_pins[] = { 224 PINCTRL_PIN(0, "FST_SPI_D2"), 225 PINCTRL_PIN(1, "FST_SPI_D0"), 226 PINCTRL_PIN(2, "FST_SPI_CLK"), 227 PINCTRL_PIN(3, "FST_SPI_D3"), 228 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 229 PINCTRL_PIN(5, "FST_SPI_D1"), 230 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 231 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 232 233 PINCTRL_PIN(15, "UART1_RTS_B"), 234 PINCTRL_PIN(16, "UART1_RXD"), 235 PINCTRL_PIN(17, "UART2_RXD"), 236 PINCTRL_PIN(18, "UART1_CTS_B"), 237 PINCTRL_PIN(19, "UART2_RTS_B"), 238 PINCTRL_PIN(20, "UART1_TXD"), 239 PINCTRL_PIN(21, "UART2_TXD"), 240 PINCTRL_PIN(22, "UART2_CTS_B"), 241 242 PINCTRL_PIN(30, "MF_HDA_CLK"), 243 PINCTRL_PIN(31, "MF_HDA_RSTB"), 244 PINCTRL_PIN(32, "MF_HDA_SDIO"), 245 PINCTRL_PIN(33, "MF_HDA_SDO"), 246 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 247 PINCTRL_PIN(35, "MF_HDA_SYNC"), 248 PINCTRL_PIN(36, "MF_HDA_SDI1"), 249 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 250 251 PINCTRL_PIN(45, "I2C5_SDA"), 252 PINCTRL_PIN(46, "I2C4_SDA"), 253 PINCTRL_PIN(47, "I2C6_SDA"), 254 PINCTRL_PIN(48, "I2C5_SCL"), 255 PINCTRL_PIN(49, "I2C_NFC_SDA"), 256 PINCTRL_PIN(50, "I2C4_SCL"), 257 PINCTRL_PIN(51, "I2C6_SCL"), 258 PINCTRL_PIN(52, "I2C_NFC_SCL"), 259 260 PINCTRL_PIN(60, "I2C1_SDA"), 261 PINCTRL_PIN(61, "I2C0_SDA"), 262 PINCTRL_PIN(62, "I2C2_SDA"), 263 PINCTRL_PIN(63, "I2C1_SCL"), 264 PINCTRL_PIN(64, "I2C3_SDA"), 265 PINCTRL_PIN(65, "I2C0_SCL"), 266 PINCTRL_PIN(66, "I2C2_SCL"), 267 PINCTRL_PIN(67, "I2C3_SCL"), 268 269 PINCTRL_PIN(75, "SATA_GP0"), 270 PINCTRL_PIN(76, "SATA_GP1"), 271 PINCTRL_PIN(77, "SATA_LEDN"), 272 PINCTRL_PIN(78, "SATA_GP2"), 273 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 274 PINCTRL_PIN(80, "SATA_GP3"), 275 PINCTRL_PIN(81, "MF_SMB_CLK"), 276 PINCTRL_PIN(82, "MF_SMB_DATA"), 277 278 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 279 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 280 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 281 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 282 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 283 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 284 PINCTRL_PIN(96, "GP_SSP_2_FS"), 285 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 286 }; 287 288 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 289 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 290 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 291 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 292 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 293 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 294 static const unsigned southwest_lpe_pins[] = { 295 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 296 }; 297 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 298 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 299 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 300 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 301 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 302 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 303 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 304 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 305 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 306 307 /* LPE I2S TXD pins need to have invert_oe set */ 308 static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 309 ALTERNATE_FUNCTION(30, 1, true), 310 ALTERNATE_FUNCTION(34, 1, true), 311 ALTERNATE_FUNCTION(97, 1, true), 312 }; 313 314 /* 315 * Two spi3 chipselects are available in different mode than the main spi3 316 * functionality, which is using mode 1. 317 */ 318 static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 319 ALTERNATE_FUNCTION(76, 3, false), 320 ALTERNATE_FUNCTION(80, 3, false), 321 }; 322 323 static const struct chv_pingroup southwest_groups[] = { 324 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 325 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 326 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 327 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 328 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 329 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 330 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 331 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 332 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 333 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 334 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 335 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 336 337 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 338 southwest_lpe_altfuncs), 339 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 340 southwest_spi3_altfuncs), 341 }; 342 343 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 344 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 345 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 346 static const char * const southwest_hda_groups[] = { "hda_grp" }; 347 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 348 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 349 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 350 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 351 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 352 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 353 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 354 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 355 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 356 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 357 358 /* 359 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 360 * enabled only as GPIOs. 361 */ 362 static const struct chv_function southwest_functions[] = { 363 FUNCTION("uart0", southwest_uart0_groups), 364 FUNCTION("uart1", southwest_uart1_groups), 365 FUNCTION("uart2", southwest_uart2_groups), 366 FUNCTION("hda", southwest_hda_groups), 367 FUNCTION("lpe", southwest_lpe_groups), 368 FUNCTION("i2c0", southwest_i2c0_groups), 369 FUNCTION("i2c1", southwest_i2c1_groups), 370 FUNCTION("i2c2", southwest_i2c2_groups), 371 FUNCTION("i2c3", southwest_i2c3_groups), 372 FUNCTION("i2c4", southwest_i2c4_groups), 373 FUNCTION("i2c5", southwest_i2c5_groups), 374 FUNCTION("i2c6", southwest_i2c6_groups), 375 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 376 FUNCTION("spi3", southwest_spi3_groups), 377 }; 378 379 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 380 GPIO_PINRANGE(0, 7), 381 GPIO_PINRANGE(15, 22), 382 GPIO_PINRANGE(30, 37), 383 GPIO_PINRANGE(45, 52), 384 GPIO_PINRANGE(60, 67), 385 GPIO_PINRANGE(75, 82), 386 GPIO_PINRANGE(90, 97), 387 }; 388 389 static const struct chv_community southwest_community = { 390 .uid = "1", 391 .pins = southwest_pins, 392 .npins = ARRAY_SIZE(southwest_pins), 393 .groups = southwest_groups, 394 .ngroups = ARRAY_SIZE(southwest_groups), 395 .functions = southwest_functions, 396 .nfunctions = ARRAY_SIZE(southwest_functions), 397 .gpio_ranges = southwest_gpio_ranges, 398 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 399 /* 400 * Southwest community can benerate GPIO interrupts only for the 401 * first 8 interrupts. The upper half (8-15) can only be used to 402 * trigger GPEs. 403 */ 404 .nirqs = 8, 405 .acpi_space_id = 0x91, 406 }; 407 408 static const struct pinctrl_pin_desc north_pins[] = { 409 PINCTRL_PIN(0, "GPIO_DFX_0"), 410 PINCTRL_PIN(1, "GPIO_DFX_3"), 411 PINCTRL_PIN(2, "GPIO_DFX_7"), 412 PINCTRL_PIN(3, "GPIO_DFX_1"), 413 PINCTRL_PIN(4, "GPIO_DFX_5"), 414 PINCTRL_PIN(5, "GPIO_DFX_4"), 415 PINCTRL_PIN(6, "GPIO_DFX_8"), 416 PINCTRL_PIN(7, "GPIO_DFX_2"), 417 PINCTRL_PIN(8, "GPIO_DFX_6"), 418 419 PINCTRL_PIN(15, "GPIO_SUS0"), 420 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 421 PINCTRL_PIN(17, "GPIO_SUS3"), 422 PINCTRL_PIN(18, "GPIO_SUS7"), 423 PINCTRL_PIN(19, "GPIO_SUS1"), 424 PINCTRL_PIN(20, "GPIO_SUS5"), 425 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 426 PINCTRL_PIN(22, "GPIO_SUS4"), 427 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 428 PINCTRL_PIN(24, "GPIO_SUS2"), 429 PINCTRL_PIN(25, "GPIO_SUS6"), 430 PINCTRL_PIN(26, "CX_PREQ_B"), 431 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 432 433 PINCTRL_PIN(30, "TRST_B"), 434 PINCTRL_PIN(31, "TCK"), 435 PINCTRL_PIN(32, "PROCHOT_B"), 436 PINCTRL_PIN(33, "SVIDO_DATA"), 437 PINCTRL_PIN(34, "TMS"), 438 PINCTRL_PIN(35, "CX_PRDY_B_2"), 439 PINCTRL_PIN(36, "TDO_2"), 440 PINCTRL_PIN(37, "CX_PRDY_B"), 441 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 442 PINCTRL_PIN(39, "TDO"), 443 PINCTRL_PIN(40, "SVIDO_CLK"), 444 PINCTRL_PIN(41, "TDI"), 445 446 PINCTRL_PIN(45, "GP_CAMERASB_05"), 447 PINCTRL_PIN(46, "GP_CAMERASB_02"), 448 PINCTRL_PIN(47, "GP_CAMERASB_08"), 449 PINCTRL_PIN(48, "GP_CAMERASB_00"), 450 PINCTRL_PIN(49, "GP_CAMERASB_06"), 451 PINCTRL_PIN(50, "GP_CAMERASB_10"), 452 PINCTRL_PIN(51, "GP_CAMERASB_03"), 453 PINCTRL_PIN(52, "GP_CAMERASB_09"), 454 PINCTRL_PIN(53, "GP_CAMERASB_01"), 455 PINCTRL_PIN(54, "GP_CAMERASB_07"), 456 PINCTRL_PIN(55, "GP_CAMERASB_11"), 457 PINCTRL_PIN(56, "GP_CAMERASB_04"), 458 459 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 460 PINCTRL_PIN(61, "HV_DDI0_HPD"), 461 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 462 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 463 PINCTRL_PIN(64, "HV_DDI1_HPD"), 464 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 465 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 466 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 467 PINCTRL_PIN(68, "HV_DDI2_HPD"), 468 PINCTRL_PIN(69, "PANEL1_VDDEN"), 469 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 470 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 471 PINCTRL_PIN(72, "PANEL0_VDDEN"), 472 }; 473 474 static const struct chv_gpio_pinrange north_gpio_ranges[] = { 475 GPIO_PINRANGE(0, 8), 476 GPIO_PINRANGE(15, 27), 477 GPIO_PINRANGE(30, 41), 478 GPIO_PINRANGE(45, 56), 479 GPIO_PINRANGE(60, 72), 480 }; 481 482 static const struct chv_community north_community = { 483 .uid = "2", 484 .pins = north_pins, 485 .npins = ARRAY_SIZE(north_pins), 486 .gpio_ranges = north_gpio_ranges, 487 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 488 /* 489 * North community can generate GPIO interrupts only for the first 490 * 8 interrupts. The upper half (8-15) can only be used to trigger 491 * GPEs. 492 */ 493 .nirqs = 8, 494 .acpi_space_id = 0x92, 495 }; 496 497 static const struct pinctrl_pin_desc east_pins[] = { 498 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 499 PINCTRL_PIN(1, "PMU_BATLOW_B"), 500 PINCTRL_PIN(2, "SUS_STAT_B"), 501 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 502 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 503 PINCTRL_PIN(5, "PMU_PLTRST_B"), 504 PINCTRL_PIN(6, "PMU_SUSCLK"), 505 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 506 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 507 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 508 PINCTRL_PIN(10, "PMU_WAKE_B"), 509 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 510 511 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 512 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 513 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 514 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 515 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 516 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 517 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 518 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 519 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 520 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 521 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 522 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 523 }; 524 525 static const struct chv_gpio_pinrange east_gpio_ranges[] = { 526 GPIO_PINRANGE(0, 11), 527 GPIO_PINRANGE(15, 26), 528 }; 529 530 static const struct chv_community east_community = { 531 .uid = "3", 532 .pins = east_pins, 533 .npins = ARRAY_SIZE(east_pins), 534 .gpio_ranges = east_gpio_ranges, 535 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 536 .nirqs = 16, 537 .acpi_space_id = 0x93, 538 }; 539 540 static const struct pinctrl_pin_desc southeast_pins[] = { 541 PINCTRL_PIN(0, "MF_PLT_CLK0"), 542 PINCTRL_PIN(1, "PWM1"), 543 PINCTRL_PIN(2, "MF_PLT_CLK1"), 544 PINCTRL_PIN(3, "MF_PLT_CLK4"), 545 PINCTRL_PIN(4, "MF_PLT_CLK3"), 546 PINCTRL_PIN(5, "PWM0"), 547 PINCTRL_PIN(6, "MF_PLT_CLK5"), 548 PINCTRL_PIN(7, "MF_PLT_CLK2"), 549 550 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 551 PINCTRL_PIN(16, "SDMMC1_CLK"), 552 PINCTRL_PIN(17, "SDMMC1_D0"), 553 PINCTRL_PIN(18, "SDMMC2_D1"), 554 PINCTRL_PIN(19, "SDMMC2_CLK"), 555 PINCTRL_PIN(20, "SDMMC1_D2"), 556 PINCTRL_PIN(21, "SDMMC2_D2"), 557 PINCTRL_PIN(22, "SDMMC2_CMD"), 558 PINCTRL_PIN(23, "SDMMC1_CMD"), 559 PINCTRL_PIN(24, "SDMMC1_D1"), 560 PINCTRL_PIN(25, "SDMMC2_D0"), 561 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 562 563 PINCTRL_PIN(30, "SDMMC3_D1"), 564 PINCTRL_PIN(31, "SDMMC3_CLK"), 565 PINCTRL_PIN(32, "SDMMC3_D3"), 566 PINCTRL_PIN(33, "SDMMC3_D2"), 567 PINCTRL_PIN(34, "SDMMC3_CMD"), 568 PINCTRL_PIN(35, "SDMMC3_D0"), 569 570 PINCTRL_PIN(45, "MF_LPC_AD2"), 571 PINCTRL_PIN(46, "LPC_CLKRUNB"), 572 PINCTRL_PIN(47, "MF_LPC_AD0"), 573 PINCTRL_PIN(48, "LPC_FRAMEB"), 574 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 575 PINCTRL_PIN(50, "MF_LPC_AD3"), 576 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 577 PINCTRL_PIN(52, "MF_LPC_AD1"), 578 579 PINCTRL_PIN(60, "SPI1_MISO"), 580 PINCTRL_PIN(61, "SPI1_CSO_B"), 581 PINCTRL_PIN(62, "SPI1_CLK"), 582 PINCTRL_PIN(63, "MMC1_D6"), 583 PINCTRL_PIN(64, "SPI1_MOSI"), 584 PINCTRL_PIN(65, "MMC1_D5"), 585 PINCTRL_PIN(66, "SPI1_CS1_B"), 586 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 587 PINCTRL_PIN(68, "MMC1_D7"), 588 PINCTRL_PIN(69, "MMC1_RCLK"), 589 590 PINCTRL_PIN(75, "USB_OC1_B"), 591 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 592 PINCTRL_PIN(77, "GPIO_ALERT"), 593 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 594 PINCTRL_PIN(79, "ILB_SERIRQ"), 595 PINCTRL_PIN(80, "USB_OC0_B"), 596 PINCTRL_PIN(81, "SDMMC3_CD_B"), 597 PINCTRL_PIN(82, "SPKR"), 598 PINCTRL_PIN(83, "SUSPWRDNACK"), 599 PINCTRL_PIN(84, "SPARE_PIN"), 600 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 601 }; 602 603 static const unsigned southeast_pwm0_pins[] = { 5 }; 604 static const unsigned southeast_pwm1_pins[] = { 1 }; 605 static const unsigned southeast_sdmmc1_pins[] = { 606 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 607 }; 608 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 609 static const unsigned southeast_sdmmc3_pins[] = { 610 30, 31, 32, 33, 34, 35, 78, 81, 85, 611 }; 612 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 613 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 614 615 static const struct chv_pingroup southeast_groups[] = { 616 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 617 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 618 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 619 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 620 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 621 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 622 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 623 }; 624 625 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 626 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 627 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 628 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 629 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 630 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 631 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 632 633 static const struct chv_function southeast_functions[] = { 634 FUNCTION("pwm0", southeast_pwm0_groups), 635 FUNCTION("pwm1", southeast_pwm1_groups), 636 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 637 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 638 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 639 FUNCTION("spi1", southeast_spi1_groups), 640 FUNCTION("spi2", southeast_spi2_groups), 641 }; 642 643 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 644 GPIO_PINRANGE(0, 7), 645 GPIO_PINRANGE(15, 26), 646 GPIO_PINRANGE(30, 35), 647 GPIO_PINRANGE(45, 52), 648 GPIO_PINRANGE(60, 69), 649 GPIO_PINRANGE(75, 85), 650 }; 651 652 static const struct chv_community southeast_community = { 653 .uid = "4", 654 .pins = southeast_pins, 655 .npins = ARRAY_SIZE(southeast_pins), 656 .groups = southeast_groups, 657 .ngroups = ARRAY_SIZE(southeast_groups), 658 .functions = southeast_functions, 659 .nfunctions = ARRAY_SIZE(southeast_functions), 660 .gpio_ranges = southeast_gpio_ranges, 661 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 662 .nirqs = 16, 663 .acpi_space_id = 0x94, 664 }; 665 666 static const struct chv_community *chv_communities[] = { 667 &southwest_community, 668 &north_community, 669 &east_community, 670 &southeast_community, 671 }; 672 673 /* 674 * Lock to serialize register accesses 675 * 676 * Due to a silicon issue, a shared lock must be used to prevent 677 * concurrent accesses across the 4 GPIO controllers. 678 * 679 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 680 * errata #CHT34, for further information. 681 */ 682 static DEFINE_RAW_SPINLOCK(chv_lock); 683 684 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 685 unsigned reg) 686 { 687 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 688 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 689 690 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 691 GPIO_REGS_SIZE * pad_no; 692 693 return pctrl->regs + offset + reg; 694 } 695 696 static void chv_writel(u32 value, void __iomem *reg) 697 { 698 writel(value, reg); 699 /* simple readback to confirm the bus transferring done */ 700 readl(reg); 701 } 702 703 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 704 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 705 { 706 void __iomem *reg; 707 708 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 709 return readl(reg) & CHV_PADCTRL1_CFGLOCK; 710 } 711 712 static int chv_get_groups_count(struct pinctrl_dev *pctldev) 713 { 714 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 715 716 return pctrl->community->ngroups; 717 } 718 719 static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 720 unsigned group) 721 { 722 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 723 724 return pctrl->community->groups[group].name; 725 } 726 727 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 728 const unsigned **pins, unsigned *npins) 729 { 730 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 731 732 *pins = pctrl->community->groups[group].pins; 733 *npins = pctrl->community->groups[group].npins; 734 return 0; 735 } 736 737 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 738 unsigned offset) 739 { 740 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 741 unsigned long flags; 742 u32 ctrl0, ctrl1; 743 bool locked; 744 745 raw_spin_lock_irqsave(&chv_lock, flags); 746 747 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 748 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 749 locked = chv_pad_locked(pctrl, offset); 750 751 raw_spin_unlock_irqrestore(&chv_lock, flags); 752 753 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 754 seq_puts(s, "GPIO "); 755 } else { 756 u32 mode; 757 758 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 759 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 760 761 seq_printf(s, "mode %d ", mode); 762 } 763 764 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 765 766 if (locked) 767 seq_puts(s, " [LOCKED]"); 768 } 769 770 static const struct pinctrl_ops chv_pinctrl_ops = { 771 .get_groups_count = chv_get_groups_count, 772 .get_group_name = chv_get_group_name, 773 .get_group_pins = chv_get_group_pins, 774 .pin_dbg_show = chv_pin_dbg_show, 775 }; 776 777 static int chv_get_functions_count(struct pinctrl_dev *pctldev) 778 { 779 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 780 781 return pctrl->community->nfunctions; 782 } 783 784 static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 785 unsigned function) 786 { 787 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 788 789 return pctrl->community->functions[function].name; 790 } 791 792 static int chv_get_function_groups(struct pinctrl_dev *pctldev, 793 unsigned function, 794 const char * const **groups, 795 unsigned * const ngroups) 796 { 797 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 798 799 *groups = pctrl->community->functions[function].groups; 800 *ngroups = pctrl->community->functions[function].ngroups; 801 return 0; 802 } 803 804 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 805 unsigned group) 806 { 807 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 808 const struct chv_pingroup *grp; 809 unsigned long flags; 810 int i; 811 812 grp = &pctrl->community->groups[group]; 813 814 raw_spin_lock_irqsave(&chv_lock, flags); 815 816 /* Check first that the pad is not locked */ 817 for (i = 0; i < grp->npins; i++) { 818 if (chv_pad_locked(pctrl, grp->pins[i])) { 819 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 820 grp->pins[i]); 821 raw_spin_unlock_irqrestore(&chv_lock, flags); 822 return -EBUSY; 823 } 824 } 825 826 for (i = 0; i < grp->npins; i++) { 827 const struct chv_alternate_function *altfunc = &grp->altfunc; 828 int pin = grp->pins[i]; 829 void __iomem *reg; 830 u32 value; 831 832 /* Check if there is pin-specific config */ 833 if (grp->overrides) { 834 int j; 835 836 for (j = 0; j < grp->noverrides; j++) { 837 if (grp->overrides[j].pin == pin) { 838 altfunc = &grp->overrides[j]; 839 break; 840 } 841 } 842 } 843 844 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 845 value = readl(reg); 846 /* Disable GPIO mode */ 847 value &= ~CHV_PADCTRL0_GPIOEN; 848 /* Set to desired mode */ 849 value &= ~CHV_PADCTRL0_PMODE_MASK; 850 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 851 chv_writel(value, reg); 852 853 /* Update for invert_oe */ 854 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 855 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 856 if (altfunc->invert_oe) 857 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 858 chv_writel(value, reg); 859 860 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 861 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 862 } 863 864 raw_spin_unlock_irqrestore(&chv_lock, flags); 865 866 return 0; 867 } 868 869 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 870 struct pinctrl_gpio_range *range, 871 unsigned offset) 872 { 873 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 874 unsigned long flags; 875 void __iomem *reg; 876 u32 value; 877 878 raw_spin_lock_irqsave(&chv_lock, flags); 879 880 if (chv_pad_locked(pctrl, offset)) { 881 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 882 if (!(value & CHV_PADCTRL0_GPIOEN)) { 883 /* Locked so cannot enable */ 884 raw_spin_unlock_irqrestore(&chv_lock, flags); 885 return -EBUSY; 886 } 887 } else { 888 int i; 889 890 /* Reset the interrupt mapping */ 891 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 892 if (pctrl->intr_lines[i] == offset) { 893 pctrl->intr_lines[i] = 0; 894 break; 895 } 896 } 897 898 /* Disable interrupt generation */ 899 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 900 value = readl(reg); 901 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 902 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 903 chv_writel(value, reg); 904 905 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 906 value = readl(reg); 907 908 /* 909 * If the pin is in HiZ mode (both TX and RX buffers are 910 * disabled) we turn it to be input now. 911 */ 912 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 913 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 914 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 915 value |= CHV_PADCTRL0_GPIOCFG_GPI << 916 CHV_PADCTRL0_GPIOCFG_SHIFT; 917 } 918 919 /* Switch to a GPIO mode */ 920 value |= CHV_PADCTRL0_GPIOEN; 921 chv_writel(value, reg); 922 } 923 924 raw_spin_unlock_irqrestore(&chv_lock, flags); 925 926 return 0; 927 } 928 929 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 930 struct pinctrl_gpio_range *range, 931 unsigned offset) 932 { 933 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 934 unsigned long flags; 935 void __iomem *reg; 936 u32 value; 937 938 raw_spin_lock_irqsave(&chv_lock, flags); 939 940 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 941 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 942 chv_writel(value, reg); 943 944 raw_spin_unlock_irqrestore(&chv_lock, flags); 945 } 946 947 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 948 struct pinctrl_gpio_range *range, 949 unsigned offset, bool input) 950 { 951 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 952 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 953 unsigned long flags; 954 u32 ctrl0; 955 956 raw_spin_lock_irqsave(&chv_lock, flags); 957 958 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 959 if (input) 960 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 961 else 962 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 963 chv_writel(ctrl0, reg); 964 965 raw_spin_unlock_irqrestore(&chv_lock, flags); 966 967 return 0; 968 } 969 970 static const struct pinmux_ops chv_pinmux_ops = { 971 .get_functions_count = chv_get_functions_count, 972 .get_function_name = chv_get_function_name, 973 .get_function_groups = chv_get_function_groups, 974 .set_mux = chv_pinmux_set_mux, 975 .gpio_request_enable = chv_gpio_request_enable, 976 .gpio_disable_free = chv_gpio_disable_free, 977 .gpio_set_direction = chv_gpio_set_direction, 978 }; 979 980 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 981 unsigned long *config) 982 { 983 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 984 enum pin_config_param param = pinconf_to_config_param(*config); 985 unsigned long flags; 986 u32 ctrl0, ctrl1; 987 u16 arg = 0; 988 u32 term; 989 990 raw_spin_lock_irqsave(&chv_lock, flags); 991 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 992 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 993 raw_spin_unlock_irqrestore(&chv_lock, flags); 994 995 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 996 997 switch (param) { 998 case PIN_CONFIG_BIAS_DISABLE: 999 if (term) 1000 return -EINVAL; 1001 break; 1002 1003 case PIN_CONFIG_BIAS_PULL_UP: 1004 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 1005 return -EINVAL; 1006 1007 switch (term) { 1008 case CHV_PADCTRL0_TERM_20K: 1009 arg = 20000; 1010 break; 1011 case CHV_PADCTRL0_TERM_5K: 1012 arg = 5000; 1013 break; 1014 case CHV_PADCTRL0_TERM_1K: 1015 arg = 1000; 1016 break; 1017 } 1018 1019 break; 1020 1021 case PIN_CONFIG_BIAS_PULL_DOWN: 1022 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 1023 return -EINVAL; 1024 1025 switch (term) { 1026 case CHV_PADCTRL0_TERM_20K: 1027 arg = 20000; 1028 break; 1029 case CHV_PADCTRL0_TERM_5K: 1030 arg = 5000; 1031 break; 1032 } 1033 1034 break; 1035 1036 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1037 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 1038 return -EINVAL; 1039 break; 1040 1041 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 1042 u32 cfg; 1043 1044 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1045 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1046 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 1047 return -EINVAL; 1048 1049 break; 1050 } 1051 1052 default: 1053 return -ENOTSUPP; 1054 } 1055 1056 *config = pinconf_to_config_packed(param, arg); 1057 return 0; 1058 } 1059 1060 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 1061 enum pin_config_param param, u32 arg) 1062 { 1063 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1064 unsigned long flags; 1065 u32 ctrl0, pull; 1066 1067 raw_spin_lock_irqsave(&chv_lock, flags); 1068 ctrl0 = readl(reg); 1069 1070 switch (param) { 1071 case PIN_CONFIG_BIAS_DISABLE: 1072 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1073 break; 1074 1075 case PIN_CONFIG_BIAS_PULL_UP: 1076 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1077 1078 switch (arg) { 1079 case 1000: 1080 /* For 1k there is only pull up */ 1081 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 1082 break; 1083 case 5000: 1084 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1085 break; 1086 case 20000: 1087 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1088 break; 1089 default: 1090 raw_spin_unlock_irqrestore(&chv_lock, flags); 1091 return -EINVAL; 1092 } 1093 1094 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1095 break; 1096 1097 case PIN_CONFIG_BIAS_PULL_DOWN: 1098 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1099 1100 switch (arg) { 1101 case 5000: 1102 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1103 break; 1104 case 20000: 1105 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1106 break; 1107 default: 1108 raw_spin_unlock_irqrestore(&chv_lock, flags); 1109 return -EINVAL; 1110 } 1111 1112 ctrl0 |= pull; 1113 break; 1114 1115 default: 1116 raw_spin_unlock_irqrestore(&chv_lock, flags); 1117 return -EINVAL; 1118 } 1119 1120 chv_writel(ctrl0, reg); 1121 raw_spin_unlock_irqrestore(&chv_lock, flags); 1122 1123 return 0; 1124 } 1125 1126 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1127 bool enable) 1128 { 1129 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1130 unsigned long flags; 1131 u32 ctrl1; 1132 1133 raw_spin_lock_irqsave(&chv_lock, flags); 1134 ctrl1 = readl(reg); 1135 1136 if (enable) 1137 ctrl1 |= CHV_PADCTRL1_ODEN; 1138 else 1139 ctrl1 &= ~CHV_PADCTRL1_ODEN; 1140 1141 chv_writel(ctrl1, reg); 1142 raw_spin_unlock_irqrestore(&chv_lock, flags); 1143 1144 return 0; 1145 } 1146 1147 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1148 unsigned long *configs, unsigned nconfigs) 1149 { 1150 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1151 enum pin_config_param param; 1152 int i, ret; 1153 u32 arg; 1154 1155 if (chv_pad_locked(pctrl, pin)) 1156 return -EBUSY; 1157 1158 for (i = 0; i < nconfigs; i++) { 1159 param = pinconf_to_config_param(configs[i]); 1160 arg = pinconf_to_config_argument(configs[i]); 1161 1162 switch (param) { 1163 case PIN_CONFIG_BIAS_DISABLE: 1164 case PIN_CONFIG_BIAS_PULL_UP: 1165 case PIN_CONFIG_BIAS_PULL_DOWN: 1166 ret = chv_config_set_pull(pctrl, pin, param, arg); 1167 if (ret) 1168 return ret; 1169 break; 1170 1171 case PIN_CONFIG_DRIVE_PUSH_PULL: 1172 ret = chv_config_set_oden(pctrl, pin, false); 1173 if (ret) 1174 return ret; 1175 break; 1176 1177 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1178 ret = chv_config_set_oden(pctrl, pin, true); 1179 if (ret) 1180 return ret; 1181 break; 1182 1183 default: 1184 return -ENOTSUPP; 1185 } 1186 1187 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 1188 param, arg); 1189 } 1190 1191 return 0; 1192 } 1193 1194 static int chv_config_group_get(struct pinctrl_dev *pctldev, 1195 unsigned int group, 1196 unsigned long *config) 1197 { 1198 const unsigned int *pins; 1199 unsigned int npins; 1200 int ret; 1201 1202 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1203 if (ret) 1204 return ret; 1205 1206 ret = chv_config_get(pctldev, pins[0], config); 1207 if (ret) 1208 return ret; 1209 1210 return 0; 1211 } 1212 1213 static int chv_config_group_set(struct pinctrl_dev *pctldev, 1214 unsigned int group, unsigned long *configs, 1215 unsigned int num_configs) 1216 { 1217 const unsigned int *pins; 1218 unsigned int npins; 1219 int i, ret; 1220 1221 ret = chv_get_group_pins(pctldev, group, &pins, &npins); 1222 if (ret) 1223 return ret; 1224 1225 for (i = 0; i < npins; i++) { 1226 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1227 if (ret) 1228 return ret; 1229 } 1230 1231 return 0; 1232 } 1233 1234 static const struct pinconf_ops chv_pinconf_ops = { 1235 .is_generic = true, 1236 .pin_config_set = chv_config_set, 1237 .pin_config_get = chv_config_get, 1238 .pin_config_group_get = chv_config_group_get, 1239 .pin_config_group_set = chv_config_group_set, 1240 }; 1241 1242 static struct pinctrl_desc chv_pinctrl_desc = { 1243 .pctlops = &chv_pinctrl_ops, 1244 .pmxops = &chv_pinmux_ops, 1245 .confops = &chv_pinconf_ops, 1246 .owner = THIS_MODULE, 1247 }; 1248 1249 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 1250 { 1251 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1252 unsigned long flags; 1253 u32 ctrl0, cfg; 1254 1255 raw_spin_lock_irqsave(&chv_lock, flags); 1256 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 1257 raw_spin_unlock_irqrestore(&chv_lock, flags); 1258 1259 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1260 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1261 1262 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1263 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1264 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1265 } 1266 1267 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1268 { 1269 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1270 unsigned long flags; 1271 void __iomem *reg; 1272 u32 ctrl0; 1273 1274 raw_spin_lock_irqsave(&chv_lock, flags); 1275 1276 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 1277 ctrl0 = readl(reg); 1278 1279 if (value) 1280 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1281 else 1282 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1283 1284 chv_writel(ctrl0, reg); 1285 1286 raw_spin_unlock_irqrestore(&chv_lock, flags); 1287 } 1288 1289 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1290 { 1291 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1292 u32 ctrl0, direction; 1293 unsigned long flags; 1294 1295 raw_spin_lock_irqsave(&chv_lock, flags); 1296 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 1297 raw_spin_unlock_irqrestore(&chv_lock, flags); 1298 1299 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1300 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1301 1302 return direction != CHV_PADCTRL0_GPIOCFG_GPO; 1303 } 1304 1305 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1306 { 1307 return pinctrl_gpio_direction_input(chip->base + offset); 1308 } 1309 1310 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1311 int value) 1312 { 1313 chv_gpio_set(chip, offset, value); 1314 return pinctrl_gpio_direction_output(chip->base + offset); 1315 } 1316 1317 static const struct gpio_chip chv_gpio_chip = { 1318 .owner = THIS_MODULE, 1319 .request = gpiochip_generic_request, 1320 .free = gpiochip_generic_free, 1321 .get_direction = chv_gpio_get_direction, 1322 .direction_input = chv_gpio_direction_input, 1323 .direction_output = chv_gpio_direction_output, 1324 .get = chv_gpio_get, 1325 .set = chv_gpio_set, 1326 }; 1327 1328 static void chv_gpio_irq_ack(struct irq_data *d) 1329 { 1330 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1331 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1332 int pin = irqd_to_hwirq(d); 1333 u32 intr_line; 1334 1335 raw_spin_lock(&chv_lock); 1336 1337 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1338 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1339 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1340 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 1341 1342 raw_spin_unlock(&chv_lock); 1343 } 1344 1345 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1346 { 1347 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1348 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1349 int pin = irqd_to_hwirq(d); 1350 u32 value, intr_line; 1351 unsigned long flags; 1352 1353 raw_spin_lock_irqsave(&chv_lock, flags); 1354 1355 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1356 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1357 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1358 1359 value = readl(pctrl->regs + CHV_INTMASK); 1360 if (mask) 1361 value &= ~BIT(intr_line); 1362 else 1363 value |= BIT(intr_line); 1364 chv_writel(value, pctrl->regs + CHV_INTMASK); 1365 1366 raw_spin_unlock_irqrestore(&chv_lock, flags); 1367 } 1368 1369 static void chv_gpio_irq_mask(struct irq_data *d) 1370 { 1371 chv_gpio_irq_mask_unmask(d, true); 1372 } 1373 1374 static void chv_gpio_irq_unmask(struct irq_data *d) 1375 { 1376 chv_gpio_irq_mask_unmask(d, false); 1377 } 1378 1379 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1380 { 1381 /* 1382 * Check if the interrupt has been requested with 0 as triggering 1383 * type. In that case it is assumed that the current values 1384 * programmed to the hardware are used (e.g BIOS configured 1385 * defaults). 1386 * 1387 * In that case ->irq_set_type() will never be called so we need to 1388 * read back the values from hardware now, set correct flow handler 1389 * and update mappings before the interrupt is being used. 1390 */ 1391 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1393 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1394 unsigned pin = irqd_to_hwirq(d); 1395 irq_flow_handler_t handler; 1396 unsigned long flags; 1397 u32 intsel, value; 1398 1399 raw_spin_lock_irqsave(&chv_lock, flags); 1400 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1401 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1402 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1403 1404 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1405 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1406 handler = handle_level_irq; 1407 else 1408 handler = handle_edge_irq; 1409 1410 if (!pctrl->intr_lines[intsel]) { 1411 irq_set_handler_locked(d, handler); 1412 pctrl->intr_lines[intsel] = pin; 1413 } 1414 raw_spin_unlock_irqrestore(&chv_lock, flags); 1415 } 1416 1417 chv_gpio_irq_unmask(d); 1418 return 0; 1419 } 1420 1421 static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 1422 { 1423 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1424 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1425 unsigned pin = irqd_to_hwirq(d); 1426 unsigned long flags; 1427 u32 value; 1428 1429 raw_spin_lock_irqsave(&chv_lock, flags); 1430 1431 /* 1432 * Pins which can be used as shared interrupt are configured in 1433 * BIOS. Driver trusts BIOS configurations and assigns different 1434 * handler according to the irq type. 1435 * 1436 * Driver needs to save the mapping between each pin and 1437 * its interrupt line. 1438 * 1. If the pin cfg is locked in BIOS: 1439 * Trust BIOS has programmed IntWakeCfg bits correctly, 1440 * driver just needs to save the mapping. 1441 * 2. If the pin cfg is not locked in BIOS: 1442 * Driver programs the IntWakeCfg bits and save the mapping. 1443 */ 1444 if (!chv_pad_locked(pctrl, pin)) { 1445 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1446 1447 value = readl(reg); 1448 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1449 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1450 1451 if (type & IRQ_TYPE_EDGE_BOTH) { 1452 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1453 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1454 else if (type & IRQ_TYPE_EDGE_RISING) 1455 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1456 else if (type & IRQ_TYPE_EDGE_FALLING) 1457 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1458 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1459 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1460 if (type & IRQ_TYPE_LEVEL_LOW) 1461 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1462 } 1463 1464 chv_writel(value, reg); 1465 } 1466 1467 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1468 value &= CHV_PADCTRL0_INTSEL_MASK; 1469 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1470 1471 pctrl->intr_lines[value] = pin; 1472 1473 if (type & IRQ_TYPE_EDGE_BOTH) 1474 irq_set_handler_locked(d, handle_edge_irq); 1475 else if (type & IRQ_TYPE_LEVEL_MASK) 1476 irq_set_handler_locked(d, handle_level_irq); 1477 1478 raw_spin_unlock_irqrestore(&chv_lock, flags); 1479 1480 return 0; 1481 } 1482 1483 static struct irq_chip chv_gpio_irqchip = { 1484 .name = "chv-gpio", 1485 .irq_startup = chv_gpio_irq_startup, 1486 .irq_ack = chv_gpio_irq_ack, 1487 .irq_mask = chv_gpio_irq_mask, 1488 .irq_unmask = chv_gpio_irq_unmask, 1489 .irq_set_type = chv_gpio_irq_type, 1490 .flags = IRQCHIP_SKIP_SET_WAKE, 1491 }; 1492 1493 static void chv_gpio_irq_handler(struct irq_desc *desc) 1494 { 1495 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1496 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1497 struct irq_chip *chip = irq_desc_get_chip(desc); 1498 unsigned long pending; 1499 u32 intr_line; 1500 1501 chained_irq_enter(chip, desc); 1502 1503 pending = readl(pctrl->regs + CHV_INTSTAT); 1504 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { 1505 unsigned irq, offset; 1506 1507 offset = pctrl->intr_lines[intr_line]; 1508 irq = irq_find_mapping(gc->irq.domain, offset); 1509 generic_handle_irq(irq); 1510 } 1511 1512 chained_irq_exit(chip, desc); 1513 } 1514 1515 /* 1516 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1517 * tables. Since we leave GPIOs that are not capable of generating 1518 * interrupts out of the irqdomain the numbering will be different and 1519 * cause devices using the hardcoded IRQ numbers fail. In order not to 1520 * break such machines we will only mask pins from irqdomain if the machine 1521 * is not listed below. 1522 */ 1523 static const struct dmi_system_id chv_no_valid_mask[] = { 1524 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1525 { 1526 .ident = "Intel_Strago based Chromebooks (All models)", 1527 .matches = { 1528 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1529 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1530 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1531 }, 1532 }, 1533 { 1534 .ident = "HP Chromebook 11 G5 (Setzer)", 1535 .matches = { 1536 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1537 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1538 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1539 }, 1540 }, 1541 { 1542 .ident = "Acer Chromebook R11 (Cyan)", 1543 .matches = { 1544 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1545 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1546 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1547 }, 1548 }, 1549 { 1550 .ident = "Samsung Chromebook 3 (Celes)", 1551 .matches = { 1552 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1553 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1554 DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 1555 }, 1556 }, 1557 {} 1558 }; 1559 1560 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 1561 { 1562 const struct chv_gpio_pinrange *range; 1563 struct gpio_chip *chip = &pctrl->chip; 1564 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1565 const struct chv_community *community = pctrl->community; 1566 int ret, i, irq_base; 1567 1568 *chip = chv_gpio_chip; 1569 1570 chip->ngpio = community->pins[community->npins - 1].number + 1; 1571 chip->label = dev_name(pctrl->dev); 1572 chip->parent = pctrl->dev; 1573 chip->base = -1; 1574 chip->irq.need_valid_mask = need_valid_mask; 1575 1576 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1577 if (ret) { 1578 dev_err(pctrl->dev, "Failed to register gpiochip\n"); 1579 return ret; 1580 } 1581 1582 for (i = 0; i < community->ngpio_ranges; i++) { 1583 range = &community->gpio_ranges[i]; 1584 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), 1585 range->base, range->base, 1586 range->npins); 1587 if (ret) { 1588 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1589 return ret; 1590 } 1591 } 1592 1593 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1594 for (i = 0; i < community->npins; i++) { 1595 const struct pinctrl_pin_desc *desc; 1596 u32 intsel; 1597 1598 desc = &community->pins[i]; 1599 1600 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); 1601 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1602 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1603 1604 if (need_valid_mask && intsel >= community->nirqs) 1605 clear_bit(i, chip->irq.valid_mask); 1606 } 1607 1608 /* 1609 * The same set of machines in chv_no_valid_mask[] have incorrectly 1610 * configured GPIOs that generate spurious interrupts so we use 1611 * this same list to apply another quirk for them. 1612 * 1613 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1614 */ 1615 if (!need_valid_mask) { 1616 /* 1617 * Mask all interrupts the community is able to generate 1618 * but leave the ones that can only generate GPEs unmasked. 1619 */ 1620 chv_writel(GENMASK(31, pctrl->community->nirqs), 1621 pctrl->regs + CHV_INTMASK); 1622 } 1623 1624 /* Clear all interrupts */ 1625 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1626 1627 if (!need_valid_mask) { 1628 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, 1629 community->npins, NUMA_NO_NODE); 1630 if (irq_base < 0) { 1631 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); 1632 return irq_base; 1633 } 1634 } 1635 1636 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1637 handle_bad_irq, IRQ_TYPE_NONE); 1638 if (ret) { 1639 dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1640 return ret; 1641 } 1642 1643 if (!need_valid_mask) { 1644 for (i = 0; i < community->ngpio_ranges; i++) { 1645 range = &community->gpio_ranges[i]; 1646 1647 irq_domain_associate_many(chip->irq.domain, irq_base, 1648 range->base, range->npins); 1649 irq_base += range->npins; 1650 } 1651 } 1652 1653 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 1654 chv_gpio_irq_handler); 1655 return 0; 1656 } 1657 1658 static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1659 acpi_physical_address address, u32 bits, u64 *value, 1660 void *handler_context, void *region_context) 1661 { 1662 struct chv_pinctrl *pctrl = region_context; 1663 unsigned long flags; 1664 acpi_status ret = AE_OK; 1665 1666 raw_spin_lock_irqsave(&chv_lock, flags); 1667 1668 if (function == ACPI_WRITE) 1669 chv_writel((u32)(*value), pctrl->regs + (u32)address); 1670 else if (function == ACPI_READ) 1671 *value = readl(pctrl->regs + (u32)address); 1672 else 1673 ret = AE_BAD_PARAMETER; 1674 1675 raw_spin_unlock_irqrestore(&chv_lock, flags); 1676 1677 return ret; 1678 } 1679 1680 static int chv_pinctrl_probe(struct platform_device *pdev) 1681 { 1682 struct chv_pinctrl *pctrl; 1683 struct acpi_device *adev; 1684 struct resource *res; 1685 acpi_status status; 1686 int ret, irq, i; 1687 1688 adev = ACPI_COMPANION(&pdev->dev); 1689 if (!adev) 1690 return -ENODEV; 1691 1692 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1693 if (!pctrl) 1694 return -ENOMEM; 1695 1696 for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 1697 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 1698 pctrl->community = chv_communities[i]; 1699 break; 1700 } 1701 if (i == ARRAY_SIZE(chv_communities)) 1702 return -ENODEV; 1703 1704 pctrl->dev = &pdev->dev; 1705 1706 #ifdef CONFIG_PM_SLEEP 1707 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 1708 pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 1709 GFP_KERNEL); 1710 if (!pctrl->saved_pin_context) 1711 return -ENOMEM; 1712 #endif 1713 1714 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1715 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 1716 if (IS_ERR(pctrl->regs)) 1717 return PTR_ERR(pctrl->regs); 1718 1719 irq = platform_get_irq(pdev, 0); 1720 if (irq < 0) { 1721 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1722 return irq; 1723 } 1724 1725 pctrl->pctldesc = chv_pinctrl_desc; 1726 pctrl->pctldesc.name = dev_name(&pdev->dev); 1727 pctrl->pctldesc.pins = pctrl->community->pins; 1728 pctrl->pctldesc.npins = pctrl->community->npins; 1729 1730 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1731 pctrl); 1732 if (IS_ERR(pctrl->pctldev)) { 1733 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1734 return PTR_ERR(pctrl->pctldev); 1735 } 1736 1737 ret = chv_gpio_probe(pctrl, irq); 1738 if (ret) 1739 return ret; 1740 1741 status = acpi_install_address_space_handler(adev->handle, 1742 pctrl->community->acpi_space_id, 1743 chv_pinctrl_mmio_access_handler, 1744 NULL, pctrl); 1745 if (ACPI_FAILURE(status)) 1746 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n"); 1747 1748 platform_set_drvdata(pdev, pctrl); 1749 1750 return 0; 1751 } 1752 1753 static int chv_pinctrl_remove(struct platform_device *pdev) 1754 { 1755 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1756 1757 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), 1758 pctrl->community->acpi_space_id, 1759 chv_pinctrl_mmio_access_handler); 1760 1761 return 0; 1762 } 1763 1764 #ifdef CONFIG_PM_SLEEP 1765 static int chv_pinctrl_suspend_noirq(struct device *dev) 1766 { 1767 struct platform_device *pdev = to_platform_device(dev); 1768 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1769 unsigned long flags; 1770 int i; 1771 1772 raw_spin_lock_irqsave(&chv_lock, flags); 1773 1774 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 1775 1776 for (i = 0; i < pctrl->community->npins; i++) { 1777 const struct pinctrl_pin_desc *desc; 1778 struct chv_pin_context *ctx; 1779 void __iomem *reg; 1780 1781 desc = &pctrl->community->pins[i]; 1782 if (chv_pad_locked(pctrl, desc->number)) 1783 continue; 1784 1785 ctx = &pctrl->saved_pin_context[i]; 1786 1787 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1788 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1789 1790 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1791 ctx->padctrl1 = readl(reg); 1792 } 1793 1794 raw_spin_unlock_irqrestore(&chv_lock, flags); 1795 1796 return 0; 1797 } 1798 1799 static int chv_pinctrl_resume_noirq(struct device *dev) 1800 { 1801 struct platform_device *pdev = to_platform_device(dev); 1802 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1803 unsigned long flags; 1804 int i; 1805 1806 raw_spin_lock_irqsave(&chv_lock, flags); 1807 1808 /* 1809 * Mask all interrupts before restoring per-pin configuration 1810 * registers because we don't know in which state BIOS left them 1811 * upon exiting suspend. 1812 */ 1813 chv_writel(0, pctrl->regs + CHV_INTMASK); 1814 1815 for (i = 0; i < pctrl->community->npins; i++) { 1816 const struct pinctrl_pin_desc *desc; 1817 const struct chv_pin_context *ctx; 1818 void __iomem *reg; 1819 u32 val; 1820 1821 desc = &pctrl->community->pins[i]; 1822 if (chv_pad_locked(pctrl, desc->number)) 1823 continue; 1824 1825 ctx = &pctrl->saved_pin_context[i]; 1826 1827 /* Only restore if our saved state differs from the current */ 1828 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1829 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1830 if (ctx->padctrl0 != val) { 1831 chv_writel(ctx->padctrl0, reg); 1832 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 1833 desc->number, readl(reg)); 1834 } 1835 1836 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1837 val = readl(reg); 1838 if (ctx->padctrl1 != val) { 1839 chv_writel(ctx->padctrl1, reg); 1840 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 1841 desc->number, readl(reg)); 1842 } 1843 } 1844 1845 /* 1846 * Now that all pins are restored to known state, we can restore 1847 * the interrupt mask register as well. 1848 */ 1849 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1850 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 1851 1852 raw_spin_unlock_irqrestore(&chv_lock, flags); 1853 1854 return 0; 1855 } 1856 #endif 1857 1858 static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1859 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1860 chv_pinctrl_resume_noirq) 1861 }; 1862 1863 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1864 { "INT33FF" }, 1865 { } 1866 }; 1867 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1868 1869 static struct platform_driver chv_pinctrl_driver = { 1870 .probe = chv_pinctrl_probe, 1871 .remove = chv_pinctrl_remove, 1872 .driver = { 1873 .name = "cherryview-pinctrl", 1874 .pm = &chv_pinctrl_pm_ops, 1875 .acpi_match_table = chv_pinctrl_acpi_match, 1876 }, 1877 }; 1878 1879 static int __init chv_pinctrl_init(void) 1880 { 1881 return platform_driver_register(&chv_pinctrl_driver); 1882 } 1883 subsys_initcall(chv_pinctrl_init); 1884 1885 static void __exit chv_pinctrl_exit(void) 1886 { 1887 platform_driver_unregister(&chv_pinctrl_driver); 1888 } 1889 module_exit(chv_pinctrl_exit); 1890 1891 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1892 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1893 MODULE_LICENSE("GPL v2"); 1894