1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Cherryview/Braswell pinctrl driver
4  *
5  * Copyright (C) 2014, 2020 Intel Corporation
6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7  *
8  * This driver is based on the original Cherryview GPIO driver by
9  *   Ning Li <ning.li@intel.com>
10  *   Alan Cox <alan@linux.intel.com>
11  */
12 
13 #include <linux/acpi.h>
14 #include <linux/dmi.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/types.h>
20 
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 
26 #include "pinctrl-intel.h"
27 
28 #define CHV_INTSTAT			0x300
29 #define CHV_INTMASK			0x380
30 
31 #define FAMILY_PAD_REGS_OFF		0x4400
32 #define FAMILY_PAD_REGS_SIZE		0x400
33 #define MAX_FAMILY_PAD_GPIO_NO		15
34 #define GPIO_REGS_SIZE			8
35 
36 #define CHV_PADCTRL0			0x000
37 #define CHV_PADCTRL0_INTSEL_SHIFT	28
38 #define CHV_PADCTRL0_INTSEL_MASK	GENMASK(31, 28)
39 #define CHV_PADCTRL0_TERM_UP		BIT(23)
40 #define CHV_PADCTRL0_TERM_SHIFT		20
41 #define CHV_PADCTRL0_TERM_MASK		GENMASK(22, 20)
42 #define CHV_PADCTRL0_TERM_20K		1
43 #define CHV_PADCTRL0_TERM_5K		2
44 #define CHV_PADCTRL0_TERM_1K		4
45 #define CHV_PADCTRL0_PMODE_SHIFT	16
46 #define CHV_PADCTRL0_PMODE_MASK		GENMASK(19, 16)
47 #define CHV_PADCTRL0_GPIOEN		BIT(15)
48 #define CHV_PADCTRL0_GPIOCFG_SHIFT	8
49 #define CHV_PADCTRL0_GPIOCFG_MASK	GENMASK(10, 8)
50 #define CHV_PADCTRL0_GPIOCFG_GPIO	0
51 #define CHV_PADCTRL0_GPIOCFG_GPO	1
52 #define CHV_PADCTRL0_GPIOCFG_GPI	2
53 #define CHV_PADCTRL0_GPIOCFG_HIZ	3
54 #define CHV_PADCTRL0_GPIOTXSTATE	BIT(1)
55 #define CHV_PADCTRL0_GPIORXSTATE	BIT(0)
56 
57 #define CHV_PADCTRL1			0x004
58 #define CHV_PADCTRL1_CFGLOCK		BIT(31)
59 #define CHV_PADCTRL1_INVRXTX_SHIFT	4
60 #define CHV_PADCTRL1_INVRXTX_MASK	GENMASK(7, 4)
61 #define CHV_PADCTRL1_INVRXTX_TXDATA	BIT(7)
62 #define CHV_PADCTRL1_INVRXTX_RXDATA	BIT(6)
63 #define CHV_PADCTRL1_INVRXTX_TXENABLE	BIT(5)
64 #define CHV_PADCTRL1_ODEN		BIT(3)
65 #define CHV_PADCTRL1_INTWAKECFG_MASK	GENMASK(2, 0)
66 #define CHV_PADCTRL1_INTWAKECFG_FALLING	1
67 #define CHV_PADCTRL1_INTWAKECFG_RISING	2
68 #define CHV_PADCTRL1_INTWAKECFG_BOTH	3
69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL	4
70 
71 struct intel_pad_context {
72 	u32 padctrl0;
73 	u32 padctrl1;
74 };
75 
76 #define CHV_INVALID_HWIRQ	((unsigned int)INVALID_HWIRQ)
77 
78 /**
79  * struct intel_community_context - community context for Cherryview
80  * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
81  * @saved_intmask: Interrupt mask saved for system sleep
82  */
83 struct intel_community_context {
84 	unsigned int intr_lines[16];
85 	u32 saved_intmask;
86 };
87 
88 #define	PINMODE_INVERT_OE	BIT(15)
89 
90 #define PINMODE(m, i)		((m) | ((i) * PINMODE_INVERT_OE))
91 
92 #define CHV_GPP(start, end)			\
93 	{					\
94 		.base = (start),		\
95 		.size = (end) - (start) + 1,	\
96 	}
97 
98 #define CHV_COMMUNITY(g, i, a)			\
99 	{					\
100 		.gpps = (g),			\
101 		.ngpps = ARRAY_SIZE(g),		\
102 		.nirqs = (i),			\
103 		.acpi_space_id = (a),		\
104 	}
105 
106 static const struct pinctrl_pin_desc southwest_pins[] = {
107 	PINCTRL_PIN(0, "FST_SPI_D2"),
108 	PINCTRL_PIN(1, "FST_SPI_D0"),
109 	PINCTRL_PIN(2, "FST_SPI_CLK"),
110 	PINCTRL_PIN(3, "FST_SPI_D3"),
111 	PINCTRL_PIN(4, "FST_SPI_CS1_B"),
112 	PINCTRL_PIN(5, "FST_SPI_D1"),
113 	PINCTRL_PIN(6, "FST_SPI_CS0_B"),
114 	PINCTRL_PIN(7, "FST_SPI_CS2_B"),
115 
116 	PINCTRL_PIN(15, "UART1_RTS_B"),
117 	PINCTRL_PIN(16, "UART1_RXD"),
118 	PINCTRL_PIN(17, "UART2_RXD"),
119 	PINCTRL_PIN(18, "UART1_CTS_B"),
120 	PINCTRL_PIN(19, "UART2_RTS_B"),
121 	PINCTRL_PIN(20, "UART1_TXD"),
122 	PINCTRL_PIN(21, "UART2_TXD"),
123 	PINCTRL_PIN(22, "UART2_CTS_B"),
124 
125 	PINCTRL_PIN(30, "MF_HDA_CLK"),
126 	PINCTRL_PIN(31, "MF_HDA_RSTB"),
127 	PINCTRL_PIN(32, "MF_HDA_SDIO"),
128 	PINCTRL_PIN(33, "MF_HDA_SDO"),
129 	PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
130 	PINCTRL_PIN(35, "MF_HDA_SYNC"),
131 	PINCTRL_PIN(36, "MF_HDA_SDI1"),
132 	PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
133 
134 	PINCTRL_PIN(45, "I2C5_SDA"),
135 	PINCTRL_PIN(46, "I2C4_SDA"),
136 	PINCTRL_PIN(47, "I2C6_SDA"),
137 	PINCTRL_PIN(48, "I2C5_SCL"),
138 	PINCTRL_PIN(49, "I2C_NFC_SDA"),
139 	PINCTRL_PIN(50, "I2C4_SCL"),
140 	PINCTRL_PIN(51, "I2C6_SCL"),
141 	PINCTRL_PIN(52, "I2C_NFC_SCL"),
142 
143 	PINCTRL_PIN(60, "I2C1_SDA"),
144 	PINCTRL_PIN(61, "I2C0_SDA"),
145 	PINCTRL_PIN(62, "I2C2_SDA"),
146 	PINCTRL_PIN(63, "I2C1_SCL"),
147 	PINCTRL_PIN(64, "I2C3_SDA"),
148 	PINCTRL_PIN(65, "I2C0_SCL"),
149 	PINCTRL_PIN(66, "I2C2_SCL"),
150 	PINCTRL_PIN(67, "I2C3_SCL"),
151 
152 	PINCTRL_PIN(75, "SATA_GP0"),
153 	PINCTRL_PIN(76, "SATA_GP1"),
154 	PINCTRL_PIN(77, "SATA_LEDN"),
155 	PINCTRL_PIN(78, "SATA_GP2"),
156 	PINCTRL_PIN(79, "MF_SMB_ALERTB"),
157 	PINCTRL_PIN(80, "SATA_GP3"),
158 	PINCTRL_PIN(81, "MF_SMB_CLK"),
159 	PINCTRL_PIN(82, "MF_SMB_DATA"),
160 
161 	PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
162 	PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
163 	PINCTRL_PIN(92, "GP_SSP_2_CLK"),
164 	PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
165 	PINCTRL_PIN(94, "GP_SSP_2_RXD"),
166 	PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
167 	PINCTRL_PIN(96, "GP_SSP_2_FS"),
168 	PINCTRL_PIN(97, "GP_SSP_2_TXD"),
169 };
170 
171 static const unsigned southwest_uart0_pins[] = { 16, 20 };
172 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
173 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
174 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
175 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
176 static const unsigned southwest_lpe_pins[] = {
177 	30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
178 };
179 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
180 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
181 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
182 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
183 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
184 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
185 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
186 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
187 
188 /* Some of LPE I2S TXD pins need to have OE inversion set */
189 static const unsigned int southwest_lpe_altfuncs[] = {
190 	PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
191 	PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
192 	PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
193 };
194 
195 /*
196  * Two spi3 chipselects are available in different mode than the main spi3
197  * functionality, which is using mode 2.
198  */
199 static const unsigned int southwest_spi3_altfuncs[] = {
200 	PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
201 	PINMODE(2, 0),						    /* 82 */
202 };
203 
204 static const struct intel_pingroup southwest_groups[] = {
205 	PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
206 	PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
207 	PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
208 	PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
209 	PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
210 	PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
211 	PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
212 	PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
213 	PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
214 	PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
215 	PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
216 	PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
217 	PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
218 	PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
219 };
220 
221 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
222 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
223 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
224 static const char * const southwest_hda_groups[] = { "hda_grp" };
225 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
226 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
227 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
228 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
229 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
230 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
231 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
232 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
233 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
234 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
235 
236 /*
237  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
238  * enabled only as GPIOs.
239  */
240 static const struct intel_function southwest_functions[] = {
241 	FUNCTION("uart0", southwest_uart0_groups),
242 	FUNCTION("uart1", southwest_uart1_groups),
243 	FUNCTION("uart2", southwest_uart2_groups),
244 	FUNCTION("hda", southwest_hda_groups),
245 	FUNCTION("lpe", southwest_lpe_groups),
246 	FUNCTION("i2c0", southwest_i2c0_groups),
247 	FUNCTION("i2c1", southwest_i2c1_groups),
248 	FUNCTION("i2c2", southwest_i2c2_groups),
249 	FUNCTION("i2c3", southwest_i2c3_groups),
250 	FUNCTION("i2c4", southwest_i2c4_groups),
251 	FUNCTION("i2c5", southwest_i2c5_groups),
252 	FUNCTION("i2c6", southwest_i2c6_groups),
253 	FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
254 	FUNCTION("spi3", southwest_spi3_groups),
255 };
256 
257 static const struct intel_padgroup southwest_gpps[] = {
258 	CHV_GPP(0, 7),
259 	CHV_GPP(15, 22),
260 	CHV_GPP(30, 37),
261 	CHV_GPP(45, 52),
262 	CHV_GPP(60, 67),
263 	CHV_GPP(75, 82),
264 	CHV_GPP(90, 97),
265 };
266 
267 /*
268  * Southwest community can generate GPIO interrupts only for the first 8
269  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
270  */
271 static const struct intel_community southwest_communities[] = {
272 	CHV_COMMUNITY(southwest_gpps, 8, 0x91),
273 };
274 
275 static const struct intel_pinctrl_soc_data southwest_soc_data = {
276 	.uid = "1",
277 	.pins = southwest_pins,
278 	.npins = ARRAY_SIZE(southwest_pins),
279 	.groups = southwest_groups,
280 	.ngroups = ARRAY_SIZE(southwest_groups),
281 	.functions = southwest_functions,
282 	.nfunctions = ARRAY_SIZE(southwest_functions),
283 	.communities = southwest_communities,
284 	.ncommunities = ARRAY_SIZE(southwest_communities),
285 };
286 
287 static const struct pinctrl_pin_desc north_pins[] = {
288 	PINCTRL_PIN(0, "GPIO_DFX_0"),
289 	PINCTRL_PIN(1, "GPIO_DFX_3"),
290 	PINCTRL_PIN(2, "GPIO_DFX_7"),
291 	PINCTRL_PIN(3, "GPIO_DFX_1"),
292 	PINCTRL_PIN(4, "GPIO_DFX_5"),
293 	PINCTRL_PIN(5, "GPIO_DFX_4"),
294 	PINCTRL_PIN(6, "GPIO_DFX_8"),
295 	PINCTRL_PIN(7, "GPIO_DFX_2"),
296 	PINCTRL_PIN(8, "GPIO_DFX_6"),
297 
298 	PINCTRL_PIN(15, "GPIO_SUS0"),
299 	PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
300 	PINCTRL_PIN(17, "GPIO_SUS3"),
301 	PINCTRL_PIN(18, "GPIO_SUS7"),
302 	PINCTRL_PIN(19, "GPIO_SUS1"),
303 	PINCTRL_PIN(20, "GPIO_SUS5"),
304 	PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
305 	PINCTRL_PIN(22, "GPIO_SUS4"),
306 	PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
307 	PINCTRL_PIN(24, "GPIO_SUS2"),
308 	PINCTRL_PIN(25, "GPIO_SUS6"),
309 	PINCTRL_PIN(26, "CX_PREQ_B"),
310 	PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
311 
312 	PINCTRL_PIN(30, "TRST_B"),
313 	PINCTRL_PIN(31, "TCK"),
314 	PINCTRL_PIN(32, "PROCHOT_B"),
315 	PINCTRL_PIN(33, "SVIDO_DATA"),
316 	PINCTRL_PIN(34, "TMS"),
317 	PINCTRL_PIN(35, "CX_PRDY_B_2"),
318 	PINCTRL_PIN(36, "TDO_2"),
319 	PINCTRL_PIN(37, "CX_PRDY_B"),
320 	PINCTRL_PIN(38, "SVIDO_ALERT_B"),
321 	PINCTRL_PIN(39, "TDO"),
322 	PINCTRL_PIN(40, "SVIDO_CLK"),
323 	PINCTRL_PIN(41, "TDI"),
324 
325 	PINCTRL_PIN(45, "GP_CAMERASB_05"),
326 	PINCTRL_PIN(46, "GP_CAMERASB_02"),
327 	PINCTRL_PIN(47, "GP_CAMERASB_08"),
328 	PINCTRL_PIN(48, "GP_CAMERASB_00"),
329 	PINCTRL_PIN(49, "GP_CAMERASB_06"),
330 	PINCTRL_PIN(50, "GP_CAMERASB_10"),
331 	PINCTRL_PIN(51, "GP_CAMERASB_03"),
332 	PINCTRL_PIN(52, "GP_CAMERASB_09"),
333 	PINCTRL_PIN(53, "GP_CAMERASB_01"),
334 	PINCTRL_PIN(54, "GP_CAMERASB_07"),
335 	PINCTRL_PIN(55, "GP_CAMERASB_11"),
336 	PINCTRL_PIN(56, "GP_CAMERASB_04"),
337 
338 	PINCTRL_PIN(60, "PANEL0_BKLTEN"),
339 	PINCTRL_PIN(61, "HV_DDI0_HPD"),
340 	PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
341 	PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
342 	PINCTRL_PIN(64, "HV_DDI1_HPD"),
343 	PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
344 	PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
345 	PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
346 	PINCTRL_PIN(68, "HV_DDI2_HPD"),
347 	PINCTRL_PIN(69, "PANEL1_VDDEN"),
348 	PINCTRL_PIN(70, "PANEL1_BKLTEN"),
349 	PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
350 	PINCTRL_PIN(72, "PANEL0_VDDEN"),
351 };
352 
353 static const struct intel_padgroup north_gpps[] = {
354 	CHV_GPP(0, 8),
355 	CHV_GPP(15, 27),
356 	CHV_GPP(30, 41),
357 	CHV_GPP(45, 56),
358 	CHV_GPP(60, 72),
359 };
360 
361 /*
362  * North community can generate GPIO interrupts only for the first 8
363  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
364  */
365 static const struct intel_community north_communities[] = {
366 	CHV_COMMUNITY(north_gpps, 8, 0x92),
367 };
368 
369 static const struct intel_pinctrl_soc_data north_soc_data = {
370 	.uid = "2",
371 	.pins = north_pins,
372 	.npins = ARRAY_SIZE(north_pins),
373 	.communities = north_communities,
374 	.ncommunities = ARRAY_SIZE(north_communities),
375 };
376 
377 static const struct pinctrl_pin_desc east_pins[] = {
378 	PINCTRL_PIN(0, "PMU_SLP_S3_B"),
379 	PINCTRL_PIN(1, "PMU_BATLOW_B"),
380 	PINCTRL_PIN(2, "SUS_STAT_B"),
381 	PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
382 	PINCTRL_PIN(4, "PMU_AC_PRESENT"),
383 	PINCTRL_PIN(5, "PMU_PLTRST_B"),
384 	PINCTRL_PIN(6, "PMU_SUSCLK"),
385 	PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
386 	PINCTRL_PIN(8, "PMU_PWRBTN_B"),
387 	PINCTRL_PIN(9, "PMU_SLP_S4_B"),
388 	PINCTRL_PIN(10, "PMU_WAKE_B"),
389 	PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
390 
391 	PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
392 	PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
393 	PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
394 	PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
395 	PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
396 	PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
397 	PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
398 	PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
399 	PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
400 	PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
401 	PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
402 	PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
403 };
404 
405 static const struct intel_padgroup east_gpps[] = {
406 	CHV_GPP(0, 11),
407 	CHV_GPP(15, 26),
408 };
409 
410 static const struct intel_community east_communities[] = {
411 	CHV_COMMUNITY(east_gpps, 16, 0x93),
412 };
413 
414 static const struct intel_pinctrl_soc_data east_soc_data = {
415 	.uid = "3",
416 	.pins = east_pins,
417 	.npins = ARRAY_SIZE(east_pins),
418 	.communities = east_communities,
419 	.ncommunities = ARRAY_SIZE(east_communities),
420 };
421 
422 static const struct pinctrl_pin_desc southeast_pins[] = {
423 	PINCTRL_PIN(0, "MF_PLT_CLK0"),
424 	PINCTRL_PIN(1, "PWM1"),
425 	PINCTRL_PIN(2, "MF_PLT_CLK1"),
426 	PINCTRL_PIN(3, "MF_PLT_CLK4"),
427 	PINCTRL_PIN(4, "MF_PLT_CLK3"),
428 	PINCTRL_PIN(5, "PWM0"),
429 	PINCTRL_PIN(6, "MF_PLT_CLK5"),
430 	PINCTRL_PIN(7, "MF_PLT_CLK2"),
431 
432 	PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
433 	PINCTRL_PIN(16, "SDMMC1_CLK"),
434 	PINCTRL_PIN(17, "SDMMC1_D0"),
435 	PINCTRL_PIN(18, "SDMMC2_D1"),
436 	PINCTRL_PIN(19, "SDMMC2_CLK"),
437 	PINCTRL_PIN(20, "SDMMC1_D2"),
438 	PINCTRL_PIN(21, "SDMMC2_D2"),
439 	PINCTRL_PIN(22, "SDMMC2_CMD"),
440 	PINCTRL_PIN(23, "SDMMC1_CMD"),
441 	PINCTRL_PIN(24, "SDMMC1_D1"),
442 	PINCTRL_PIN(25, "SDMMC2_D0"),
443 	PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
444 
445 	PINCTRL_PIN(30, "SDMMC3_D1"),
446 	PINCTRL_PIN(31, "SDMMC3_CLK"),
447 	PINCTRL_PIN(32, "SDMMC3_D3"),
448 	PINCTRL_PIN(33, "SDMMC3_D2"),
449 	PINCTRL_PIN(34, "SDMMC3_CMD"),
450 	PINCTRL_PIN(35, "SDMMC3_D0"),
451 
452 	PINCTRL_PIN(45, "MF_LPC_AD2"),
453 	PINCTRL_PIN(46, "LPC_CLKRUNB"),
454 	PINCTRL_PIN(47, "MF_LPC_AD0"),
455 	PINCTRL_PIN(48, "LPC_FRAMEB"),
456 	PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
457 	PINCTRL_PIN(50, "MF_LPC_AD3"),
458 	PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
459 	PINCTRL_PIN(52, "MF_LPC_AD1"),
460 
461 	PINCTRL_PIN(60, "SPI1_MISO"),
462 	PINCTRL_PIN(61, "SPI1_CSO_B"),
463 	PINCTRL_PIN(62, "SPI1_CLK"),
464 	PINCTRL_PIN(63, "MMC1_D6"),
465 	PINCTRL_PIN(64, "SPI1_MOSI"),
466 	PINCTRL_PIN(65, "MMC1_D5"),
467 	PINCTRL_PIN(66, "SPI1_CS1_B"),
468 	PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
469 	PINCTRL_PIN(68, "MMC1_D7"),
470 	PINCTRL_PIN(69, "MMC1_RCLK"),
471 
472 	PINCTRL_PIN(75, "USB_OC1_B"),
473 	PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
474 	PINCTRL_PIN(77, "GPIO_ALERT"),
475 	PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
476 	PINCTRL_PIN(79, "ILB_SERIRQ"),
477 	PINCTRL_PIN(80, "USB_OC0_B"),
478 	PINCTRL_PIN(81, "SDMMC3_CD_B"),
479 	PINCTRL_PIN(82, "SPKR"),
480 	PINCTRL_PIN(83, "SUSPWRDNACK"),
481 	PINCTRL_PIN(84, "SPARE_PIN"),
482 	PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
483 };
484 
485 static const unsigned southeast_pwm0_pins[] = { 5 };
486 static const unsigned southeast_pwm1_pins[] = { 1 };
487 static const unsigned southeast_sdmmc1_pins[] = {
488 	16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
489 };
490 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
491 static const unsigned southeast_sdmmc3_pins[] = {
492 	30, 31, 32, 33, 34, 35, 78, 81, 85,
493 };
494 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
495 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
496 
497 static const struct intel_pingroup southeast_groups[] = {
498 	PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
499 	PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
500 	PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
501 	PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
502 	PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
503 	PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
504 	PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
505 };
506 
507 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
508 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
509 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
510 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
511 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
512 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
513 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
514 
515 static const struct intel_function southeast_functions[] = {
516 	FUNCTION("pwm0", southeast_pwm0_groups),
517 	FUNCTION("pwm1", southeast_pwm1_groups),
518 	FUNCTION("sdmmc1", southeast_sdmmc1_groups),
519 	FUNCTION("sdmmc2", southeast_sdmmc2_groups),
520 	FUNCTION("sdmmc3", southeast_sdmmc3_groups),
521 	FUNCTION("spi1", southeast_spi1_groups),
522 	FUNCTION("spi2", southeast_spi2_groups),
523 };
524 
525 static const struct intel_padgroup southeast_gpps[] = {
526 	CHV_GPP(0, 7),
527 	CHV_GPP(15, 26),
528 	CHV_GPP(30, 35),
529 	CHV_GPP(45, 52),
530 	CHV_GPP(60, 69),
531 	CHV_GPP(75, 85),
532 };
533 
534 static const struct intel_community southeast_communities[] = {
535 	CHV_COMMUNITY(southeast_gpps, 16, 0x94),
536 };
537 
538 static const struct intel_pinctrl_soc_data southeast_soc_data = {
539 	.uid = "4",
540 	.pins = southeast_pins,
541 	.npins = ARRAY_SIZE(southeast_pins),
542 	.groups = southeast_groups,
543 	.ngroups = ARRAY_SIZE(southeast_groups),
544 	.functions = southeast_functions,
545 	.nfunctions = ARRAY_SIZE(southeast_functions),
546 	.communities = southeast_communities,
547 	.ncommunities = ARRAY_SIZE(southeast_communities),
548 };
549 
550 static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
551 	&southwest_soc_data,
552 	&north_soc_data,
553 	&east_soc_data,
554 	&southeast_soc_data,
555 	NULL
556 };
557 
558 /*
559  * Lock to serialize register accesses
560  *
561  * Due to a silicon issue, a shared lock must be used to prevent
562  * concurrent accesses across the 4 GPIO controllers.
563  *
564  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
565  * errata #CHT34, for further information.
566  */
567 static DEFINE_RAW_SPINLOCK(chv_lock);
568 
569 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
570 {
571 	const struct intel_community *community = &pctrl->communities[0];
572 
573 	return readl(community->regs + offset);
574 }
575 
576 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
577 {
578 	const struct intel_community *community = &pctrl->communities[0];
579 	void __iomem *reg = community->regs + offset;
580 
581 	/* Write and simple read back to confirm the bus transferring done */
582 	writel(value, reg);
583 	readl(reg);
584 }
585 
586 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
587 				unsigned int reg)
588 {
589 	const struct intel_community *community = &pctrl->communities[0];
590 	unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
591 	unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
592 
593 	offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
594 
595 	return community->pad_regs + offset + reg;
596 }
597 
598 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
599 {
600 	return readl(chv_padreg(pctrl, pin, offset));
601 }
602 
603 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
604 {
605 	void __iomem *reg = chv_padreg(pctrl, pin, offset);
606 
607 	/* Write and simple read back to confirm the bus transferring done */
608 	writel(value, reg);
609 	readl(reg);
610 }
611 
612 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
613 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
614 {
615 	return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
616 }
617 
618 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
619 {
620 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
621 
622 	return pctrl->soc->ngroups;
623 }
624 
625 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
626 				      unsigned int group)
627 {
628 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
629 
630 	return pctrl->soc->groups[group].name;
631 }
632 
633 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
634 			      const unsigned int **pins, unsigned int *npins)
635 {
636 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
637 
638 	*pins = pctrl->soc->groups[group].pins;
639 	*npins = pctrl->soc->groups[group].npins;
640 	return 0;
641 }
642 
643 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
644 			     unsigned int offset)
645 {
646 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
647 	unsigned long flags;
648 	u32 ctrl0, ctrl1;
649 	bool locked;
650 
651 	raw_spin_lock_irqsave(&chv_lock, flags);
652 
653 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
654 	ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
655 	locked = chv_pad_locked(pctrl, offset);
656 
657 	raw_spin_unlock_irqrestore(&chv_lock, flags);
658 
659 	if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
660 		seq_puts(s, "GPIO ");
661 	} else {
662 		u32 mode;
663 
664 		mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
665 		mode >>= CHV_PADCTRL0_PMODE_SHIFT;
666 
667 		seq_printf(s, "mode %d ", mode);
668 	}
669 
670 	seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
671 
672 	if (locked)
673 		seq_puts(s, " [LOCKED]");
674 }
675 
676 static const struct pinctrl_ops chv_pinctrl_ops = {
677 	.get_groups_count = chv_get_groups_count,
678 	.get_group_name = chv_get_group_name,
679 	.get_group_pins = chv_get_group_pins,
680 	.pin_dbg_show = chv_pin_dbg_show,
681 };
682 
683 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
684 {
685 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
686 
687 	return pctrl->soc->nfunctions;
688 }
689 
690 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
691 					 unsigned int function)
692 {
693 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
694 
695 	return pctrl->soc->functions[function].name;
696 }
697 
698 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
699 				   unsigned int function,
700 				   const char * const **groups,
701 				   unsigned int * const ngroups)
702 {
703 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
704 
705 	*groups = pctrl->soc->functions[function].groups;
706 	*ngroups = pctrl->soc->functions[function].ngroups;
707 	return 0;
708 }
709 
710 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
711 			      unsigned int function, unsigned int group)
712 {
713 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
714 	struct device *dev = pctrl->dev;
715 	const struct intel_pingroup *grp;
716 	unsigned long flags;
717 	int i;
718 
719 	grp = &pctrl->soc->groups[group];
720 
721 	raw_spin_lock_irqsave(&chv_lock, flags);
722 
723 	/* Check first that the pad is not locked */
724 	for (i = 0; i < grp->npins; i++) {
725 		if (chv_pad_locked(pctrl, grp->pins[i])) {
726 			raw_spin_unlock_irqrestore(&chv_lock, flags);
727 			dev_warn(dev, "unable to set mode for locked pin %u\n", grp->pins[i]);
728 			return -EBUSY;
729 		}
730 	}
731 
732 	for (i = 0; i < grp->npins; i++) {
733 		int pin = grp->pins[i];
734 		unsigned int mode;
735 		bool invert_oe;
736 		u32 value;
737 
738 		/* Check if there is pin-specific config */
739 		if (grp->modes)
740 			mode = grp->modes[i];
741 		else
742 			mode = grp->mode;
743 
744 		/* Extract OE inversion */
745 		invert_oe = mode & PINMODE_INVERT_OE;
746 		mode &= ~PINMODE_INVERT_OE;
747 
748 		value = chv_readl(pctrl, pin, CHV_PADCTRL0);
749 		/* Disable GPIO mode */
750 		value &= ~CHV_PADCTRL0_GPIOEN;
751 		/* Set to desired mode */
752 		value &= ~CHV_PADCTRL0_PMODE_MASK;
753 		value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
754 		chv_writel(pctrl, pin, CHV_PADCTRL0, value);
755 
756 		/* Update for invert_oe */
757 		value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
758 		if (invert_oe)
759 			value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
760 		chv_writel(pctrl, pin, CHV_PADCTRL1, value);
761 
762 		dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode,
763 			invert_oe ? "" : "not ");
764 	}
765 
766 	raw_spin_unlock_irqrestore(&chv_lock, flags);
767 
768 	return 0;
769 }
770 
771 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
772 				      unsigned int offset)
773 {
774 	u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
775 	u32 value;
776 
777 	/*
778 	 * One some devices the GPIO should output the inverted value from what
779 	 * device-drivers / ACPI code expects (inverted external buffer?). The
780 	 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
781 	 * preserve this flag if the pin is already setup as GPIO.
782 	 */
783 	value = chv_readl(pctrl, offset, CHV_PADCTRL0);
784 	if (value & CHV_PADCTRL0_GPIOEN)
785 		invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
786 
787 	value = chv_readl(pctrl, offset, CHV_PADCTRL1);
788 	value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
789 	value &= ~invrxtx_mask;
790 	chv_writel(pctrl, offset, CHV_PADCTRL1, value);
791 }
792 
793 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
794 				   struct pinctrl_gpio_range *range,
795 				   unsigned int offset)
796 {
797 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
798 	unsigned long flags;
799 	u32 value;
800 
801 	raw_spin_lock_irqsave(&chv_lock, flags);
802 
803 	if (chv_pad_locked(pctrl, offset)) {
804 		value = chv_readl(pctrl, offset, CHV_PADCTRL0);
805 		if (!(value & CHV_PADCTRL0_GPIOEN)) {
806 			/* Locked so cannot enable */
807 			raw_spin_unlock_irqrestore(&chv_lock, flags);
808 			return -EBUSY;
809 		}
810 	} else {
811 		struct intel_community_context *cctx = &pctrl->context.communities[0];
812 		int i;
813 
814 		/* Reset the interrupt mapping */
815 		for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
816 			if (cctx->intr_lines[i] == offset) {
817 				cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
818 				break;
819 			}
820 		}
821 
822 		/* Disable interrupt generation */
823 		chv_gpio_clear_triggering(pctrl, offset);
824 
825 		value = chv_readl(pctrl, offset, CHV_PADCTRL0);
826 
827 		/*
828 		 * If the pin is in HiZ mode (both TX and RX buffers are
829 		 * disabled) we turn it to be input now.
830 		 */
831 		if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
832 		     (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
833 			value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
834 			value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
835 		}
836 
837 		/* Switch to a GPIO mode */
838 		value |= CHV_PADCTRL0_GPIOEN;
839 		chv_writel(pctrl, offset, CHV_PADCTRL0, value);
840 	}
841 
842 	raw_spin_unlock_irqrestore(&chv_lock, flags);
843 
844 	return 0;
845 }
846 
847 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
848 				  struct pinctrl_gpio_range *range,
849 				  unsigned int offset)
850 {
851 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
852 	unsigned long flags;
853 
854 	raw_spin_lock_irqsave(&chv_lock, flags);
855 
856 	if (!chv_pad_locked(pctrl, offset))
857 		chv_gpio_clear_triggering(pctrl, offset);
858 
859 	raw_spin_unlock_irqrestore(&chv_lock, flags);
860 }
861 
862 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
863 				  struct pinctrl_gpio_range *range,
864 				  unsigned int offset, bool input)
865 {
866 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
867 	unsigned long flags;
868 	u32 ctrl0;
869 
870 	raw_spin_lock_irqsave(&chv_lock, flags);
871 
872 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
873 	if (input)
874 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
875 	else
876 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
877 	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
878 
879 	raw_spin_unlock_irqrestore(&chv_lock, flags);
880 
881 	return 0;
882 }
883 
884 static const struct pinmux_ops chv_pinmux_ops = {
885 	.get_functions_count = chv_get_functions_count,
886 	.get_function_name = chv_get_function_name,
887 	.get_function_groups = chv_get_function_groups,
888 	.set_mux = chv_pinmux_set_mux,
889 	.gpio_request_enable = chv_gpio_request_enable,
890 	.gpio_disable_free = chv_gpio_disable_free,
891 	.gpio_set_direction = chv_gpio_set_direction,
892 };
893 
894 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
895 			  unsigned long *config)
896 {
897 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
898 	enum pin_config_param param = pinconf_to_config_param(*config);
899 	unsigned long flags;
900 	u32 ctrl0, ctrl1;
901 	u16 arg = 0;
902 	u32 term;
903 
904 	raw_spin_lock_irqsave(&chv_lock, flags);
905 	ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
906 	ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
907 	raw_spin_unlock_irqrestore(&chv_lock, flags);
908 
909 	term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
910 
911 	switch (param) {
912 	case PIN_CONFIG_BIAS_DISABLE:
913 		if (term)
914 			return -EINVAL;
915 		break;
916 
917 	case PIN_CONFIG_BIAS_PULL_UP:
918 		if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
919 			return -EINVAL;
920 
921 		switch (term) {
922 		case CHV_PADCTRL0_TERM_20K:
923 			arg = 20000;
924 			break;
925 		case CHV_PADCTRL0_TERM_5K:
926 			arg = 5000;
927 			break;
928 		case CHV_PADCTRL0_TERM_1K:
929 			arg = 1000;
930 			break;
931 		}
932 
933 		break;
934 
935 	case PIN_CONFIG_BIAS_PULL_DOWN:
936 		if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
937 			return -EINVAL;
938 
939 		switch (term) {
940 		case CHV_PADCTRL0_TERM_20K:
941 			arg = 20000;
942 			break;
943 		case CHV_PADCTRL0_TERM_5K:
944 			arg = 5000;
945 			break;
946 		}
947 
948 		break;
949 
950 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
951 		if (!(ctrl1 & CHV_PADCTRL1_ODEN))
952 			return -EINVAL;
953 		break;
954 
955 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
956 		u32 cfg;
957 
958 		cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
959 		cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
960 		if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
961 			return -EINVAL;
962 
963 		break;
964 	}
965 
966 	default:
967 		return -ENOTSUPP;
968 	}
969 
970 	*config = pinconf_to_config_packed(param, arg);
971 	return 0;
972 }
973 
974 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
975 			       enum pin_config_param param, u32 arg)
976 {
977 	unsigned long flags;
978 	u32 ctrl0, pull;
979 
980 	raw_spin_lock_irqsave(&chv_lock, flags);
981 	ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
982 
983 	switch (param) {
984 	case PIN_CONFIG_BIAS_DISABLE:
985 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
986 		break;
987 
988 	case PIN_CONFIG_BIAS_PULL_UP:
989 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
990 
991 		switch (arg) {
992 		case 1000:
993 			/* For 1k there is only pull up */
994 			pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
995 			break;
996 		case 5000:
997 			pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
998 			break;
999 		case 20000:
1000 			pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1001 			break;
1002 		default:
1003 			raw_spin_unlock_irqrestore(&chv_lock, flags);
1004 			return -EINVAL;
1005 		}
1006 
1007 		ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1008 		break;
1009 
1010 	case PIN_CONFIG_BIAS_PULL_DOWN:
1011 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1012 
1013 		switch (arg) {
1014 		case 5000:
1015 			pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1016 			break;
1017 		case 20000:
1018 			pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1019 			break;
1020 		default:
1021 			raw_spin_unlock_irqrestore(&chv_lock, flags);
1022 			return -EINVAL;
1023 		}
1024 
1025 		ctrl0 |= pull;
1026 		break;
1027 
1028 	default:
1029 		raw_spin_unlock_irqrestore(&chv_lock, flags);
1030 		return -EINVAL;
1031 	}
1032 
1033 	chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
1034 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1035 
1036 	return 0;
1037 }
1038 
1039 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
1040 			       bool enable)
1041 {
1042 	unsigned long flags;
1043 	u32 ctrl1;
1044 
1045 	raw_spin_lock_irqsave(&chv_lock, flags);
1046 	ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
1047 
1048 	if (enable)
1049 		ctrl1 |= CHV_PADCTRL1_ODEN;
1050 	else
1051 		ctrl1 &= ~CHV_PADCTRL1_ODEN;
1052 
1053 	chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
1054 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1055 
1056 	return 0;
1057 }
1058 
1059 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1060 			  unsigned long *configs, unsigned int nconfigs)
1061 {
1062 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1063 	struct device *dev = pctrl->dev;
1064 	enum pin_config_param param;
1065 	int i, ret;
1066 	u32 arg;
1067 
1068 	if (chv_pad_locked(pctrl, pin))
1069 		return -EBUSY;
1070 
1071 	for (i = 0; i < nconfigs; i++) {
1072 		param = pinconf_to_config_param(configs[i]);
1073 		arg = pinconf_to_config_argument(configs[i]);
1074 
1075 		switch (param) {
1076 		case PIN_CONFIG_BIAS_DISABLE:
1077 		case PIN_CONFIG_BIAS_PULL_UP:
1078 		case PIN_CONFIG_BIAS_PULL_DOWN:
1079 			ret = chv_config_set_pull(pctrl, pin, param, arg);
1080 			if (ret)
1081 				return ret;
1082 			break;
1083 
1084 		case PIN_CONFIG_DRIVE_PUSH_PULL:
1085 			ret = chv_config_set_oden(pctrl, pin, false);
1086 			if (ret)
1087 				return ret;
1088 			break;
1089 
1090 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1091 			ret = chv_config_set_oden(pctrl, pin, true);
1092 			if (ret)
1093 				return ret;
1094 			break;
1095 
1096 		default:
1097 			return -ENOTSUPP;
1098 		}
1099 
1100 		dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg);
1101 	}
1102 
1103 	return 0;
1104 }
1105 
1106 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1107 				unsigned int group,
1108 				unsigned long *config)
1109 {
1110 	const unsigned int *pins;
1111 	unsigned int npins;
1112 	int ret;
1113 
1114 	ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1115 	if (ret)
1116 		return ret;
1117 
1118 	ret = chv_config_get(pctldev, pins[0], config);
1119 	if (ret)
1120 		return ret;
1121 
1122 	return 0;
1123 }
1124 
1125 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1126 				unsigned int group, unsigned long *configs,
1127 				unsigned int num_configs)
1128 {
1129 	const unsigned int *pins;
1130 	unsigned int npins;
1131 	int i, ret;
1132 
1133 	ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1134 	if (ret)
1135 		return ret;
1136 
1137 	for (i = 0; i < npins; i++) {
1138 		ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1139 		if (ret)
1140 			return ret;
1141 	}
1142 
1143 	return 0;
1144 }
1145 
1146 static const struct pinconf_ops chv_pinconf_ops = {
1147 	.is_generic = true,
1148 	.pin_config_set = chv_config_set,
1149 	.pin_config_get = chv_config_get,
1150 	.pin_config_group_get = chv_config_group_get,
1151 	.pin_config_group_set = chv_config_group_set,
1152 };
1153 
1154 static struct pinctrl_desc chv_pinctrl_desc = {
1155 	.pctlops = &chv_pinctrl_ops,
1156 	.pmxops = &chv_pinmux_ops,
1157 	.confops = &chv_pinconf_ops,
1158 	.owner = THIS_MODULE,
1159 };
1160 
1161 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1162 {
1163 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1164 	unsigned long flags;
1165 	u32 ctrl0, cfg;
1166 
1167 	raw_spin_lock_irqsave(&chv_lock, flags);
1168 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1169 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1170 
1171 	cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1172 	cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1173 
1174 	if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1175 		return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1176 	return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1177 }
1178 
1179 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1180 {
1181 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1182 	unsigned long flags;
1183 	u32 ctrl0;
1184 
1185 	raw_spin_lock_irqsave(&chv_lock, flags);
1186 
1187 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1188 
1189 	if (value)
1190 		ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1191 	else
1192 		ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1193 
1194 	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
1195 
1196 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1197 }
1198 
1199 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1200 {
1201 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1202 	u32 ctrl0, direction;
1203 	unsigned long flags;
1204 
1205 	raw_spin_lock_irqsave(&chv_lock, flags);
1206 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1207 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1208 
1209 	direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1210 	direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1211 
1212 	if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1213 		return GPIO_LINE_DIRECTION_OUT;
1214 
1215 	return GPIO_LINE_DIRECTION_IN;
1216 }
1217 
1218 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1219 {
1220 	return pinctrl_gpio_direction_input(chip->base + offset);
1221 }
1222 
1223 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1224 				     int value)
1225 {
1226 	chv_gpio_set(chip, offset, value);
1227 	return pinctrl_gpio_direction_output(chip->base + offset);
1228 }
1229 
1230 static const struct gpio_chip chv_gpio_chip = {
1231 	.owner = THIS_MODULE,
1232 	.request = gpiochip_generic_request,
1233 	.free = gpiochip_generic_free,
1234 	.get_direction = chv_gpio_get_direction,
1235 	.direction_input = chv_gpio_direction_input,
1236 	.direction_output = chv_gpio_direction_output,
1237 	.get = chv_gpio_get,
1238 	.set = chv_gpio_set,
1239 };
1240 
1241 static void chv_gpio_irq_ack(struct irq_data *d)
1242 {
1243 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1244 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1245 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1246 	u32 intr_line;
1247 
1248 	raw_spin_lock(&chv_lock);
1249 
1250 	intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1251 	intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1252 	intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1253 	chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
1254 
1255 	raw_spin_unlock(&chv_lock);
1256 }
1257 
1258 static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1259 {
1260 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1261 	u32 value, intr_line;
1262 	unsigned long flags;
1263 
1264 	raw_spin_lock_irqsave(&chv_lock, flags);
1265 
1266 	intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1267 	intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1268 	intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1269 
1270 	value = chv_pctrl_readl(pctrl, CHV_INTMASK);
1271 	if (mask)
1272 		value &= ~BIT(intr_line);
1273 	else
1274 		value |= BIT(intr_line);
1275 	chv_pctrl_writel(pctrl, CHV_INTMASK, value);
1276 
1277 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1278 }
1279 
1280 static void chv_gpio_irq_mask(struct irq_data *d)
1281 {
1282 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1283 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1284 
1285 	chv_gpio_irq_mask_unmask(gc, hwirq, true);
1286 	gpiochip_disable_irq(gc, hwirq);
1287 }
1288 
1289 static void chv_gpio_irq_unmask(struct irq_data *d)
1290 {
1291 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1292 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1293 
1294 	gpiochip_enable_irq(gc, hwirq);
1295 	chv_gpio_irq_mask_unmask(gc, hwirq, false);
1296 }
1297 
1298 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1299 {
1300 	/*
1301 	 * Check if the interrupt has been requested with 0 as triggering
1302 	 * type. In that case it is assumed that the current values
1303 	 * programmed to the hardware are used (e.g BIOS configured
1304 	 * defaults).
1305 	 *
1306 	 * In that case ->irq_set_type() will never be called so we need to
1307 	 * read back the values from hardware now, set correct flow handler
1308 	 * and update mappings before the interrupt is being used.
1309 	 */
1310 	if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1311 		struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1312 		struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1313 		struct device *dev = pctrl->dev;
1314 		struct intel_community_context *cctx = &pctrl->context.communities[0];
1315 		irq_hw_number_t hwirq = irqd_to_hwirq(d);
1316 		irq_flow_handler_t handler;
1317 		unsigned long flags;
1318 		u32 intsel, value;
1319 
1320 		raw_spin_lock_irqsave(&chv_lock, flags);
1321 		intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1322 		intsel &= CHV_PADCTRL0_INTSEL_MASK;
1323 		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1324 
1325 		value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
1326 		if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1327 			handler = handle_level_irq;
1328 		else
1329 			handler = handle_edge_irq;
1330 
1331 		if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
1332 			irq_set_handler_locked(d, handler);
1333 			dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n",
1334 				intsel, hwirq);
1335 			cctx->intr_lines[intsel] = hwirq;
1336 		}
1337 		raw_spin_unlock_irqrestore(&chv_lock, flags);
1338 	}
1339 
1340 	chv_gpio_irq_unmask(d);
1341 	return 0;
1342 }
1343 
1344 static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin)
1345 {
1346 	struct device *dev = pctrl->dev;
1347 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1348 	const struct intel_community *community = &pctrl->communities[0];
1349 	u32 value, intsel;
1350 	int i;
1351 
1352 	value = chv_readl(pctrl, pin, CHV_PADCTRL0);
1353 	intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT;
1354 
1355 	if (cctx->intr_lines[intsel] == pin)
1356 		return 0;
1357 
1358 	if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
1359 		dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin);
1360 		cctx->intr_lines[intsel] = pin;
1361 		return 0;
1362 	}
1363 
1364 	/*
1365 	 * The interrupt line selected by the BIOS is already in use by
1366 	 * another pin, this is a known BIOS bug found on several models.
1367 	 * But this may also be caused by Linux deciding to use a pin as
1368 	 * IRQ which was not expected to be used as such by the BIOS authors,
1369 	 * so log this at info level only.
1370 	 */
1371 	dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel,
1372 		 cctx->intr_lines[intsel], pin);
1373 
1374 	if (chv_pad_locked(pctrl, pin))
1375 		return -EBUSY;
1376 
1377 	/*
1378 	 * The BIOS fills the interrupt lines from 0 counting up, start at
1379 	 * the other end to find a free interrupt line to workaround this.
1380 	 */
1381 	for (i = community->nirqs - 1; i >= 0; i--) {
1382 		if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ)
1383 			break;
1384 	}
1385 	if (i < 0)
1386 		return -EBUSY;
1387 
1388 	dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i);
1389 
1390 	value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT);
1391 	chv_writel(pctrl, pin, CHV_PADCTRL0, value);
1392 	cctx->intr_lines[i] = pin;
1393 
1394 	return 0;
1395 }
1396 
1397 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1398 {
1399 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1400 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1401 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1402 	unsigned long flags;
1403 	u32 value;
1404 	int ret;
1405 
1406 	raw_spin_lock_irqsave(&chv_lock, flags);
1407 
1408 	ret = chv_gpio_set_intr_line(pctrl, hwirq);
1409 	if (ret)
1410 		goto out_unlock;
1411 
1412 	/*
1413 	 * Pins which can be used as shared interrupt are configured in
1414 	 * BIOS. Driver trusts BIOS configurations and assigns different
1415 	 * handler according to the irq type.
1416 	 *
1417 	 * Driver needs to save the mapping between each pin and
1418 	 * its interrupt line.
1419 	 * 1. If the pin cfg is locked in BIOS:
1420 	 *	Trust BIOS has programmed IntWakeCfg bits correctly,
1421 	 *	driver just needs to save the mapping.
1422 	 * 2. If the pin cfg is not locked in BIOS:
1423 	 *	Driver programs the IntWakeCfg bits and save the mapping.
1424 	 */
1425 	if (!chv_pad_locked(pctrl, hwirq)) {
1426 		value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
1427 		value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1428 		value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1429 
1430 		if (type & IRQ_TYPE_EDGE_BOTH) {
1431 			if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1432 				value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1433 			else if (type & IRQ_TYPE_EDGE_RISING)
1434 				value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1435 			else if (type & IRQ_TYPE_EDGE_FALLING)
1436 				value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1437 		} else if (type & IRQ_TYPE_LEVEL_MASK) {
1438 			value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1439 			if (type & IRQ_TYPE_LEVEL_LOW)
1440 				value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1441 		}
1442 
1443 		chv_writel(pctrl, hwirq, CHV_PADCTRL1, value);
1444 	}
1445 
1446 	if (type & IRQ_TYPE_EDGE_BOTH)
1447 		irq_set_handler_locked(d, handle_edge_irq);
1448 	else if (type & IRQ_TYPE_LEVEL_MASK)
1449 		irq_set_handler_locked(d, handle_level_irq);
1450 
1451 out_unlock:
1452 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1453 
1454 	return ret;
1455 }
1456 
1457 static const struct irq_chip chv_gpio_irq_chip = {
1458 	.name		= "chv-gpio",
1459 	.irq_startup	= chv_gpio_irq_startup,
1460 	.irq_ack	= chv_gpio_irq_ack,
1461 	.irq_mask	= chv_gpio_irq_mask,
1462 	.irq_unmask	= chv_gpio_irq_unmask,
1463 	.irq_set_type	= chv_gpio_irq_type,
1464 	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
1465 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
1466 };
1467 
1468 static void chv_gpio_irq_handler(struct irq_desc *desc)
1469 {
1470 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1471 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1472 	struct device *dev = pctrl->dev;
1473 	const struct intel_community *community = &pctrl->communities[0];
1474 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1475 	struct irq_chip *chip = irq_desc_get_chip(desc);
1476 	unsigned long pending;
1477 	unsigned long flags;
1478 	u32 intr_line;
1479 
1480 	chained_irq_enter(chip, desc);
1481 
1482 	raw_spin_lock_irqsave(&chv_lock, flags);
1483 	pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
1484 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1485 
1486 	for_each_set_bit(intr_line, &pending, community->nirqs) {
1487 		unsigned int offset;
1488 
1489 		offset = cctx->intr_lines[intr_line];
1490 		if (offset == CHV_INVALID_HWIRQ) {
1491 			dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line);
1492 			/* Some boards expect hwirq 0 to trigger in this case */
1493 			offset = 0;
1494 		}
1495 
1496 		generic_handle_domain_irq(gc->irq.domain, offset);
1497 	}
1498 
1499 	chained_irq_exit(chip, desc);
1500 }
1501 
1502 /*
1503  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1504  * tables. Since we leave GPIOs that are not capable of generating
1505  * interrupts out of the irqdomain the numbering will be different and
1506  * cause devices using the hardcoded IRQ numbers fail. In order not to
1507  * break such machines we will only mask pins from irqdomain if the machine
1508  * is not listed below.
1509  */
1510 static const struct dmi_system_id chv_no_valid_mask[] = {
1511 	/* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1512 	{
1513 		.ident = "Intel_Strago based Chromebooks (All models)",
1514 		.matches = {
1515 			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1516 			DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1517 		},
1518 	},
1519 	{
1520 		.ident = "HP Chromebook 11 G5 (Setzer)",
1521 		.matches = {
1522 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1523 			DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1524 		},
1525 	},
1526 	{
1527 		.ident = "Acer Chromebook R11 (Cyan)",
1528 		.matches = {
1529 			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1530 			DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1531 		},
1532 	},
1533 	{
1534 		.ident = "Samsung Chromebook 3 (Celes)",
1535 		.matches = {
1536 			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1537 			DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1538 		},
1539 	},
1540 	{}
1541 };
1542 
1543 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1544 				    unsigned long *valid_mask,
1545 				    unsigned int ngpios)
1546 {
1547 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1548 	const struct intel_community *community = &pctrl->communities[0];
1549 	int i;
1550 
1551 	/* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1552 	for (i = 0; i < pctrl->soc->npins; i++) {
1553 		const struct pinctrl_pin_desc *desc;
1554 		u32 intsel;
1555 
1556 		desc = &pctrl->soc->pins[i];
1557 
1558 		intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1559 		intsel &= CHV_PADCTRL0_INTSEL_MASK;
1560 		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1561 
1562 		if (intsel >= community->nirqs)
1563 			clear_bit(desc->number, valid_mask);
1564 	}
1565 }
1566 
1567 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1568 {
1569 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1570 	const struct intel_community *community = &pctrl->communities[0];
1571 
1572 	/*
1573 	 * The same set of machines in chv_no_valid_mask[] have incorrectly
1574 	 * configured GPIOs that generate spurious interrupts so we use
1575 	 * this same list to apply another quirk for them.
1576 	 *
1577 	 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1578 	 */
1579 	if (!pctrl->chip.irq.init_valid_mask) {
1580 		/*
1581 		 * Mask all interrupts the community is able to generate
1582 		 * but leave the ones that can only generate GPEs unmasked.
1583 		 */
1584 		chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
1585 	}
1586 
1587 	/* Clear all interrupts */
1588 	chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1589 
1590 	return 0;
1591 }
1592 
1593 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1594 {
1595 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1596 	struct device *dev = pctrl->dev;
1597 	const struct intel_community *community = &pctrl->communities[0];
1598 	const struct intel_padgroup *gpp;
1599 	int ret, i;
1600 
1601 	for (i = 0; i < community->ngpps; i++) {
1602 		gpp = &community->gpps[i];
1603 		ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);
1604 		if (ret) {
1605 			dev_err(dev, "failed to add GPIO pin range\n");
1606 			return ret;
1607 		}
1608 	}
1609 
1610 	return 0;
1611 }
1612 
1613 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1614 {
1615 	const struct intel_community *community = &pctrl->communities[0];
1616 	const struct intel_padgroup *gpp;
1617 	struct gpio_chip *chip = &pctrl->chip;
1618 	struct device *dev = pctrl->dev;
1619 	bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1620 	int ret, i, irq_base;
1621 
1622 	*chip = chv_gpio_chip;
1623 
1624 	chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
1625 	chip->label = dev_name(dev);
1626 	chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1627 	chip->parent = dev;
1628 	chip->base = -1;
1629 
1630 	pctrl->irq = irq;
1631 
1632 	gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip);
1633 	chip->irq.init_hw = chv_gpio_irq_init_hw;
1634 	chip->irq.parent_handler = chv_gpio_irq_handler;
1635 	chip->irq.num_parents = 1;
1636 	chip->irq.parents = &pctrl->irq;
1637 	chip->irq.default_type = IRQ_TYPE_NONE;
1638 	chip->irq.handler = handle_bad_irq;
1639 	if (need_valid_mask) {
1640 		chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1641 	} else {
1642 		irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);
1643 		if (irq_base < 0) {
1644 			dev_err(dev, "Failed to allocate IRQ numbers\n");
1645 			return irq_base;
1646 		}
1647 	}
1648 
1649 	ret = devm_gpiochip_add_data(dev, chip, pctrl);
1650 	if (ret) {
1651 		dev_err(dev, "Failed to register gpiochip\n");
1652 		return ret;
1653 	}
1654 
1655 	if (!need_valid_mask) {
1656 		for (i = 0; i < community->ngpps; i++) {
1657 			gpp = &community->gpps[i];
1658 
1659 			irq_domain_associate_many(chip->irq.domain, irq_base,
1660 						  gpp->base, gpp->size);
1661 			irq_base += gpp->size;
1662 		}
1663 	}
1664 
1665 	return 0;
1666 }
1667 
1668 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1669 	acpi_physical_address address, u32 bits, u64 *value,
1670 	void *handler_context, void *region_context)
1671 {
1672 	struct intel_pinctrl *pctrl = region_context;
1673 	unsigned long flags;
1674 	acpi_status ret = AE_OK;
1675 
1676 	raw_spin_lock_irqsave(&chv_lock, flags);
1677 
1678 	if (function == ACPI_WRITE)
1679 		chv_pctrl_writel(pctrl, address, *value);
1680 	else if (function == ACPI_READ)
1681 		*value = chv_pctrl_readl(pctrl, address);
1682 	else
1683 		ret = AE_BAD_PARAMETER;
1684 
1685 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1686 
1687 	return ret;
1688 }
1689 
1690 static int chv_pinctrl_probe(struct platform_device *pdev)
1691 {
1692 	const struct intel_pinctrl_soc_data *soc_data;
1693 	struct intel_community_context *cctx;
1694 	struct intel_community *community;
1695 	struct device *dev = &pdev->dev;
1696 	struct acpi_device *adev = ACPI_COMPANION(dev);
1697 	struct intel_pinctrl *pctrl;
1698 	acpi_status status;
1699 	unsigned int i;
1700 	int ret, irq;
1701 
1702 	soc_data = intel_pinctrl_get_soc_data(pdev);
1703 	if (IS_ERR(soc_data))
1704 		return PTR_ERR(soc_data);
1705 
1706 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1707 	if (!pctrl)
1708 		return -ENOMEM;
1709 
1710 	pctrl->dev = dev;
1711 	pctrl->soc = soc_data;
1712 
1713 	pctrl->ncommunities = pctrl->soc->ncommunities;
1714 	pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
1715 					  pctrl->ncommunities * sizeof(*pctrl->communities),
1716 					  GFP_KERNEL);
1717 	if (!pctrl->communities)
1718 		return -ENOMEM;
1719 
1720 	community = &pctrl->communities[0];
1721 	community->regs = devm_platform_ioremap_resource(pdev, 0);
1722 	if (IS_ERR(community->regs))
1723 		return PTR_ERR(community->regs);
1724 
1725 	community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
1726 
1727 #ifdef CONFIG_PM_SLEEP
1728 	pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
1729 					   sizeof(*pctrl->context.pads),
1730 					   GFP_KERNEL);
1731 	if (!pctrl->context.pads)
1732 		return -ENOMEM;
1733 #endif
1734 
1735 	pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
1736 						  sizeof(*pctrl->context.communities),
1737 						  GFP_KERNEL);
1738 	if (!pctrl->context.communities)
1739 		return -ENOMEM;
1740 
1741 	cctx = &pctrl->context.communities[0];
1742 	for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++)
1743 		cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
1744 
1745 	irq = platform_get_irq(pdev, 0);
1746 	if (irq < 0)
1747 		return irq;
1748 
1749 	pctrl->pctldesc = chv_pinctrl_desc;
1750 	pctrl->pctldesc.name = dev_name(dev);
1751 	pctrl->pctldesc.pins = pctrl->soc->pins;
1752 	pctrl->pctldesc.npins = pctrl->soc->npins;
1753 
1754 	pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1755 	if (IS_ERR(pctrl->pctldev)) {
1756 		dev_err(dev, "failed to register pinctrl driver\n");
1757 		return PTR_ERR(pctrl->pctldev);
1758 	}
1759 
1760 	ret = chv_gpio_probe(pctrl, irq);
1761 	if (ret)
1762 		return ret;
1763 
1764 	status = acpi_install_address_space_handler(adev->handle,
1765 					community->acpi_space_id,
1766 					chv_pinctrl_mmio_access_handler,
1767 					NULL, pctrl);
1768 	if (ACPI_FAILURE(status))
1769 		dev_err(dev, "failed to install ACPI addr space handler\n");
1770 
1771 	platform_set_drvdata(pdev, pctrl);
1772 
1773 	return 0;
1774 }
1775 
1776 static int chv_pinctrl_remove(struct platform_device *pdev)
1777 {
1778 	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1779 	const struct intel_community *community = &pctrl->communities[0];
1780 
1781 	acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1782 					  community->acpi_space_id,
1783 					  chv_pinctrl_mmio_access_handler);
1784 
1785 	return 0;
1786 }
1787 
1788 #ifdef CONFIG_PM_SLEEP
1789 static int chv_pinctrl_suspend_noirq(struct device *dev)
1790 {
1791 	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1792 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1793 	unsigned long flags;
1794 	int i;
1795 
1796 	raw_spin_lock_irqsave(&chv_lock, flags);
1797 
1798 	cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
1799 
1800 	for (i = 0; i < pctrl->soc->npins; i++) {
1801 		const struct pinctrl_pin_desc *desc;
1802 		struct intel_pad_context *ctx = &pctrl->context.pads[i];
1803 
1804 		desc = &pctrl->soc->pins[i];
1805 		if (chv_pad_locked(pctrl, desc->number))
1806 			continue;
1807 
1808 		ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1809 		ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
1810 
1811 		ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1812 	}
1813 
1814 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1815 
1816 	return 0;
1817 }
1818 
1819 static int chv_pinctrl_resume_noirq(struct device *dev)
1820 {
1821 	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1822 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1823 	unsigned long flags;
1824 	int i;
1825 
1826 	raw_spin_lock_irqsave(&chv_lock, flags);
1827 
1828 	/*
1829 	 * Mask all interrupts before restoring per-pin configuration
1830 	 * registers because we don't know in which state BIOS left them
1831 	 * upon exiting suspend.
1832 	 */
1833 	chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
1834 
1835 	for (i = 0; i < pctrl->soc->npins; i++) {
1836 		const struct pinctrl_pin_desc *desc;
1837 		struct intel_pad_context *ctx = &pctrl->context.pads[i];
1838 		u32 val;
1839 
1840 		desc = &pctrl->soc->pins[i];
1841 		if (chv_pad_locked(pctrl, desc->number))
1842 			continue;
1843 
1844 		/* Only restore if our saved state differs from the current */
1845 		val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1846 		val &= ~CHV_PADCTRL0_GPIORXSTATE;
1847 		if (ctx->padctrl0 != val) {
1848 			chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
1849 			dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number,
1850 				chv_readl(pctrl, desc->number, CHV_PADCTRL0));
1851 		}
1852 
1853 		val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1854 		if (ctx->padctrl1 != val) {
1855 			chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
1856 			dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number,
1857 				chv_readl(pctrl, desc->number, CHV_PADCTRL1));
1858 		}
1859 	}
1860 
1861 	/*
1862 	 * Now that all pins are restored to known state, we can restore
1863 	 * the interrupt mask register as well.
1864 	 */
1865 	chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1866 	chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
1867 
1868 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1869 
1870 	return 0;
1871 }
1872 #endif
1873 
1874 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1875 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1876 				      chv_pinctrl_resume_noirq)
1877 };
1878 
1879 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1880 	{ "INT33FF", (kernel_ulong_t)chv_soc_data },
1881 	{ }
1882 };
1883 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1884 
1885 static struct platform_driver chv_pinctrl_driver = {
1886 	.probe = chv_pinctrl_probe,
1887 	.remove = chv_pinctrl_remove,
1888 	.driver = {
1889 		.name = "cherryview-pinctrl",
1890 		.pm = &chv_pinctrl_pm_ops,
1891 		.acpi_match_table = chv_pinctrl_acpi_match,
1892 	},
1893 };
1894 
1895 static int __init chv_pinctrl_init(void)
1896 {
1897 	return platform_driver_register(&chv_pinctrl_driver);
1898 }
1899 subsys_initcall(chv_pinctrl_init);
1900 
1901 static void __exit chv_pinctrl_exit(void)
1902 {
1903 	platform_driver_unregister(&chv_pinctrl_driver);
1904 }
1905 module_exit(chv_pinctrl_exit);
1906 
1907 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1908 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1909 MODULE_LICENSE("GPL v2");
1910