1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Cherryview/Braswell pinctrl driver
4  *
5  * Copyright (C) 2014, 2020 Intel Corporation
6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7  *
8  * This driver is based on the original Cherryview GPIO driver by
9  *   Ning Li <ning.li@intel.com>
10  *   Alan Cox <alan@linux.intel.com>
11  */
12 
13 #include <linux/acpi.h>
14 #include <linux/dmi.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/seq_file.h>
20 #include <linux/types.h>
21 
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 
28 #include "pinctrl-intel.h"
29 
30 #define CHV_INTSTAT			0x300
31 #define CHV_INTMASK			0x380
32 
33 #define FAMILY_PAD_REGS_OFF		0x4400
34 #define FAMILY_PAD_REGS_SIZE		0x400
35 #define MAX_FAMILY_PAD_GPIO_NO		15
36 #define GPIO_REGS_SIZE			8
37 
38 #define CHV_PADCTRL0			0x000
39 #define CHV_PADCTRL0_INTSEL_SHIFT	28
40 #define CHV_PADCTRL0_INTSEL_MASK	GENMASK(31, 28)
41 #define CHV_PADCTRL0_TERM_UP		BIT(23)
42 #define CHV_PADCTRL0_TERM_SHIFT		20
43 #define CHV_PADCTRL0_TERM_MASK		GENMASK(22, 20)
44 #define CHV_PADCTRL0_TERM_20K		1
45 #define CHV_PADCTRL0_TERM_5K		2
46 #define CHV_PADCTRL0_TERM_1K		4
47 #define CHV_PADCTRL0_PMODE_SHIFT	16
48 #define CHV_PADCTRL0_PMODE_MASK		GENMASK(19, 16)
49 #define CHV_PADCTRL0_GPIOEN		BIT(15)
50 #define CHV_PADCTRL0_GPIOCFG_SHIFT	8
51 #define CHV_PADCTRL0_GPIOCFG_MASK	GENMASK(10, 8)
52 #define CHV_PADCTRL0_GPIOCFG_GPIO	0
53 #define CHV_PADCTRL0_GPIOCFG_GPO	1
54 #define CHV_PADCTRL0_GPIOCFG_GPI	2
55 #define CHV_PADCTRL0_GPIOCFG_HIZ	3
56 #define CHV_PADCTRL0_GPIOTXSTATE	BIT(1)
57 #define CHV_PADCTRL0_GPIORXSTATE	BIT(0)
58 
59 #define CHV_PADCTRL1			0x004
60 #define CHV_PADCTRL1_CFGLOCK		BIT(31)
61 #define CHV_PADCTRL1_INVRXTX_SHIFT	4
62 #define CHV_PADCTRL1_INVRXTX_MASK	GENMASK(7, 4)
63 #define CHV_PADCTRL1_INVRXTX_TXDATA	BIT(7)
64 #define CHV_PADCTRL1_INVRXTX_RXDATA	BIT(6)
65 #define CHV_PADCTRL1_INVRXTX_TXENABLE	BIT(5)
66 #define CHV_PADCTRL1_ODEN		BIT(3)
67 #define CHV_PADCTRL1_INTWAKECFG_MASK	GENMASK(2, 0)
68 #define CHV_PADCTRL1_INTWAKECFG_FALLING	1
69 #define CHV_PADCTRL1_INTWAKECFG_RISING	2
70 #define CHV_PADCTRL1_INTWAKECFG_BOTH	3
71 #define CHV_PADCTRL1_INTWAKECFG_LEVEL	4
72 
73 struct intel_pad_context {
74 	u32 padctrl0;
75 	u32 padctrl1;
76 };
77 
78 #define CHV_INVALID_HWIRQ	(~0U)
79 
80 /**
81  * struct intel_community_context - community context for Cherryview
82  * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
83  * @saved_intmask: Interrupt mask saved for system sleep
84  */
85 struct intel_community_context {
86 	unsigned int intr_lines[16];
87 	u32 saved_intmask;
88 };
89 
90 #define	PINMODE_INVERT_OE	BIT(15)
91 
92 #define PINMODE(m, i)		((m) | ((i) * PINMODE_INVERT_OE))
93 
94 #define CHV_GPP(start, end)			\
95 	{					\
96 		.base = (start),		\
97 		.size = (end) - (start) + 1,	\
98 	}
99 
100 #define CHV_COMMUNITY(g, i, a)			\
101 	{					\
102 		.gpps = (g),			\
103 		.ngpps = ARRAY_SIZE(g),		\
104 		.nirqs = (i),			\
105 		.acpi_space_id = (a),		\
106 	}
107 
108 static const struct pinctrl_pin_desc southwest_pins[] = {
109 	PINCTRL_PIN(0, "FST_SPI_D2"),
110 	PINCTRL_PIN(1, "FST_SPI_D0"),
111 	PINCTRL_PIN(2, "FST_SPI_CLK"),
112 	PINCTRL_PIN(3, "FST_SPI_D3"),
113 	PINCTRL_PIN(4, "FST_SPI_CS1_B"),
114 	PINCTRL_PIN(5, "FST_SPI_D1"),
115 	PINCTRL_PIN(6, "FST_SPI_CS0_B"),
116 	PINCTRL_PIN(7, "FST_SPI_CS2_B"),
117 
118 	PINCTRL_PIN(15, "UART1_RTS_B"),
119 	PINCTRL_PIN(16, "UART1_RXD"),
120 	PINCTRL_PIN(17, "UART2_RXD"),
121 	PINCTRL_PIN(18, "UART1_CTS_B"),
122 	PINCTRL_PIN(19, "UART2_RTS_B"),
123 	PINCTRL_PIN(20, "UART1_TXD"),
124 	PINCTRL_PIN(21, "UART2_TXD"),
125 	PINCTRL_PIN(22, "UART2_CTS_B"),
126 
127 	PINCTRL_PIN(30, "MF_HDA_CLK"),
128 	PINCTRL_PIN(31, "MF_HDA_RSTB"),
129 	PINCTRL_PIN(32, "MF_HDA_SDIO"),
130 	PINCTRL_PIN(33, "MF_HDA_SDO"),
131 	PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
132 	PINCTRL_PIN(35, "MF_HDA_SYNC"),
133 	PINCTRL_PIN(36, "MF_HDA_SDI1"),
134 	PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
135 
136 	PINCTRL_PIN(45, "I2C5_SDA"),
137 	PINCTRL_PIN(46, "I2C4_SDA"),
138 	PINCTRL_PIN(47, "I2C6_SDA"),
139 	PINCTRL_PIN(48, "I2C5_SCL"),
140 	PINCTRL_PIN(49, "I2C_NFC_SDA"),
141 	PINCTRL_PIN(50, "I2C4_SCL"),
142 	PINCTRL_PIN(51, "I2C6_SCL"),
143 	PINCTRL_PIN(52, "I2C_NFC_SCL"),
144 
145 	PINCTRL_PIN(60, "I2C1_SDA"),
146 	PINCTRL_PIN(61, "I2C0_SDA"),
147 	PINCTRL_PIN(62, "I2C2_SDA"),
148 	PINCTRL_PIN(63, "I2C1_SCL"),
149 	PINCTRL_PIN(64, "I2C3_SDA"),
150 	PINCTRL_PIN(65, "I2C0_SCL"),
151 	PINCTRL_PIN(66, "I2C2_SCL"),
152 	PINCTRL_PIN(67, "I2C3_SCL"),
153 
154 	PINCTRL_PIN(75, "SATA_GP0"),
155 	PINCTRL_PIN(76, "SATA_GP1"),
156 	PINCTRL_PIN(77, "SATA_LEDN"),
157 	PINCTRL_PIN(78, "SATA_GP2"),
158 	PINCTRL_PIN(79, "MF_SMB_ALERTB"),
159 	PINCTRL_PIN(80, "SATA_GP3"),
160 	PINCTRL_PIN(81, "MF_SMB_CLK"),
161 	PINCTRL_PIN(82, "MF_SMB_DATA"),
162 
163 	PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
164 	PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
165 	PINCTRL_PIN(92, "GP_SSP_2_CLK"),
166 	PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
167 	PINCTRL_PIN(94, "GP_SSP_2_RXD"),
168 	PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
169 	PINCTRL_PIN(96, "GP_SSP_2_FS"),
170 	PINCTRL_PIN(97, "GP_SSP_2_TXD"),
171 };
172 
173 static const unsigned southwest_uart0_pins[] = { 16, 20 };
174 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
175 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
176 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
177 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
178 static const unsigned southwest_lpe_pins[] = {
179 	30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
180 };
181 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
182 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
183 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
184 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
185 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
186 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
187 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
188 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
189 
190 /* Some of LPE I2S TXD pins need to have OE inversion set */
191 static const unsigned int southwest_lpe_altfuncs[] = {
192 	PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
193 	PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
194 	PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
195 };
196 
197 /*
198  * Two spi3 chipselects are available in different mode than the main spi3
199  * functionality, which is using mode 2.
200  */
201 static const unsigned int southwest_spi3_altfuncs[] = {
202 	PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
203 	PINMODE(2, 0),						    /* 82 */
204 };
205 
206 static const struct intel_pingroup southwest_groups[] = {
207 	PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
208 	PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
209 	PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
210 	PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
211 	PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
212 	PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
213 	PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
214 	PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
215 	PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
216 	PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
217 	PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
218 	PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
219 	PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
220 	PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
221 };
222 
223 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
224 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
225 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
226 static const char * const southwest_hda_groups[] = { "hda_grp" };
227 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
228 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
229 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
230 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
231 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
232 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
233 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
234 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
235 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
236 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
237 
238 /*
239  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
240  * enabled only as GPIOs.
241  */
242 static const struct intel_function southwest_functions[] = {
243 	FUNCTION("uart0", southwest_uart0_groups),
244 	FUNCTION("uart1", southwest_uart1_groups),
245 	FUNCTION("uart2", southwest_uart2_groups),
246 	FUNCTION("hda", southwest_hda_groups),
247 	FUNCTION("lpe", southwest_lpe_groups),
248 	FUNCTION("i2c0", southwest_i2c0_groups),
249 	FUNCTION("i2c1", southwest_i2c1_groups),
250 	FUNCTION("i2c2", southwest_i2c2_groups),
251 	FUNCTION("i2c3", southwest_i2c3_groups),
252 	FUNCTION("i2c4", southwest_i2c4_groups),
253 	FUNCTION("i2c5", southwest_i2c5_groups),
254 	FUNCTION("i2c6", southwest_i2c6_groups),
255 	FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
256 	FUNCTION("spi3", southwest_spi3_groups),
257 };
258 
259 static const struct intel_padgroup southwest_gpps[] = {
260 	CHV_GPP(0, 7),
261 	CHV_GPP(15, 22),
262 	CHV_GPP(30, 37),
263 	CHV_GPP(45, 52),
264 	CHV_GPP(60, 67),
265 	CHV_GPP(75, 82),
266 	CHV_GPP(90, 97),
267 };
268 
269 /*
270  * Southwest community can generate GPIO interrupts only for the first 8
271  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
272  */
273 static const struct intel_community southwest_communities[] = {
274 	CHV_COMMUNITY(southwest_gpps, 8, 0x91),
275 };
276 
277 static const struct intel_pinctrl_soc_data southwest_soc_data = {
278 	.uid = "1",
279 	.pins = southwest_pins,
280 	.npins = ARRAY_SIZE(southwest_pins),
281 	.groups = southwest_groups,
282 	.ngroups = ARRAY_SIZE(southwest_groups),
283 	.functions = southwest_functions,
284 	.nfunctions = ARRAY_SIZE(southwest_functions),
285 	.communities = southwest_communities,
286 	.ncommunities = ARRAY_SIZE(southwest_communities),
287 };
288 
289 static const struct pinctrl_pin_desc north_pins[] = {
290 	PINCTRL_PIN(0, "GPIO_DFX_0"),
291 	PINCTRL_PIN(1, "GPIO_DFX_3"),
292 	PINCTRL_PIN(2, "GPIO_DFX_7"),
293 	PINCTRL_PIN(3, "GPIO_DFX_1"),
294 	PINCTRL_PIN(4, "GPIO_DFX_5"),
295 	PINCTRL_PIN(5, "GPIO_DFX_4"),
296 	PINCTRL_PIN(6, "GPIO_DFX_8"),
297 	PINCTRL_PIN(7, "GPIO_DFX_2"),
298 	PINCTRL_PIN(8, "GPIO_DFX_6"),
299 
300 	PINCTRL_PIN(15, "GPIO_SUS0"),
301 	PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
302 	PINCTRL_PIN(17, "GPIO_SUS3"),
303 	PINCTRL_PIN(18, "GPIO_SUS7"),
304 	PINCTRL_PIN(19, "GPIO_SUS1"),
305 	PINCTRL_PIN(20, "GPIO_SUS5"),
306 	PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
307 	PINCTRL_PIN(22, "GPIO_SUS4"),
308 	PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
309 	PINCTRL_PIN(24, "GPIO_SUS2"),
310 	PINCTRL_PIN(25, "GPIO_SUS6"),
311 	PINCTRL_PIN(26, "CX_PREQ_B"),
312 	PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
313 
314 	PINCTRL_PIN(30, "TRST_B"),
315 	PINCTRL_PIN(31, "TCK"),
316 	PINCTRL_PIN(32, "PROCHOT_B"),
317 	PINCTRL_PIN(33, "SVIDO_DATA"),
318 	PINCTRL_PIN(34, "TMS"),
319 	PINCTRL_PIN(35, "CX_PRDY_B_2"),
320 	PINCTRL_PIN(36, "TDO_2"),
321 	PINCTRL_PIN(37, "CX_PRDY_B"),
322 	PINCTRL_PIN(38, "SVIDO_ALERT_B"),
323 	PINCTRL_PIN(39, "TDO"),
324 	PINCTRL_PIN(40, "SVIDO_CLK"),
325 	PINCTRL_PIN(41, "TDI"),
326 
327 	PINCTRL_PIN(45, "GP_CAMERASB_05"),
328 	PINCTRL_PIN(46, "GP_CAMERASB_02"),
329 	PINCTRL_PIN(47, "GP_CAMERASB_08"),
330 	PINCTRL_PIN(48, "GP_CAMERASB_00"),
331 	PINCTRL_PIN(49, "GP_CAMERASB_06"),
332 	PINCTRL_PIN(50, "GP_CAMERASB_10"),
333 	PINCTRL_PIN(51, "GP_CAMERASB_03"),
334 	PINCTRL_PIN(52, "GP_CAMERASB_09"),
335 	PINCTRL_PIN(53, "GP_CAMERASB_01"),
336 	PINCTRL_PIN(54, "GP_CAMERASB_07"),
337 	PINCTRL_PIN(55, "GP_CAMERASB_11"),
338 	PINCTRL_PIN(56, "GP_CAMERASB_04"),
339 
340 	PINCTRL_PIN(60, "PANEL0_BKLTEN"),
341 	PINCTRL_PIN(61, "HV_DDI0_HPD"),
342 	PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
343 	PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
344 	PINCTRL_PIN(64, "HV_DDI1_HPD"),
345 	PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
346 	PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
347 	PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
348 	PINCTRL_PIN(68, "HV_DDI2_HPD"),
349 	PINCTRL_PIN(69, "PANEL1_VDDEN"),
350 	PINCTRL_PIN(70, "PANEL1_BKLTEN"),
351 	PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
352 	PINCTRL_PIN(72, "PANEL0_VDDEN"),
353 };
354 
355 static const struct intel_padgroup north_gpps[] = {
356 	CHV_GPP(0, 8),
357 	CHV_GPP(15, 27),
358 	CHV_GPP(30, 41),
359 	CHV_GPP(45, 56),
360 	CHV_GPP(60, 72),
361 };
362 
363 /*
364  * North community can generate GPIO interrupts only for the first 8
365  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
366  */
367 static const struct intel_community north_communities[] = {
368 	CHV_COMMUNITY(north_gpps, 8, 0x92),
369 };
370 
371 static const struct intel_pinctrl_soc_data north_soc_data = {
372 	.uid = "2",
373 	.pins = north_pins,
374 	.npins = ARRAY_SIZE(north_pins),
375 	.communities = north_communities,
376 	.ncommunities = ARRAY_SIZE(north_communities),
377 };
378 
379 static const struct pinctrl_pin_desc east_pins[] = {
380 	PINCTRL_PIN(0, "PMU_SLP_S3_B"),
381 	PINCTRL_PIN(1, "PMU_BATLOW_B"),
382 	PINCTRL_PIN(2, "SUS_STAT_B"),
383 	PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
384 	PINCTRL_PIN(4, "PMU_AC_PRESENT"),
385 	PINCTRL_PIN(5, "PMU_PLTRST_B"),
386 	PINCTRL_PIN(6, "PMU_SUSCLK"),
387 	PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
388 	PINCTRL_PIN(8, "PMU_PWRBTN_B"),
389 	PINCTRL_PIN(9, "PMU_SLP_S4_B"),
390 	PINCTRL_PIN(10, "PMU_WAKE_B"),
391 	PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
392 
393 	PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
394 	PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
395 	PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
396 	PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
397 	PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
398 	PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
399 	PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
400 	PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
401 	PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
402 	PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
403 	PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
404 	PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
405 };
406 
407 static const struct intel_padgroup east_gpps[] = {
408 	CHV_GPP(0, 11),
409 	CHV_GPP(15, 26),
410 };
411 
412 static const struct intel_community east_communities[] = {
413 	CHV_COMMUNITY(east_gpps, 16, 0x93),
414 };
415 
416 static const struct intel_pinctrl_soc_data east_soc_data = {
417 	.uid = "3",
418 	.pins = east_pins,
419 	.npins = ARRAY_SIZE(east_pins),
420 	.communities = east_communities,
421 	.ncommunities = ARRAY_SIZE(east_communities),
422 };
423 
424 static const struct pinctrl_pin_desc southeast_pins[] = {
425 	PINCTRL_PIN(0, "MF_PLT_CLK0"),
426 	PINCTRL_PIN(1, "PWM1"),
427 	PINCTRL_PIN(2, "MF_PLT_CLK1"),
428 	PINCTRL_PIN(3, "MF_PLT_CLK4"),
429 	PINCTRL_PIN(4, "MF_PLT_CLK3"),
430 	PINCTRL_PIN(5, "PWM0"),
431 	PINCTRL_PIN(6, "MF_PLT_CLK5"),
432 	PINCTRL_PIN(7, "MF_PLT_CLK2"),
433 
434 	PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
435 	PINCTRL_PIN(16, "SDMMC1_CLK"),
436 	PINCTRL_PIN(17, "SDMMC1_D0"),
437 	PINCTRL_PIN(18, "SDMMC2_D1"),
438 	PINCTRL_PIN(19, "SDMMC2_CLK"),
439 	PINCTRL_PIN(20, "SDMMC1_D2"),
440 	PINCTRL_PIN(21, "SDMMC2_D2"),
441 	PINCTRL_PIN(22, "SDMMC2_CMD"),
442 	PINCTRL_PIN(23, "SDMMC1_CMD"),
443 	PINCTRL_PIN(24, "SDMMC1_D1"),
444 	PINCTRL_PIN(25, "SDMMC2_D0"),
445 	PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
446 
447 	PINCTRL_PIN(30, "SDMMC3_D1"),
448 	PINCTRL_PIN(31, "SDMMC3_CLK"),
449 	PINCTRL_PIN(32, "SDMMC3_D3"),
450 	PINCTRL_PIN(33, "SDMMC3_D2"),
451 	PINCTRL_PIN(34, "SDMMC3_CMD"),
452 	PINCTRL_PIN(35, "SDMMC3_D0"),
453 
454 	PINCTRL_PIN(45, "MF_LPC_AD2"),
455 	PINCTRL_PIN(46, "LPC_CLKRUNB"),
456 	PINCTRL_PIN(47, "MF_LPC_AD0"),
457 	PINCTRL_PIN(48, "LPC_FRAMEB"),
458 	PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
459 	PINCTRL_PIN(50, "MF_LPC_AD3"),
460 	PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
461 	PINCTRL_PIN(52, "MF_LPC_AD1"),
462 
463 	PINCTRL_PIN(60, "SPI1_MISO"),
464 	PINCTRL_PIN(61, "SPI1_CSO_B"),
465 	PINCTRL_PIN(62, "SPI1_CLK"),
466 	PINCTRL_PIN(63, "MMC1_D6"),
467 	PINCTRL_PIN(64, "SPI1_MOSI"),
468 	PINCTRL_PIN(65, "MMC1_D5"),
469 	PINCTRL_PIN(66, "SPI1_CS1_B"),
470 	PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
471 	PINCTRL_PIN(68, "MMC1_D7"),
472 	PINCTRL_PIN(69, "MMC1_RCLK"),
473 
474 	PINCTRL_PIN(75, "USB_OC1_B"),
475 	PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
476 	PINCTRL_PIN(77, "GPIO_ALERT"),
477 	PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
478 	PINCTRL_PIN(79, "ILB_SERIRQ"),
479 	PINCTRL_PIN(80, "USB_OC0_B"),
480 	PINCTRL_PIN(81, "SDMMC3_CD_B"),
481 	PINCTRL_PIN(82, "SPKR"),
482 	PINCTRL_PIN(83, "SUSPWRDNACK"),
483 	PINCTRL_PIN(84, "SPARE_PIN"),
484 	PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
485 };
486 
487 static const unsigned southeast_pwm0_pins[] = { 5 };
488 static const unsigned southeast_pwm1_pins[] = { 1 };
489 static const unsigned southeast_sdmmc1_pins[] = {
490 	16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
491 };
492 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
493 static const unsigned southeast_sdmmc3_pins[] = {
494 	30, 31, 32, 33, 34, 35, 78, 81, 85,
495 };
496 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
497 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
498 
499 static const struct intel_pingroup southeast_groups[] = {
500 	PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
501 	PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
502 	PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
503 	PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
504 	PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
505 	PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
506 	PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
507 };
508 
509 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
510 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
511 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
512 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
513 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
514 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
515 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
516 
517 static const struct intel_function southeast_functions[] = {
518 	FUNCTION("pwm0", southeast_pwm0_groups),
519 	FUNCTION("pwm1", southeast_pwm1_groups),
520 	FUNCTION("sdmmc1", southeast_sdmmc1_groups),
521 	FUNCTION("sdmmc2", southeast_sdmmc2_groups),
522 	FUNCTION("sdmmc3", southeast_sdmmc3_groups),
523 	FUNCTION("spi1", southeast_spi1_groups),
524 	FUNCTION("spi2", southeast_spi2_groups),
525 };
526 
527 static const struct intel_padgroup southeast_gpps[] = {
528 	CHV_GPP(0, 7),
529 	CHV_GPP(15, 26),
530 	CHV_GPP(30, 35),
531 	CHV_GPP(45, 52),
532 	CHV_GPP(60, 69),
533 	CHV_GPP(75, 85),
534 };
535 
536 static const struct intel_community southeast_communities[] = {
537 	CHV_COMMUNITY(southeast_gpps, 16, 0x94),
538 };
539 
540 static const struct intel_pinctrl_soc_data southeast_soc_data = {
541 	.uid = "4",
542 	.pins = southeast_pins,
543 	.npins = ARRAY_SIZE(southeast_pins),
544 	.groups = southeast_groups,
545 	.ngroups = ARRAY_SIZE(southeast_groups),
546 	.functions = southeast_functions,
547 	.nfunctions = ARRAY_SIZE(southeast_functions),
548 	.communities = southeast_communities,
549 	.ncommunities = ARRAY_SIZE(southeast_communities),
550 };
551 
552 static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
553 	&southwest_soc_data,
554 	&north_soc_data,
555 	&east_soc_data,
556 	&southeast_soc_data,
557 	NULL
558 };
559 
560 /*
561  * Lock to serialize register accesses
562  *
563  * Due to a silicon issue, a shared lock must be used to prevent
564  * concurrent accesses across the 4 GPIO controllers.
565  *
566  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
567  * errata #CHT34, for further information.
568  */
569 static DEFINE_RAW_SPINLOCK(chv_lock);
570 
571 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
572 {
573 	const struct intel_community *community = &pctrl->communities[0];
574 
575 	return readl(community->regs + offset);
576 }
577 
578 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
579 {
580 	const struct intel_community *community = &pctrl->communities[0];
581 	void __iomem *reg = community->regs + offset;
582 
583 	/* Write and simple read back to confirm the bus transferring done */
584 	writel(value, reg);
585 	readl(reg);
586 }
587 
588 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
589 				unsigned int reg)
590 {
591 	const struct intel_community *community = &pctrl->communities[0];
592 	unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
593 	unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
594 
595 	offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
596 
597 	return community->pad_regs + offset + reg;
598 }
599 
600 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
601 {
602 	return readl(chv_padreg(pctrl, pin, offset));
603 }
604 
605 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
606 {
607 	void __iomem *reg = chv_padreg(pctrl, pin, offset);
608 
609 	/* Write and simple read back to confirm the bus transferring done */
610 	writel(value, reg);
611 	readl(reg);
612 }
613 
614 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
615 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
616 {
617 	return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
618 }
619 
620 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
621 			     unsigned int offset)
622 {
623 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
624 	unsigned long flags;
625 	u32 ctrl0, ctrl1;
626 	bool locked;
627 
628 	raw_spin_lock_irqsave(&chv_lock, flags);
629 
630 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
631 	ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
632 	locked = chv_pad_locked(pctrl, offset);
633 
634 	raw_spin_unlock_irqrestore(&chv_lock, flags);
635 
636 	if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
637 		seq_puts(s, "GPIO ");
638 	} else {
639 		u32 mode;
640 
641 		mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
642 		mode >>= CHV_PADCTRL0_PMODE_SHIFT;
643 
644 		seq_printf(s, "mode %d ", mode);
645 	}
646 
647 	seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
648 
649 	if (locked)
650 		seq_puts(s, " [LOCKED]");
651 }
652 
653 static const struct pinctrl_ops chv_pinctrl_ops = {
654 	.get_groups_count = intel_get_groups_count,
655 	.get_group_name = intel_get_group_name,
656 	.get_group_pins = intel_get_group_pins,
657 	.pin_dbg_show = chv_pin_dbg_show,
658 };
659 
660 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
661 			      unsigned int function, unsigned int group)
662 {
663 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
664 	struct device *dev = pctrl->dev;
665 	const struct intel_pingroup *grp;
666 	unsigned long flags;
667 	int i;
668 
669 	grp = &pctrl->soc->groups[group];
670 
671 	raw_spin_lock_irqsave(&chv_lock, flags);
672 
673 	/* Check first that the pad is not locked */
674 	for (i = 0; i < grp->grp.npins; i++) {
675 		if (chv_pad_locked(pctrl, grp->grp.pins[i])) {
676 			raw_spin_unlock_irqrestore(&chv_lock, flags);
677 			dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);
678 			return -EBUSY;
679 		}
680 	}
681 
682 	for (i = 0; i < grp->grp.npins; i++) {
683 		int pin = grp->grp.pins[i];
684 		unsigned int mode;
685 		bool invert_oe;
686 		u32 value;
687 
688 		/* Check if there is pin-specific config */
689 		if (grp->modes)
690 			mode = grp->modes[i];
691 		else
692 			mode = grp->mode;
693 
694 		/* Extract OE inversion */
695 		invert_oe = mode & PINMODE_INVERT_OE;
696 		mode &= ~PINMODE_INVERT_OE;
697 
698 		value = chv_readl(pctrl, pin, CHV_PADCTRL0);
699 		/* Disable GPIO mode */
700 		value &= ~CHV_PADCTRL0_GPIOEN;
701 		/* Set to desired mode */
702 		value &= ~CHV_PADCTRL0_PMODE_MASK;
703 		value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
704 		chv_writel(pctrl, pin, CHV_PADCTRL0, value);
705 
706 		/* Update for invert_oe */
707 		value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
708 		if (invert_oe)
709 			value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
710 		chv_writel(pctrl, pin, CHV_PADCTRL1, value);
711 
712 		dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode,
713 			invert_oe ? "" : "not ");
714 	}
715 
716 	raw_spin_unlock_irqrestore(&chv_lock, flags);
717 
718 	return 0;
719 }
720 
721 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
722 				      unsigned int offset)
723 {
724 	u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
725 	u32 value;
726 
727 	/*
728 	 * One some devices the GPIO should output the inverted value from what
729 	 * device-drivers / ACPI code expects (inverted external buffer?). The
730 	 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
731 	 * preserve this flag if the pin is already setup as GPIO.
732 	 */
733 	value = chv_readl(pctrl, offset, CHV_PADCTRL0);
734 	if (value & CHV_PADCTRL0_GPIOEN)
735 		invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
736 
737 	value = chv_readl(pctrl, offset, CHV_PADCTRL1);
738 	value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
739 	value &= ~invrxtx_mask;
740 	chv_writel(pctrl, offset, CHV_PADCTRL1, value);
741 }
742 
743 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
744 				   struct pinctrl_gpio_range *range,
745 				   unsigned int offset)
746 {
747 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
748 	unsigned long flags;
749 	u32 value;
750 
751 	raw_spin_lock_irqsave(&chv_lock, flags);
752 
753 	if (chv_pad_locked(pctrl, offset)) {
754 		value = chv_readl(pctrl, offset, CHV_PADCTRL0);
755 		if (!(value & CHV_PADCTRL0_GPIOEN)) {
756 			/* Locked so cannot enable */
757 			raw_spin_unlock_irqrestore(&chv_lock, flags);
758 			return -EBUSY;
759 		}
760 	} else {
761 		struct intel_community_context *cctx = &pctrl->context.communities[0];
762 		int i;
763 
764 		/* Reset the interrupt mapping */
765 		for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
766 			if (cctx->intr_lines[i] == offset) {
767 				cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
768 				break;
769 			}
770 		}
771 
772 		/* Disable interrupt generation */
773 		chv_gpio_clear_triggering(pctrl, offset);
774 
775 		value = chv_readl(pctrl, offset, CHV_PADCTRL0);
776 
777 		/*
778 		 * If the pin is in HiZ mode (both TX and RX buffers are
779 		 * disabled) we turn it to be input now.
780 		 */
781 		if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
782 		     (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
783 			value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
784 			value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
785 		}
786 
787 		/* Switch to a GPIO mode */
788 		value |= CHV_PADCTRL0_GPIOEN;
789 		chv_writel(pctrl, offset, CHV_PADCTRL0, value);
790 	}
791 
792 	raw_spin_unlock_irqrestore(&chv_lock, flags);
793 
794 	return 0;
795 }
796 
797 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
798 				  struct pinctrl_gpio_range *range,
799 				  unsigned int offset)
800 {
801 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
802 	unsigned long flags;
803 
804 	raw_spin_lock_irqsave(&chv_lock, flags);
805 
806 	if (!chv_pad_locked(pctrl, offset))
807 		chv_gpio_clear_triggering(pctrl, offset);
808 
809 	raw_spin_unlock_irqrestore(&chv_lock, flags);
810 }
811 
812 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
813 				  struct pinctrl_gpio_range *range,
814 				  unsigned int offset, bool input)
815 {
816 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
817 	unsigned long flags;
818 	u32 ctrl0;
819 
820 	raw_spin_lock_irqsave(&chv_lock, flags);
821 
822 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
823 	if (input)
824 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
825 	else
826 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
827 	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
828 
829 	raw_spin_unlock_irqrestore(&chv_lock, flags);
830 
831 	return 0;
832 }
833 
834 static const struct pinmux_ops chv_pinmux_ops = {
835 	.get_functions_count = intel_get_functions_count,
836 	.get_function_name = intel_get_function_name,
837 	.get_function_groups = intel_get_function_groups,
838 	.set_mux = chv_pinmux_set_mux,
839 	.gpio_request_enable = chv_gpio_request_enable,
840 	.gpio_disable_free = chv_gpio_disable_free,
841 	.gpio_set_direction = chv_gpio_set_direction,
842 };
843 
844 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
845 			  unsigned long *config)
846 {
847 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
848 	enum pin_config_param param = pinconf_to_config_param(*config);
849 	unsigned long flags;
850 	u32 ctrl0, ctrl1;
851 	u16 arg = 0;
852 	u32 term;
853 
854 	raw_spin_lock_irqsave(&chv_lock, flags);
855 	ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
856 	ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
857 	raw_spin_unlock_irqrestore(&chv_lock, flags);
858 
859 	term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
860 
861 	switch (param) {
862 	case PIN_CONFIG_BIAS_DISABLE:
863 		if (term)
864 			return -EINVAL;
865 		break;
866 
867 	case PIN_CONFIG_BIAS_PULL_UP:
868 		if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
869 			return -EINVAL;
870 
871 		switch (term) {
872 		case CHV_PADCTRL0_TERM_20K:
873 			arg = 20000;
874 			break;
875 		case CHV_PADCTRL0_TERM_5K:
876 			arg = 5000;
877 			break;
878 		case CHV_PADCTRL0_TERM_1K:
879 			arg = 1000;
880 			break;
881 		}
882 
883 		break;
884 
885 	case PIN_CONFIG_BIAS_PULL_DOWN:
886 		if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
887 			return -EINVAL;
888 
889 		switch (term) {
890 		case CHV_PADCTRL0_TERM_20K:
891 			arg = 20000;
892 			break;
893 		case CHV_PADCTRL0_TERM_5K:
894 			arg = 5000;
895 			break;
896 		}
897 
898 		break;
899 
900 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
901 		u32 cfg;
902 
903 		cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
904 		cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
905 		if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
906 			return -EINVAL;
907 
908 		break;
909 
910 	case PIN_CONFIG_DRIVE_PUSH_PULL:
911 		if (ctrl1 & CHV_PADCTRL1_ODEN)
912 			return -EINVAL;
913 		break;
914 
915 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
916 		if (!(ctrl1 & CHV_PADCTRL1_ODEN))
917 			return -EINVAL;
918 		break;
919 	}
920 
921 	default:
922 		return -ENOTSUPP;
923 	}
924 
925 	*config = pinconf_to_config_packed(param, arg);
926 	return 0;
927 }
928 
929 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
930 			       enum pin_config_param param, u32 arg)
931 {
932 	unsigned long flags;
933 	u32 ctrl0, pull;
934 
935 	raw_spin_lock_irqsave(&chv_lock, flags);
936 	ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
937 
938 	switch (param) {
939 	case PIN_CONFIG_BIAS_DISABLE:
940 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
941 		break;
942 
943 	case PIN_CONFIG_BIAS_PULL_UP:
944 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
945 
946 		switch (arg) {
947 		case 1000:
948 			/* For 1k there is only pull up */
949 			pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
950 			break;
951 		case 5000:
952 			pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
953 			break;
954 		case 20000:
955 			pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
956 			break;
957 		default:
958 			raw_spin_unlock_irqrestore(&chv_lock, flags);
959 			return -EINVAL;
960 		}
961 
962 		ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
963 		break;
964 
965 	case PIN_CONFIG_BIAS_PULL_DOWN:
966 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
967 
968 		switch (arg) {
969 		case 5000:
970 			pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
971 			break;
972 		case 20000:
973 			pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
974 			break;
975 		default:
976 			raw_spin_unlock_irqrestore(&chv_lock, flags);
977 			return -EINVAL;
978 		}
979 
980 		ctrl0 |= pull;
981 		break;
982 
983 	default:
984 		raw_spin_unlock_irqrestore(&chv_lock, flags);
985 		return -EINVAL;
986 	}
987 
988 	chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
989 	raw_spin_unlock_irqrestore(&chv_lock, flags);
990 
991 	return 0;
992 }
993 
994 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
995 			       bool enable)
996 {
997 	unsigned long flags;
998 	u32 ctrl1;
999 
1000 	raw_spin_lock_irqsave(&chv_lock, flags);
1001 	ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
1002 
1003 	if (enable)
1004 		ctrl1 |= CHV_PADCTRL1_ODEN;
1005 	else
1006 		ctrl1 &= ~CHV_PADCTRL1_ODEN;
1007 
1008 	chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
1009 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1010 
1011 	return 0;
1012 }
1013 
1014 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1015 			  unsigned long *configs, unsigned int nconfigs)
1016 {
1017 	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1018 	struct device *dev = pctrl->dev;
1019 	enum pin_config_param param;
1020 	int i, ret;
1021 	u32 arg;
1022 
1023 	if (chv_pad_locked(pctrl, pin))
1024 		return -EBUSY;
1025 
1026 	for (i = 0; i < nconfigs; i++) {
1027 		param = pinconf_to_config_param(configs[i]);
1028 		arg = pinconf_to_config_argument(configs[i]);
1029 
1030 		switch (param) {
1031 		case PIN_CONFIG_BIAS_DISABLE:
1032 		case PIN_CONFIG_BIAS_PULL_UP:
1033 		case PIN_CONFIG_BIAS_PULL_DOWN:
1034 			ret = chv_config_set_pull(pctrl, pin, param, arg);
1035 			if (ret)
1036 				return ret;
1037 			break;
1038 
1039 		case PIN_CONFIG_DRIVE_PUSH_PULL:
1040 			ret = chv_config_set_oden(pctrl, pin, false);
1041 			if (ret)
1042 				return ret;
1043 			break;
1044 
1045 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1046 			ret = chv_config_set_oden(pctrl, pin, true);
1047 			if (ret)
1048 				return ret;
1049 			break;
1050 
1051 		default:
1052 			return -ENOTSUPP;
1053 		}
1054 
1055 		dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg);
1056 	}
1057 
1058 	return 0;
1059 }
1060 
1061 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1062 				unsigned int group,
1063 				unsigned long *config)
1064 {
1065 	const unsigned int *pins;
1066 	unsigned int npins;
1067 	int ret;
1068 
1069 	ret = intel_get_group_pins(pctldev, group, &pins, &npins);
1070 	if (ret)
1071 		return ret;
1072 
1073 	ret = chv_config_get(pctldev, pins[0], config);
1074 	if (ret)
1075 		return ret;
1076 
1077 	return 0;
1078 }
1079 
1080 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1081 				unsigned int group, unsigned long *configs,
1082 				unsigned int num_configs)
1083 {
1084 	const unsigned int *pins;
1085 	unsigned int npins;
1086 	int i, ret;
1087 
1088 	ret = intel_get_group_pins(pctldev, group, &pins, &npins);
1089 	if (ret)
1090 		return ret;
1091 
1092 	for (i = 0; i < npins; i++) {
1093 		ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1094 		if (ret)
1095 			return ret;
1096 	}
1097 
1098 	return 0;
1099 }
1100 
1101 static const struct pinconf_ops chv_pinconf_ops = {
1102 	.is_generic = true,
1103 	.pin_config_set = chv_config_set,
1104 	.pin_config_get = chv_config_get,
1105 	.pin_config_group_get = chv_config_group_get,
1106 	.pin_config_group_set = chv_config_group_set,
1107 };
1108 
1109 static struct pinctrl_desc chv_pinctrl_desc = {
1110 	.pctlops = &chv_pinctrl_ops,
1111 	.pmxops = &chv_pinmux_ops,
1112 	.confops = &chv_pinconf_ops,
1113 	.owner = THIS_MODULE,
1114 };
1115 
1116 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1117 {
1118 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1119 	unsigned long flags;
1120 	u32 ctrl0, cfg;
1121 
1122 	raw_spin_lock_irqsave(&chv_lock, flags);
1123 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1124 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1125 
1126 	cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1127 	cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1128 
1129 	if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1130 		return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1131 	return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1132 }
1133 
1134 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1135 {
1136 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1137 	unsigned long flags;
1138 	u32 ctrl0;
1139 
1140 	raw_spin_lock_irqsave(&chv_lock, flags);
1141 
1142 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1143 
1144 	if (value)
1145 		ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1146 	else
1147 		ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1148 
1149 	chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
1150 
1151 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1152 }
1153 
1154 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1155 {
1156 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1157 	u32 ctrl0, direction;
1158 	unsigned long flags;
1159 
1160 	raw_spin_lock_irqsave(&chv_lock, flags);
1161 	ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1162 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1163 
1164 	direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1165 	direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1166 
1167 	if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1168 		return GPIO_LINE_DIRECTION_OUT;
1169 
1170 	return GPIO_LINE_DIRECTION_IN;
1171 }
1172 
1173 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1174 {
1175 	return pinctrl_gpio_direction_input(chip->base + offset);
1176 }
1177 
1178 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1179 				     int value)
1180 {
1181 	chv_gpio_set(chip, offset, value);
1182 	return pinctrl_gpio_direction_output(chip->base + offset);
1183 }
1184 
1185 static const struct gpio_chip chv_gpio_chip = {
1186 	.owner = THIS_MODULE,
1187 	.request = gpiochip_generic_request,
1188 	.free = gpiochip_generic_free,
1189 	.get_direction = chv_gpio_get_direction,
1190 	.direction_input = chv_gpio_direction_input,
1191 	.direction_output = chv_gpio_direction_output,
1192 	.get = chv_gpio_get,
1193 	.set = chv_gpio_set,
1194 };
1195 
1196 static void chv_gpio_irq_ack(struct irq_data *d)
1197 {
1198 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1199 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1200 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1201 	u32 intr_line;
1202 
1203 	raw_spin_lock(&chv_lock);
1204 
1205 	intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1206 	intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1207 	intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1208 	chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
1209 
1210 	raw_spin_unlock(&chv_lock);
1211 }
1212 
1213 static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1214 {
1215 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1216 	u32 value, intr_line;
1217 	unsigned long flags;
1218 
1219 	raw_spin_lock_irqsave(&chv_lock, flags);
1220 
1221 	intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1222 	intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1223 	intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1224 
1225 	value = chv_pctrl_readl(pctrl, CHV_INTMASK);
1226 	if (mask)
1227 		value &= ~BIT(intr_line);
1228 	else
1229 		value |= BIT(intr_line);
1230 	chv_pctrl_writel(pctrl, CHV_INTMASK, value);
1231 
1232 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1233 }
1234 
1235 static void chv_gpio_irq_mask(struct irq_data *d)
1236 {
1237 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1238 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1239 
1240 	chv_gpio_irq_mask_unmask(gc, hwirq, true);
1241 	gpiochip_disable_irq(gc, hwirq);
1242 }
1243 
1244 static void chv_gpio_irq_unmask(struct irq_data *d)
1245 {
1246 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1247 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1248 
1249 	gpiochip_enable_irq(gc, hwirq);
1250 	chv_gpio_irq_mask_unmask(gc, hwirq, false);
1251 }
1252 
1253 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1254 {
1255 	/*
1256 	 * Check if the interrupt has been requested with 0 as triggering
1257 	 * type. In that case it is assumed that the current values
1258 	 * programmed to the hardware are used (e.g BIOS configured
1259 	 * defaults).
1260 	 *
1261 	 * In that case ->irq_set_type() will never be called so we need to
1262 	 * read back the values from hardware now, set correct flow handler
1263 	 * and update mappings before the interrupt is being used.
1264 	 */
1265 	if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1266 		struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1267 		struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1268 		struct device *dev = pctrl->dev;
1269 		struct intel_community_context *cctx = &pctrl->context.communities[0];
1270 		irq_hw_number_t hwirq = irqd_to_hwirq(d);
1271 		irq_flow_handler_t handler;
1272 		unsigned long flags;
1273 		u32 intsel, value;
1274 
1275 		raw_spin_lock_irqsave(&chv_lock, flags);
1276 		intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1277 		intsel &= CHV_PADCTRL0_INTSEL_MASK;
1278 		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1279 
1280 		value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
1281 		if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1282 			handler = handle_level_irq;
1283 		else
1284 			handler = handle_edge_irq;
1285 
1286 		if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
1287 			irq_set_handler_locked(d, handler);
1288 			dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n",
1289 				intsel, hwirq);
1290 			cctx->intr_lines[intsel] = hwirq;
1291 		}
1292 		raw_spin_unlock_irqrestore(&chv_lock, flags);
1293 	}
1294 
1295 	chv_gpio_irq_unmask(d);
1296 	return 0;
1297 }
1298 
1299 static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin)
1300 {
1301 	struct device *dev = pctrl->dev;
1302 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1303 	const struct intel_community *community = &pctrl->communities[0];
1304 	u32 value, intsel;
1305 	int i;
1306 
1307 	value = chv_readl(pctrl, pin, CHV_PADCTRL0);
1308 	intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT;
1309 
1310 	if (cctx->intr_lines[intsel] == pin)
1311 		return 0;
1312 
1313 	if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
1314 		dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin);
1315 		cctx->intr_lines[intsel] = pin;
1316 		return 0;
1317 	}
1318 
1319 	/*
1320 	 * The interrupt line selected by the BIOS is already in use by
1321 	 * another pin, this is a known BIOS bug found on several models.
1322 	 * But this may also be caused by Linux deciding to use a pin as
1323 	 * IRQ which was not expected to be used as such by the BIOS authors,
1324 	 * so log this at info level only.
1325 	 */
1326 	dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel,
1327 		 cctx->intr_lines[intsel], pin);
1328 
1329 	if (chv_pad_locked(pctrl, pin))
1330 		return -EBUSY;
1331 
1332 	/*
1333 	 * The BIOS fills the interrupt lines from 0 counting up, start at
1334 	 * the other end to find a free interrupt line to workaround this.
1335 	 */
1336 	for (i = community->nirqs - 1; i >= 0; i--) {
1337 		if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ)
1338 			break;
1339 	}
1340 	if (i < 0)
1341 		return -EBUSY;
1342 
1343 	dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i);
1344 
1345 	value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT);
1346 	chv_writel(pctrl, pin, CHV_PADCTRL0, value);
1347 	cctx->intr_lines[i] = pin;
1348 
1349 	return 0;
1350 }
1351 
1352 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1353 {
1354 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1355 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1356 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
1357 	unsigned long flags;
1358 	u32 value;
1359 	int ret;
1360 
1361 	raw_spin_lock_irqsave(&chv_lock, flags);
1362 
1363 	ret = chv_gpio_set_intr_line(pctrl, hwirq);
1364 	if (ret) {
1365 		raw_spin_unlock_irqrestore(&chv_lock, flags);
1366 		return ret;
1367 	}
1368 
1369 	/*
1370 	 * Pins which can be used as shared interrupt are configured in
1371 	 * BIOS. Driver trusts BIOS configurations and assigns different
1372 	 * handler according to the irq type.
1373 	 *
1374 	 * Driver needs to save the mapping between each pin and
1375 	 * its interrupt line.
1376 	 * 1. If the pin cfg is locked in BIOS:
1377 	 *	Trust BIOS has programmed IntWakeCfg bits correctly,
1378 	 *	driver just needs to save the mapping.
1379 	 * 2. If the pin cfg is not locked in BIOS:
1380 	 *	Driver programs the IntWakeCfg bits and save the mapping.
1381 	 */
1382 	if (!chv_pad_locked(pctrl, hwirq)) {
1383 		value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
1384 		value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1385 		value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1386 
1387 		if (type & IRQ_TYPE_EDGE_BOTH) {
1388 			if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1389 				value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1390 			else if (type & IRQ_TYPE_EDGE_RISING)
1391 				value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1392 			else if (type & IRQ_TYPE_EDGE_FALLING)
1393 				value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1394 		} else if (type & IRQ_TYPE_LEVEL_MASK) {
1395 			value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1396 			if (type & IRQ_TYPE_LEVEL_LOW)
1397 				value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1398 		}
1399 
1400 		chv_writel(pctrl, hwirq, CHV_PADCTRL1, value);
1401 	}
1402 
1403 	if (type & IRQ_TYPE_EDGE_BOTH)
1404 		irq_set_handler_locked(d, handle_edge_irq);
1405 	else if (type & IRQ_TYPE_LEVEL_MASK)
1406 		irq_set_handler_locked(d, handle_level_irq);
1407 
1408 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1409 
1410 	return 0;
1411 }
1412 
1413 static const struct irq_chip chv_gpio_irq_chip = {
1414 	.name		= "chv-gpio",
1415 	.irq_startup	= chv_gpio_irq_startup,
1416 	.irq_ack	= chv_gpio_irq_ack,
1417 	.irq_mask	= chv_gpio_irq_mask,
1418 	.irq_unmask	= chv_gpio_irq_unmask,
1419 	.irq_set_type	= chv_gpio_irq_type,
1420 	.flags		= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
1421 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
1422 };
1423 
1424 static void chv_gpio_irq_handler(struct irq_desc *desc)
1425 {
1426 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1427 	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1428 	struct device *dev = pctrl->dev;
1429 	const struct intel_community *community = &pctrl->communities[0];
1430 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1431 	struct irq_chip *chip = irq_desc_get_chip(desc);
1432 	unsigned long pending;
1433 	unsigned long flags;
1434 	u32 intr_line;
1435 
1436 	chained_irq_enter(chip, desc);
1437 
1438 	raw_spin_lock_irqsave(&chv_lock, flags);
1439 	pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
1440 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1441 
1442 	for_each_set_bit(intr_line, &pending, community->nirqs) {
1443 		unsigned int offset;
1444 
1445 		offset = cctx->intr_lines[intr_line];
1446 		if (offset == CHV_INVALID_HWIRQ) {
1447 			dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line);
1448 			/* Some boards expect hwirq 0 to trigger in this case */
1449 			offset = 0;
1450 		}
1451 
1452 		generic_handle_domain_irq(gc->irq.domain, offset);
1453 	}
1454 
1455 	chained_irq_exit(chip, desc);
1456 }
1457 
1458 /*
1459  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1460  * tables. Since we leave GPIOs that are not capable of generating
1461  * interrupts out of the irqdomain the numbering will be different and
1462  * cause devices using the hardcoded IRQ numbers fail. In order not to
1463  * break such machines we will only mask pins from irqdomain if the machine
1464  * is not listed below.
1465  */
1466 static const struct dmi_system_id chv_no_valid_mask[] = {
1467 	/* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1468 	{
1469 		.ident = "Intel_Strago based Chromebooks (All models)",
1470 		.matches = {
1471 			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1472 			DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1473 		},
1474 	},
1475 	{
1476 		.ident = "HP Chromebook 11 G5 (Setzer)",
1477 		.matches = {
1478 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1479 			DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1480 		},
1481 	},
1482 	{
1483 		.ident = "Acer Chromebook R11 (Cyan)",
1484 		.matches = {
1485 			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1486 			DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1487 		},
1488 	},
1489 	{
1490 		.ident = "Samsung Chromebook 3 (Celes)",
1491 		.matches = {
1492 			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1493 			DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1494 		},
1495 	},
1496 	{}
1497 };
1498 
1499 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1500 				    unsigned long *valid_mask,
1501 				    unsigned int ngpios)
1502 {
1503 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1504 	const struct intel_community *community = &pctrl->communities[0];
1505 	int i;
1506 
1507 	/* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1508 	for (i = 0; i < pctrl->soc->npins; i++) {
1509 		const struct pinctrl_pin_desc *desc;
1510 		u32 intsel;
1511 
1512 		desc = &pctrl->soc->pins[i];
1513 
1514 		intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1515 		intsel &= CHV_PADCTRL0_INTSEL_MASK;
1516 		intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1517 
1518 		if (intsel >= community->nirqs)
1519 			clear_bit(desc->number, valid_mask);
1520 	}
1521 }
1522 
1523 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1524 {
1525 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1526 	const struct intel_community *community = &pctrl->communities[0];
1527 
1528 	/*
1529 	 * The same set of machines in chv_no_valid_mask[] have incorrectly
1530 	 * configured GPIOs that generate spurious interrupts so we use
1531 	 * this same list to apply another quirk for them.
1532 	 *
1533 	 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1534 	 */
1535 	if (!pctrl->chip.irq.init_valid_mask) {
1536 		/*
1537 		 * Mask all interrupts the community is able to generate
1538 		 * but leave the ones that can only generate GPEs unmasked.
1539 		 */
1540 		chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
1541 	}
1542 
1543 	/* Clear all interrupts */
1544 	chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1545 
1546 	return 0;
1547 }
1548 
1549 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1550 {
1551 	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1552 	struct device *dev = pctrl->dev;
1553 	const struct intel_community *community = &pctrl->communities[0];
1554 	const struct intel_padgroup *gpp;
1555 	int ret, i;
1556 
1557 	for (i = 0; i < community->ngpps; i++) {
1558 		gpp = &community->gpps[i];
1559 		ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);
1560 		if (ret) {
1561 			dev_err(dev, "failed to add GPIO pin range\n");
1562 			return ret;
1563 		}
1564 	}
1565 
1566 	return 0;
1567 }
1568 
1569 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1570 {
1571 	const struct intel_community *community = &pctrl->communities[0];
1572 	const struct intel_padgroup *gpp;
1573 	struct gpio_chip *chip = &pctrl->chip;
1574 	struct device *dev = pctrl->dev;
1575 	bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1576 	int ret, i, irq_base;
1577 
1578 	*chip = chv_gpio_chip;
1579 
1580 	chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
1581 	chip->label = dev_name(dev);
1582 	chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1583 	chip->parent = dev;
1584 	chip->base = -1;
1585 
1586 	pctrl->irq = irq;
1587 
1588 	gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip);
1589 	chip->irq.init_hw = chv_gpio_irq_init_hw;
1590 	chip->irq.parent_handler = chv_gpio_irq_handler;
1591 	chip->irq.num_parents = 1;
1592 	chip->irq.parents = &pctrl->irq;
1593 	chip->irq.default_type = IRQ_TYPE_NONE;
1594 	chip->irq.handler = handle_bad_irq;
1595 	if (need_valid_mask) {
1596 		chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1597 	} else {
1598 		irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);
1599 		if (irq_base < 0) {
1600 			dev_err(dev, "Failed to allocate IRQ numbers\n");
1601 			return irq_base;
1602 		}
1603 	}
1604 
1605 	ret = devm_gpiochip_add_data(dev, chip, pctrl);
1606 	if (ret) {
1607 		dev_err(dev, "Failed to register gpiochip\n");
1608 		return ret;
1609 	}
1610 
1611 	if (!need_valid_mask) {
1612 		for (i = 0; i < community->ngpps; i++) {
1613 			gpp = &community->gpps[i];
1614 
1615 			irq_domain_associate_many(chip->irq.domain, irq_base,
1616 						  gpp->base, gpp->size);
1617 			irq_base += gpp->size;
1618 		}
1619 	}
1620 
1621 	return 0;
1622 }
1623 
1624 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1625 	acpi_physical_address address, u32 bits, u64 *value,
1626 	void *handler_context, void *region_context)
1627 {
1628 	struct intel_pinctrl *pctrl = region_context;
1629 	unsigned long flags;
1630 	acpi_status ret = AE_OK;
1631 
1632 	raw_spin_lock_irqsave(&chv_lock, flags);
1633 
1634 	if (function == ACPI_WRITE)
1635 		chv_pctrl_writel(pctrl, address, *value);
1636 	else if (function == ACPI_READ)
1637 		*value = chv_pctrl_readl(pctrl, address);
1638 	else
1639 		ret = AE_BAD_PARAMETER;
1640 
1641 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1642 
1643 	return ret;
1644 }
1645 
1646 static int chv_pinctrl_probe(struct platform_device *pdev)
1647 {
1648 	const struct intel_pinctrl_soc_data *soc_data;
1649 	struct intel_community_context *cctx;
1650 	struct intel_community *community;
1651 	struct device *dev = &pdev->dev;
1652 	struct intel_pinctrl *pctrl;
1653 	acpi_status status;
1654 	unsigned int i;
1655 	int ret, irq;
1656 
1657 	soc_data = intel_pinctrl_get_soc_data(pdev);
1658 	if (IS_ERR(soc_data))
1659 		return PTR_ERR(soc_data);
1660 
1661 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1662 	if (!pctrl)
1663 		return -ENOMEM;
1664 
1665 	pctrl->dev = dev;
1666 	pctrl->soc = soc_data;
1667 
1668 	pctrl->ncommunities = pctrl->soc->ncommunities;
1669 	pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
1670 					  pctrl->ncommunities * sizeof(*pctrl->communities),
1671 					  GFP_KERNEL);
1672 	if (!pctrl->communities)
1673 		return -ENOMEM;
1674 
1675 	community = &pctrl->communities[0];
1676 	community->regs = devm_platform_ioremap_resource(pdev, 0);
1677 	if (IS_ERR(community->regs))
1678 		return PTR_ERR(community->regs);
1679 
1680 	community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
1681 
1682 #ifdef CONFIG_PM_SLEEP
1683 	pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
1684 					   sizeof(*pctrl->context.pads),
1685 					   GFP_KERNEL);
1686 	if (!pctrl->context.pads)
1687 		return -ENOMEM;
1688 #endif
1689 
1690 	pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
1691 						  sizeof(*pctrl->context.communities),
1692 						  GFP_KERNEL);
1693 	if (!pctrl->context.communities)
1694 		return -ENOMEM;
1695 
1696 	cctx = &pctrl->context.communities[0];
1697 	for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++)
1698 		cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
1699 
1700 	irq = platform_get_irq(pdev, 0);
1701 	if (irq < 0)
1702 		return irq;
1703 
1704 	pctrl->pctldesc = chv_pinctrl_desc;
1705 	pctrl->pctldesc.name = dev_name(dev);
1706 	pctrl->pctldesc.pins = pctrl->soc->pins;
1707 	pctrl->pctldesc.npins = pctrl->soc->npins;
1708 
1709 	pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1710 	if (IS_ERR(pctrl->pctldev)) {
1711 		dev_err(dev, "failed to register pinctrl driver\n");
1712 		return PTR_ERR(pctrl->pctldev);
1713 	}
1714 
1715 	ret = chv_gpio_probe(pctrl, irq);
1716 	if (ret)
1717 		return ret;
1718 
1719 	status = acpi_install_address_space_handler(ACPI_HANDLE(dev),
1720 					community->acpi_space_id,
1721 					chv_pinctrl_mmio_access_handler,
1722 					NULL, pctrl);
1723 	if (ACPI_FAILURE(status))
1724 		dev_err(dev, "failed to install ACPI addr space handler\n");
1725 
1726 	platform_set_drvdata(pdev, pctrl);
1727 
1728 	return 0;
1729 }
1730 
1731 static int chv_pinctrl_remove(struct platform_device *pdev)
1732 {
1733 	struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1734 	const struct intel_community *community = &pctrl->communities[0];
1735 
1736 	acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev),
1737 					  community->acpi_space_id,
1738 					  chv_pinctrl_mmio_access_handler);
1739 
1740 	return 0;
1741 }
1742 
1743 static int chv_pinctrl_suspend_noirq(struct device *dev)
1744 {
1745 	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1746 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1747 	unsigned long flags;
1748 	int i;
1749 
1750 	raw_spin_lock_irqsave(&chv_lock, flags);
1751 
1752 	cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
1753 
1754 	for (i = 0; i < pctrl->soc->npins; i++) {
1755 		const struct pinctrl_pin_desc *desc;
1756 		struct intel_pad_context *ctx = &pctrl->context.pads[i];
1757 
1758 		desc = &pctrl->soc->pins[i];
1759 		if (chv_pad_locked(pctrl, desc->number))
1760 			continue;
1761 
1762 		ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1763 		ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
1764 
1765 		ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1766 	}
1767 
1768 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1769 
1770 	return 0;
1771 }
1772 
1773 static int chv_pinctrl_resume_noirq(struct device *dev)
1774 {
1775 	struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1776 	struct intel_community_context *cctx = &pctrl->context.communities[0];
1777 	unsigned long flags;
1778 	int i;
1779 
1780 	raw_spin_lock_irqsave(&chv_lock, flags);
1781 
1782 	/*
1783 	 * Mask all interrupts before restoring per-pin configuration
1784 	 * registers because we don't know in which state BIOS left them
1785 	 * upon exiting suspend.
1786 	 */
1787 	chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
1788 
1789 	for (i = 0; i < pctrl->soc->npins; i++) {
1790 		const struct pinctrl_pin_desc *desc;
1791 		struct intel_pad_context *ctx = &pctrl->context.pads[i];
1792 		u32 val;
1793 
1794 		desc = &pctrl->soc->pins[i];
1795 		if (chv_pad_locked(pctrl, desc->number))
1796 			continue;
1797 
1798 		/* Only restore if our saved state differs from the current */
1799 		val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1800 		val &= ~CHV_PADCTRL0_GPIORXSTATE;
1801 		if (ctx->padctrl0 != val) {
1802 			chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
1803 			dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number,
1804 				chv_readl(pctrl, desc->number, CHV_PADCTRL0));
1805 		}
1806 
1807 		val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1808 		if (ctx->padctrl1 != val) {
1809 			chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
1810 			dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number,
1811 				chv_readl(pctrl, desc->number, CHV_PADCTRL1));
1812 		}
1813 	}
1814 
1815 	/*
1816 	 * Now that all pins are restored to known state, we can restore
1817 	 * the interrupt mask register as well.
1818 	 */
1819 	chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1820 	chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
1821 
1822 	raw_spin_unlock_irqrestore(&chv_lock, flags);
1823 
1824 	return 0;
1825 }
1826 
1827 static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops,
1828 			       chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq);
1829 
1830 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1831 	{ "INT33FF", (kernel_ulong_t)chv_soc_data },
1832 	{ }
1833 };
1834 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1835 
1836 static struct platform_driver chv_pinctrl_driver = {
1837 	.probe = chv_pinctrl_probe,
1838 	.remove = chv_pinctrl_remove,
1839 	.driver = {
1840 		.name = "cherryview-pinctrl",
1841 		.pm = pm_sleep_ptr(&chv_pinctrl_pm_ops),
1842 		.acpi_match_table = chv_pinctrl_acpi_match,
1843 	},
1844 };
1845 
1846 static int __init chv_pinctrl_init(void)
1847 {
1848 	return platform_driver_register(&chv_pinctrl_driver);
1849 }
1850 subsys_initcall(chv_pinctrl_init);
1851 
1852 static void __exit chv_pinctrl_exit(void)
1853 {
1854 	platform_driver_unregister(&chv_pinctrl_driver);
1855 }
1856 module_exit(chv_pinctrl_exit);
1857 
1858 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1859 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1860 MODULE_LICENSE("GPL v2");
1861 MODULE_IMPORT_NS(PINCTRL_INTEL);
1862