1 /* 2 * Cherryview/Braswell pinctrl driver 3 * 4 * Copyright (C) 2014, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * 7 * This driver is based on the original Cherryview GPIO driver by 8 * Ning Li <ning.li@intel.com> 9 * Alan Cox <alan@linux.intel.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/types.h> 20 #include <linux/gpio.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/acpi.h> 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/platform_device.h> 28 29 #define CHV_INTSTAT 0x300 30 #define CHV_INTMASK 0x380 31 32 #define FAMILY_PAD_REGS_OFF 0x4400 33 #define FAMILY_PAD_REGS_SIZE 0x400 34 #define MAX_FAMILY_PAD_GPIO_NO 15 35 #define GPIO_REGS_SIZE 8 36 37 #define CHV_PADCTRL0 0x000 38 #define CHV_PADCTRL0_INTSEL_SHIFT 28 39 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 40 #define CHV_PADCTRL0_TERM_UP BIT(23) 41 #define CHV_PADCTRL0_TERM_SHIFT 20 42 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 43 #define CHV_PADCTRL0_TERM_20K 1 44 #define CHV_PADCTRL0_TERM_5K 2 45 #define CHV_PADCTRL0_TERM_1K 4 46 #define CHV_PADCTRL0_PMODE_SHIFT 16 47 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 48 #define CHV_PADCTRL0_GPIOEN BIT(15) 49 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 50 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 51 #define CHV_PADCTRL0_GPIOCFG_GPIO 0 52 #define CHV_PADCTRL0_GPIOCFG_GPO 1 53 #define CHV_PADCTRL0_GPIOCFG_GPI 2 54 #define CHV_PADCTRL0_GPIOCFG_HIZ 3 55 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 56 #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 57 58 #define CHV_PADCTRL1 0x004 59 #define CHV_PADCTRL1_CFGLOCK BIT(31) 60 #define CHV_PADCTRL1_INVRXTX_SHIFT 4 61 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 62 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 63 #define CHV_PADCTRL1_ODEN BIT(3) 64 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 65 #define CHV_PADCTRL1_INTWAKECFG_MASK 7 66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 67 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 68 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 70 71 /** 72 * struct chv_alternate_function - A per group or per pin alternate function 73 * @pin: Pin number (only used in per pin configs) 74 * @mode: Mode the pin should be set in 75 * @invert_oe: Invert OE for this pin 76 */ 77 struct chv_alternate_function { 78 unsigned pin; 79 u8 mode; 80 bool invert_oe; 81 }; 82 83 /** 84 * struct chv_pincgroup - describes a CHV pin group 85 * @name: Name of the group 86 * @pins: An array of pins in this group 87 * @npins: Number of pins in this group 88 * @altfunc: Alternate function applied to all pins in this group 89 * @overrides: Alternate function override per pin or %NULL if not used 90 * @noverrides: Number of per pin alternate function overrides if 91 * @overrides != NULL. 92 */ 93 struct chv_pingroup { 94 const char *name; 95 const unsigned *pins; 96 size_t npins; 97 struct chv_alternate_function altfunc; 98 const struct chv_alternate_function *overrides; 99 size_t noverrides; 100 }; 101 102 /** 103 * struct chv_function - A CHV pinmux function 104 * @name: Name of the function 105 * @groups: An array of groups for this function 106 * @ngroups: Number of groups in @groups 107 */ 108 struct chv_function { 109 const char *name; 110 const char * const *groups; 111 size_t ngroups; 112 }; 113 114 /** 115 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 116 * @base: Start pin number 117 * @npins: Number of pins in this range 118 */ 119 struct chv_gpio_pinrange { 120 unsigned base; 121 unsigned npins; 122 }; 123 124 /** 125 * struct chv_community - A community specific configuration 126 * @uid: ACPI _UID used to match the community 127 * @pins: All pins in this community 128 * @npins: Number of pins 129 * @groups: All groups in this community 130 * @ngroups: Number of groups 131 * @functions: All functions in this community 132 * @nfunctions: Number of functions 133 * @ngpios: Number of GPIOs in this community 134 * @gpio_ranges: An array of GPIO ranges in this community 135 * @ngpio_ranges: Number of GPIO ranges 136 * @ngpios: Total number of GPIOs in this community 137 */ 138 struct chv_community { 139 const char *uid; 140 const struct pinctrl_pin_desc *pins; 141 size_t npins; 142 const struct chv_pingroup *groups; 143 size_t ngroups; 144 const struct chv_function *functions; 145 size_t nfunctions; 146 const struct chv_gpio_pinrange *gpio_ranges; 147 size_t ngpio_ranges; 148 size_t ngpios; 149 }; 150 151 struct chv_pin_context { 152 u32 padctrl0; 153 u32 padctrl1; 154 }; 155 156 /** 157 * struct chv_pinctrl - CHV pinctrl private structure 158 * @dev: Pointer to the parent device 159 * @pctldesc: Pin controller description 160 * @pctldev: Pointer to the pin controller device 161 * @chip: GPIO chip in this pin controller 162 * @regs: MMIO registers 163 * @lock: Lock to serialize register accesses 164 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 165 * offset (in GPIO number space) 166 * @community: Community this pinctrl instance represents 167 * 168 * The first group in @groups is expected to contain all pins that can be 169 * used as GPIOs. 170 */ 171 struct chv_pinctrl { 172 struct device *dev; 173 struct pinctrl_desc pctldesc; 174 struct pinctrl_dev *pctldev; 175 struct gpio_chip chip; 176 void __iomem *regs; 177 raw_spinlock_t lock; 178 unsigned intr_lines[16]; 179 const struct chv_community *community; 180 u32 saved_intmask; 181 struct chv_pin_context *saved_pin_context; 182 }; 183 184 #define ALTERNATE_FUNCTION(p, m, i) \ 185 { \ 186 .pin = (p), \ 187 .mode = (m), \ 188 .invert_oe = (i), \ 189 } 190 191 #define PIN_GROUP(n, p, m, i) \ 192 { \ 193 .name = (n), \ 194 .pins = (p), \ 195 .npins = ARRAY_SIZE((p)), \ 196 .altfunc.mode = (m), \ 197 .altfunc.invert_oe = (i), \ 198 } 199 200 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 201 { \ 202 .name = (n), \ 203 .pins = (p), \ 204 .npins = ARRAY_SIZE((p)), \ 205 .altfunc.mode = (m), \ 206 .altfunc.invert_oe = (i), \ 207 .overrides = (o), \ 208 .noverrides = ARRAY_SIZE((o)), \ 209 } 210 211 #define FUNCTION(n, g) \ 212 { \ 213 .name = (n), \ 214 .groups = (g), \ 215 .ngroups = ARRAY_SIZE((g)), \ 216 } 217 218 #define GPIO_PINRANGE(start, end) \ 219 { \ 220 .base = (start), \ 221 .npins = (end) - (start) + 1, \ 222 } 223 224 static const struct pinctrl_pin_desc southwest_pins[] = { 225 PINCTRL_PIN(0, "FST_SPI_D2"), 226 PINCTRL_PIN(1, "FST_SPI_D0"), 227 PINCTRL_PIN(2, "FST_SPI_CLK"), 228 PINCTRL_PIN(3, "FST_SPI_D3"), 229 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 230 PINCTRL_PIN(5, "FST_SPI_D1"), 231 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 232 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 233 234 PINCTRL_PIN(15, "UART1_RTS_B"), 235 PINCTRL_PIN(16, "UART1_RXD"), 236 PINCTRL_PIN(17, "UART2_RXD"), 237 PINCTRL_PIN(18, "UART1_CTS_B"), 238 PINCTRL_PIN(19, "UART2_RTS_B"), 239 PINCTRL_PIN(20, "UART1_TXD"), 240 PINCTRL_PIN(21, "UART2_TXD"), 241 PINCTRL_PIN(22, "UART2_CTS_B"), 242 243 PINCTRL_PIN(30, "MF_HDA_CLK"), 244 PINCTRL_PIN(31, "MF_HDA_RSTB"), 245 PINCTRL_PIN(32, "MF_HDA_SDIO"), 246 PINCTRL_PIN(33, "MF_HDA_SDO"), 247 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 248 PINCTRL_PIN(35, "MF_HDA_SYNC"), 249 PINCTRL_PIN(36, "MF_HDA_SDI1"), 250 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 251 252 PINCTRL_PIN(45, "I2C5_SDA"), 253 PINCTRL_PIN(46, "I2C4_SDA"), 254 PINCTRL_PIN(47, "I2C6_SDA"), 255 PINCTRL_PIN(48, "I2C5_SCL"), 256 PINCTRL_PIN(49, "I2C_NFC_SDA"), 257 PINCTRL_PIN(50, "I2C4_SCL"), 258 PINCTRL_PIN(51, "I2C6_SCL"), 259 PINCTRL_PIN(52, "I2C_NFC_SCL"), 260 261 PINCTRL_PIN(60, "I2C1_SDA"), 262 PINCTRL_PIN(61, "I2C0_SDA"), 263 PINCTRL_PIN(62, "I2C2_SDA"), 264 PINCTRL_PIN(63, "I2C1_SCL"), 265 PINCTRL_PIN(64, "I2C3_SDA"), 266 PINCTRL_PIN(65, "I2C0_SCL"), 267 PINCTRL_PIN(66, "I2C2_SCL"), 268 PINCTRL_PIN(67, "I2C3_SCL"), 269 270 PINCTRL_PIN(75, "SATA_GP0"), 271 PINCTRL_PIN(76, "SATA_GP1"), 272 PINCTRL_PIN(77, "SATA_LEDN"), 273 PINCTRL_PIN(78, "SATA_GP2"), 274 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 275 PINCTRL_PIN(80, "SATA_GP3"), 276 PINCTRL_PIN(81, "MF_SMB_CLK"), 277 PINCTRL_PIN(82, "MF_SMB_DATA"), 278 279 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 280 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 281 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 282 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 283 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 284 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 285 PINCTRL_PIN(96, "GP_SSP_2_FS"), 286 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 287 }; 288 289 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 290 static const unsigned southwest_uart0_pins[] = { 16, 20 }; 291 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 292 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 293 static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 294 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 295 static const unsigned southwest_lpe_pins[] = { 296 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 297 }; 298 static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 299 static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 300 static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 301 static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 302 static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 303 static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 304 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 305 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 306 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 307 308 /* LPE I2S TXD pins need to have invert_oe set */ 309 static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 310 ALTERNATE_FUNCTION(30, 1, true), 311 ALTERNATE_FUNCTION(34, 1, true), 312 ALTERNATE_FUNCTION(97, 1, true), 313 }; 314 315 /* 316 * Two spi3 chipselects are available in different mode than the main spi3 317 * functionality, which is using mode 1. 318 */ 319 static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 320 ALTERNATE_FUNCTION(76, 3, false), 321 ALTERNATE_FUNCTION(80, 3, false), 322 }; 323 324 static const struct chv_pingroup southwest_groups[] = { 325 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 326 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 327 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 328 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 329 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 330 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 331 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 332 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 333 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 334 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 335 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 336 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 337 338 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 339 southwest_lpe_altfuncs), 340 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 341 southwest_spi3_altfuncs), 342 }; 343 344 static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 345 static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 346 static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 347 static const char * const southwest_hda_groups[] = { "hda_grp" }; 348 static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 349 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 350 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 351 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 352 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 353 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 354 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 355 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 356 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 357 static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 358 359 /* 360 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 361 * enabled only as GPIOs. 362 */ 363 static const struct chv_function southwest_functions[] = { 364 FUNCTION("uart0", southwest_uart0_groups), 365 FUNCTION("uart1", southwest_uart1_groups), 366 FUNCTION("uart2", southwest_uart2_groups), 367 FUNCTION("hda", southwest_hda_groups), 368 FUNCTION("lpe", southwest_lpe_groups), 369 FUNCTION("i2c0", southwest_i2c0_groups), 370 FUNCTION("i2c1", southwest_i2c1_groups), 371 FUNCTION("i2c2", southwest_i2c2_groups), 372 FUNCTION("i2c3", southwest_i2c3_groups), 373 FUNCTION("i2c4", southwest_i2c4_groups), 374 FUNCTION("i2c5", southwest_i2c5_groups), 375 FUNCTION("i2c6", southwest_i2c6_groups), 376 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 377 FUNCTION("spi3", southwest_spi3_groups), 378 }; 379 380 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 381 GPIO_PINRANGE(0, 7), 382 GPIO_PINRANGE(15, 22), 383 GPIO_PINRANGE(30, 37), 384 GPIO_PINRANGE(45, 52), 385 GPIO_PINRANGE(60, 67), 386 GPIO_PINRANGE(75, 82), 387 GPIO_PINRANGE(90, 97), 388 }; 389 390 static const struct chv_community southwest_community = { 391 .uid = "1", 392 .pins = southwest_pins, 393 .npins = ARRAY_SIZE(southwest_pins), 394 .groups = southwest_groups, 395 .ngroups = ARRAY_SIZE(southwest_groups), 396 .functions = southwest_functions, 397 .nfunctions = ARRAY_SIZE(southwest_functions), 398 .gpio_ranges = southwest_gpio_ranges, 399 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 400 .ngpios = ARRAY_SIZE(southwest_pins), 401 }; 402 403 static const struct pinctrl_pin_desc north_pins[] = { 404 PINCTRL_PIN(0, "GPIO_DFX_0"), 405 PINCTRL_PIN(1, "GPIO_DFX_3"), 406 PINCTRL_PIN(2, "GPIO_DFX_7"), 407 PINCTRL_PIN(3, "GPIO_DFX_1"), 408 PINCTRL_PIN(4, "GPIO_DFX_5"), 409 PINCTRL_PIN(5, "GPIO_DFX_4"), 410 PINCTRL_PIN(6, "GPIO_DFX_8"), 411 PINCTRL_PIN(7, "GPIO_DFX_2"), 412 PINCTRL_PIN(8, "GPIO_DFX_6"), 413 414 PINCTRL_PIN(15, "GPIO_SUS0"), 415 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 416 PINCTRL_PIN(17, "GPIO_SUS3"), 417 PINCTRL_PIN(18, "GPIO_SUS7"), 418 PINCTRL_PIN(19, "GPIO_SUS1"), 419 PINCTRL_PIN(20, "GPIO_SUS5"), 420 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 421 PINCTRL_PIN(22, "GPIO_SUS4"), 422 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 423 PINCTRL_PIN(24, "GPIO_SUS2"), 424 PINCTRL_PIN(25, "GPIO_SUS6"), 425 PINCTRL_PIN(26, "CX_PREQ_B"), 426 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 427 428 PINCTRL_PIN(30, "TRST_B"), 429 PINCTRL_PIN(31, "TCK"), 430 PINCTRL_PIN(32, "PROCHOT_B"), 431 PINCTRL_PIN(33, "SVIDO_DATA"), 432 PINCTRL_PIN(34, "TMS"), 433 PINCTRL_PIN(35, "CX_PRDY_B_2"), 434 PINCTRL_PIN(36, "TDO_2"), 435 PINCTRL_PIN(37, "CX_PRDY_B"), 436 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 437 PINCTRL_PIN(39, "TDO"), 438 PINCTRL_PIN(40, "SVIDO_CLK"), 439 PINCTRL_PIN(41, "TDI"), 440 441 PINCTRL_PIN(45, "GP_CAMERASB_05"), 442 PINCTRL_PIN(46, "GP_CAMERASB_02"), 443 PINCTRL_PIN(47, "GP_CAMERASB_08"), 444 PINCTRL_PIN(48, "GP_CAMERASB_00"), 445 PINCTRL_PIN(49, "GP_CAMERASB_06"), 446 PINCTRL_PIN(50, "GP_CAMERASB_10"), 447 PINCTRL_PIN(51, "GP_CAMERASB_03"), 448 PINCTRL_PIN(52, "GP_CAMERASB_09"), 449 PINCTRL_PIN(53, "GP_CAMERASB_01"), 450 PINCTRL_PIN(54, "GP_CAMERASB_07"), 451 PINCTRL_PIN(55, "GP_CAMERASB_11"), 452 PINCTRL_PIN(56, "GP_CAMERASB_04"), 453 454 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 455 PINCTRL_PIN(61, "HV_DDI0_HPD"), 456 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 457 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 458 PINCTRL_PIN(64, "HV_DDI1_HPD"), 459 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 460 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 461 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 462 PINCTRL_PIN(68, "HV_DDI2_HPD"), 463 PINCTRL_PIN(69, "PANEL1_VDDEN"), 464 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 465 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 466 PINCTRL_PIN(72, "PANEL0_VDDEN"), 467 }; 468 469 static const struct chv_gpio_pinrange north_gpio_ranges[] = { 470 GPIO_PINRANGE(0, 8), 471 GPIO_PINRANGE(15, 27), 472 GPIO_PINRANGE(30, 41), 473 GPIO_PINRANGE(45, 56), 474 GPIO_PINRANGE(60, 72), 475 }; 476 477 static const struct chv_community north_community = { 478 .uid = "2", 479 .pins = north_pins, 480 .npins = ARRAY_SIZE(north_pins), 481 .gpio_ranges = north_gpio_ranges, 482 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 483 .ngpios = ARRAY_SIZE(north_pins), 484 }; 485 486 static const struct pinctrl_pin_desc east_pins[] = { 487 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 488 PINCTRL_PIN(1, "PMU_BATLOW_B"), 489 PINCTRL_PIN(2, "SUS_STAT_B"), 490 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 491 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 492 PINCTRL_PIN(5, "PMU_PLTRST_B"), 493 PINCTRL_PIN(6, "PMU_SUSCLK"), 494 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 495 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 496 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 497 PINCTRL_PIN(10, "PMU_WAKE_B"), 498 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 499 500 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 501 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 502 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 503 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 504 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 505 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 506 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 507 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 508 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 509 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 510 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 511 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 512 }; 513 514 static const struct chv_gpio_pinrange east_gpio_ranges[] = { 515 GPIO_PINRANGE(0, 11), 516 GPIO_PINRANGE(15, 26), 517 }; 518 519 static const struct chv_community east_community = { 520 .uid = "3", 521 .pins = east_pins, 522 .npins = ARRAY_SIZE(east_pins), 523 .gpio_ranges = east_gpio_ranges, 524 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 525 .ngpios = ARRAY_SIZE(east_pins), 526 }; 527 528 static const struct pinctrl_pin_desc southeast_pins[] = { 529 PINCTRL_PIN(0, "MF_PLT_CLK0"), 530 PINCTRL_PIN(1, "PWM1"), 531 PINCTRL_PIN(2, "MF_PLT_CLK1"), 532 PINCTRL_PIN(3, "MF_PLT_CLK4"), 533 PINCTRL_PIN(4, "MF_PLT_CLK3"), 534 PINCTRL_PIN(5, "PWM0"), 535 PINCTRL_PIN(6, "MF_PLT_CLK5"), 536 PINCTRL_PIN(7, "MF_PLT_CLK2"), 537 538 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 539 PINCTRL_PIN(16, "SDMMC1_CLK"), 540 PINCTRL_PIN(17, "SDMMC1_D0"), 541 PINCTRL_PIN(18, "SDMMC2_D1"), 542 PINCTRL_PIN(19, "SDMMC2_CLK"), 543 PINCTRL_PIN(20, "SDMMC1_D2"), 544 PINCTRL_PIN(21, "SDMMC2_D2"), 545 PINCTRL_PIN(22, "SDMMC2_CMD"), 546 PINCTRL_PIN(23, "SDMMC1_CMD"), 547 PINCTRL_PIN(24, "SDMMC1_D1"), 548 PINCTRL_PIN(25, "SDMMC2_D0"), 549 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 550 551 PINCTRL_PIN(30, "SDMMC3_D1"), 552 PINCTRL_PIN(31, "SDMMC3_CLK"), 553 PINCTRL_PIN(32, "SDMMC3_D3"), 554 PINCTRL_PIN(33, "SDMMC3_D2"), 555 PINCTRL_PIN(34, "SDMMC3_CMD"), 556 PINCTRL_PIN(35, "SDMMC3_D0"), 557 558 PINCTRL_PIN(45, "MF_LPC_AD2"), 559 PINCTRL_PIN(46, "LPC_CLKRUNB"), 560 PINCTRL_PIN(47, "MF_LPC_AD0"), 561 PINCTRL_PIN(48, "LPC_FRAMEB"), 562 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 563 PINCTRL_PIN(50, "MF_LPC_AD3"), 564 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 565 PINCTRL_PIN(52, "MF_LPC_AD1"), 566 567 PINCTRL_PIN(60, "SPI1_MISO"), 568 PINCTRL_PIN(61, "SPI1_CSO_B"), 569 PINCTRL_PIN(62, "SPI1_CLK"), 570 PINCTRL_PIN(63, "MMC1_D6"), 571 PINCTRL_PIN(64, "SPI1_MOSI"), 572 PINCTRL_PIN(65, "MMC1_D5"), 573 PINCTRL_PIN(66, "SPI1_CS1_B"), 574 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 575 PINCTRL_PIN(68, "MMC1_D7"), 576 PINCTRL_PIN(69, "MMC1_RCLK"), 577 578 PINCTRL_PIN(75, "USB_OC1_B"), 579 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 580 PINCTRL_PIN(77, "GPIO_ALERT"), 581 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 582 PINCTRL_PIN(79, "ILB_SERIRQ"), 583 PINCTRL_PIN(80, "USB_OC0_B"), 584 PINCTRL_PIN(81, "SDMMC3_CD_B"), 585 PINCTRL_PIN(82, "SPKR"), 586 PINCTRL_PIN(83, "SUSPWRDNACK"), 587 PINCTRL_PIN(84, "SPARE_PIN"), 588 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 589 }; 590 591 static const unsigned southeast_pwm0_pins[] = { 5 }; 592 static const unsigned southeast_pwm1_pins[] = { 1 }; 593 static const unsigned southeast_sdmmc1_pins[] = { 594 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 595 }; 596 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 597 static const unsigned southeast_sdmmc3_pins[] = { 598 30, 31, 32, 33, 34, 35, 78, 81, 85, 599 }; 600 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 601 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 602 603 static const struct chv_pingroup southeast_groups[] = { 604 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 605 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 606 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 607 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 608 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 609 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 610 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 611 }; 612 613 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 614 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 615 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 616 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 617 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 618 static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 619 static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 620 621 static const struct chv_function southeast_functions[] = { 622 FUNCTION("pwm0", southeast_pwm0_groups), 623 FUNCTION("pwm1", southeast_pwm1_groups), 624 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 625 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 626 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 627 FUNCTION("spi1", southeast_spi1_groups), 628 FUNCTION("spi2", southeast_spi2_groups), 629 }; 630 631 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 632 GPIO_PINRANGE(0, 7), 633 GPIO_PINRANGE(15, 26), 634 GPIO_PINRANGE(30, 35), 635 GPIO_PINRANGE(45, 52), 636 GPIO_PINRANGE(60, 69), 637 GPIO_PINRANGE(75, 85), 638 }; 639 640 static const struct chv_community southeast_community = { 641 .uid = "4", 642 .pins = southeast_pins, 643 .npins = ARRAY_SIZE(southeast_pins), 644 .groups = southeast_groups, 645 .ngroups = ARRAY_SIZE(southeast_groups), 646 .functions = southeast_functions, 647 .nfunctions = ARRAY_SIZE(southeast_functions), 648 .gpio_ranges = southeast_gpio_ranges, 649 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 650 .ngpios = ARRAY_SIZE(southeast_pins), 651 }; 652 653 static const struct chv_community *chv_communities[] = { 654 &southwest_community, 655 &north_community, 656 &east_community, 657 &southeast_community, 658 }; 659 660 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 661 unsigned reg) 662 { 663 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 664 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 665 666 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 667 GPIO_REGS_SIZE * pad_no; 668 669 return pctrl->regs + offset + reg; 670 } 671 672 static void chv_writel(u32 value, void __iomem *reg) 673 { 674 writel(value, reg); 675 /* simple readback to confirm the bus transferring done */ 676 readl(reg); 677 } 678 679 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 680 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 681 { 682 void __iomem *reg; 683 684 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 685 return readl(reg) & CHV_PADCTRL1_CFGLOCK; 686 } 687 688 static int chv_get_groups_count(struct pinctrl_dev *pctldev) 689 { 690 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 691 692 return pctrl->community->ngroups; 693 } 694 695 static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 696 unsigned group) 697 { 698 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 699 700 return pctrl->community->groups[group].name; 701 } 702 703 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 704 const unsigned **pins, unsigned *npins) 705 { 706 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 707 708 *pins = pctrl->community->groups[group].pins; 709 *npins = pctrl->community->groups[group].npins; 710 return 0; 711 } 712 713 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 714 unsigned offset) 715 { 716 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 717 unsigned long flags; 718 u32 ctrl0, ctrl1; 719 bool locked; 720 721 raw_spin_lock_irqsave(&pctrl->lock, flags); 722 723 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 724 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 725 locked = chv_pad_locked(pctrl, offset); 726 727 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 728 729 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 730 seq_puts(s, "GPIO "); 731 } else { 732 u32 mode; 733 734 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 735 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 736 737 seq_printf(s, "mode %d ", mode); 738 } 739 740 seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1); 741 742 if (locked) 743 seq_puts(s, " [LOCKED]"); 744 } 745 746 static const struct pinctrl_ops chv_pinctrl_ops = { 747 .get_groups_count = chv_get_groups_count, 748 .get_group_name = chv_get_group_name, 749 .get_group_pins = chv_get_group_pins, 750 .pin_dbg_show = chv_pin_dbg_show, 751 }; 752 753 static int chv_get_functions_count(struct pinctrl_dev *pctldev) 754 { 755 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 756 757 return pctrl->community->nfunctions; 758 } 759 760 static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 761 unsigned function) 762 { 763 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 764 765 return pctrl->community->functions[function].name; 766 } 767 768 static int chv_get_function_groups(struct pinctrl_dev *pctldev, 769 unsigned function, 770 const char * const **groups, 771 unsigned * const ngroups) 772 { 773 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 774 775 *groups = pctrl->community->functions[function].groups; 776 *ngroups = pctrl->community->functions[function].ngroups; 777 return 0; 778 } 779 780 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 781 unsigned group) 782 { 783 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 784 const struct chv_pingroup *grp; 785 unsigned long flags; 786 int i; 787 788 grp = &pctrl->community->groups[group]; 789 790 raw_spin_lock_irqsave(&pctrl->lock, flags); 791 792 /* Check first that the pad is not locked */ 793 for (i = 0; i < grp->npins; i++) { 794 if (chv_pad_locked(pctrl, grp->pins[i])) { 795 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 796 grp->pins[i]); 797 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 798 return -EBUSY; 799 } 800 } 801 802 for (i = 0; i < grp->npins; i++) { 803 const struct chv_alternate_function *altfunc = &grp->altfunc; 804 int pin = grp->pins[i]; 805 void __iomem *reg; 806 u32 value; 807 808 /* Check if there is pin-specific config */ 809 if (grp->overrides) { 810 int j; 811 812 for (j = 0; j < grp->noverrides; j++) { 813 if (grp->overrides[j].pin == pin) { 814 altfunc = &grp->overrides[j]; 815 break; 816 } 817 } 818 } 819 820 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 821 value = readl(reg); 822 /* Disable GPIO mode */ 823 value &= ~CHV_PADCTRL0_GPIOEN; 824 /* Set to desired mode */ 825 value &= ~CHV_PADCTRL0_PMODE_MASK; 826 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 827 chv_writel(value, reg); 828 829 /* Update for invert_oe */ 830 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 831 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 832 if (altfunc->invert_oe) 833 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 834 chv_writel(value, reg); 835 836 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 837 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 838 } 839 840 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 841 842 return 0; 843 } 844 845 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 846 struct pinctrl_gpio_range *range, 847 unsigned offset) 848 { 849 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 850 unsigned long flags; 851 void __iomem *reg; 852 u32 value; 853 854 raw_spin_lock_irqsave(&pctrl->lock, flags); 855 856 if (chv_pad_locked(pctrl, offset)) { 857 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 858 if (!(value & CHV_PADCTRL0_GPIOEN)) { 859 /* Locked so cannot enable */ 860 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 861 return -EBUSY; 862 } 863 } else { 864 int i; 865 866 /* Reset the interrupt mapping */ 867 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 868 if (pctrl->intr_lines[i] == offset) { 869 pctrl->intr_lines[i] = 0; 870 break; 871 } 872 } 873 874 /* Disable interrupt generation */ 875 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 876 value = readl(reg); 877 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 878 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 879 chv_writel(value, reg); 880 881 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 882 value = readl(reg); 883 884 /* 885 * If the pin is in HiZ mode (both TX and RX buffers are 886 * disabled) we turn it to be input now. 887 */ 888 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 889 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 890 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 891 value |= CHV_PADCTRL0_GPIOCFG_GPI << 892 CHV_PADCTRL0_GPIOCFG_SHIFT; 893 } 894 895 /* Switch to a GPIO mode */ 896 value |= CHV_PADCTRL0_GPIOEN; 897 chv_writel(value, reg); 898 } 899 900 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 901 902 return 0; 903 } 904 905 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 906 struct pinctrl_gpio_range *range, 907 unsigned offset) 908 { 909 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 910 unsigned long flags; 911 void __iomem *reg; 912 u32 value; 913 914 raw_spin_lock_irqsave(&pctrl->lock, flags); 915 916 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 917 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 918 chv_writel(value, reg); 919 920 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 921 } 922 923 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 924 struct pinctrl_gpio_range *range, 925 unsigned offset, bool input) 926 { 927 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 928 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 929 unsigned long flags; 930 u32 ctrl0; 931 932 raw_spin_lock_irqsave(&pctrl->lock, flags); 933 934 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 935 if (input) 936 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 937 else 938 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 939 chv_writel(ctrl0, reg); 940 941 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 942 943 return 0; 944 } 945 946 static const struct pinmux_ops chv_pinmux_ops = { 947 .get_functions_count = chv_get_functions_count, 948 .get_function_name = chv_get_function_name, 949 .get_function_groups = chv_get_function_groups, 950 .set_mux = chv_pinmux_set_mux, 951 .gpio_request_enable = chv_gpio_request_enable, 952 .gpio_disable_free = chv_gpio_disable_free, 953 .gpio_set_direction = chv_gpio_set_direction, 954 }; 955 956 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 957 unsigned long *config) 958 { 959 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 960 enum pin_config_param param = pinconf_to_config_param(*config); 961 unsigned long flags; 962 u32 ctrl0, ctrl1; 963 u16 arg = 0; 964 u32 term; 965 966 raw_spin_lock_irqsave(&pctrl->lock, flags); 967 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 968 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 969 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 970 971 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 972 973 switch (param) { 974 case PIN_CONFIG_BIAS_DISABLE: 975 if (term) 976 return -EINVAL; 977 break; 978 979 case PIN_CONFIG_BIAS_PULL_UP: 980 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 981 return -EINVAL; 982 983 switch (term) { 984 case CHV_PADCTRL0_TERM_20K: 985 arg = 20000; 986 break; 987 case CHV_PADCTRL0_TERM_5K: 988 arg = 5000; 989 break; 990 case CHV_PADCTRL0_TERM_1K: 991 arg = 1000; 992 break; 993 } 994 995 break; 996 997 case PIN_CONFIG_BIAS_PULL_DOWN: 998 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 999 return -EINVAL; 1000 1001 switch (term) { 1002 case CHV_PADCTRL0_TERM_20K: 1003 arg = 20000; 1004 break; 1005 case CHV_PADCTRL0_TERM_5K: 1006 arg = 5000; 1007 break; 1008 } 1009 1010 break; 1011 1012 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1013 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 1014 return -EINVAL; 1015 break; 1016 1017 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 1018 u32 cfg; 1019 1020 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1021 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1022 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 1023 return -EINVAL; 1024 1025 break; 1026 } 1027 1028 default: 1029 return -ENOTSUPP; 1030 } 1031 1032 *config = pinconf_to_config_packed(param, arg); 1033 return 0; 1034 } 1035 1036 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 1037 enum pin_config_param param, u16 arg) 1038 { 1039 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1040 unsigned long flags; 1041 u32 ctrl0, pull; 1042 1043 raw_spin_lock_irqsave(&pctrl->lock, flags); 1044 ctrl0 = readl(reg); 1045 1046 switch (param) { 1047 case PIN_CONFIG_BIAS_DISABLE: 1048 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1049 break; 1050 1051 case PIN_CONFIG_BIAS_PULL_UP: 1052 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1053 1054 switch (arg) { 1055 case 1000: 1056 /* For 1k there is only pull up */ 1057 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 1058 break; 1059 case 5000: 1060 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1061 break; 1062 case 20000: 1063 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1064 break; 1065 default: 1066 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1067 return -EINVAL; 1068 } 1069 1070 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 1071 break; 1072 1073 case PIN_CONFIG_BIAS_PULL_DOWN: 1074 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 1075 1076 switch (arg) { 1077 case 5000: 1078 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 1079 break; 1080 case 20000: 1081 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1082 break; 1083 default: 1084 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1085 return -EINVAL; 1086 } 1087 1088 ctrl0 |= pull; 1089 break; 1090 1091 default: 1092 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1093 return -EINVAL; 1094 } 1095 1096 chv_writel(ctrl0, reg); 1097 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1098 1099 return 0; 1100 } 1101 1102 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 1103 unsigned long *configs, unsigned nconfigs) 1104 { 1105 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1106 enum pin_config_param param; 1107 int i, ret; 1108 u16 arg; 1109 1110 if (chv_pad_locked(pctrl, pin)) 1111 return -EBUSY; 1112 1113 for (i = 0; i < nconfigs; i++) { 1114 param = pinconf_to_config_param(configs[i]); 1115 arg = pinconf_to_config_argument(configs[i]); 1116 1117 switch (param) { 1118 case PIN_CONFIG_BIAS_DISABLE: 1119 case PIN_CONFIG_BIAS_PULL_UP: 1120 case PIN_CONFIG_BIAS_PULL_DOWN: 1121 ret = chv_config_set_pull(pctrl, pin, param, arg); 1122 if (ret) 1123 return ret; 1124 break; 1125 1126 default: 1127 return -ENOTSUPP; 1128 } 1129 1130 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 1131 param, arg); 1132 } 1133 1134 return 0; 1135 } 1136 1137 static const struct pinconf_ops chv_pinconf_ops = { 1138 .is_generic = true, 1139 .pin_config_set = chv_config_set, 1140 .pin_config_get = chv_config_get, 1141 }; 1142 1143 static struct pinctrl_desc chv_pinctrl_desc = { 1144 .pctlops = &chv_pinctrl_ops, 1145 .pmxops = &chv_pinmux_ops, 1146 .confops = &chv_pinconf_ops, 1147 .owner = THIS_MODULE, 1148 }; 1149 1150 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, 1151 unsigned offset) 1152 { 1153 return pctrl->community->pins[offset].number; 1154 } 1155 1156 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 1157 { 1158 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1159 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1160 unsigned long flags; 1161 u32 ctrl0, cfg; 1162 1163 raw_spin_lock_irqsave(&pctrl->lock, flags); 1164 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1165 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1166 1167 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1168 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1169 1170 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1171 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1172 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1173 } 1174 1175 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1176 { 1177 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1178 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 1179 unsigned long flags; 1180 void __iomem *reg; 1181 u32 ctrl0; 1182 1183 raw_spin_lock_irqsave(&pctrl->lock, flags); 1184 1185 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1186 ctrl0 = readl(reg); 1187 1188 if (value) 1189 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1190 else 1191 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1192 1193 chv_writel(ctrl0, reg); 1194 1195 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1196 } 1197 1198 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1199 { 1200 struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 1201 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 1202 u32 ctrl0, direction; 1203 unsigned long flags; 1204 1205 raw_spin_lock_irqsave(&pctrl->lock, flags); 1206 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1207 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1208 1209 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1210 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1211 1212 return direction != CHV_PADCTRL0_GPIOCFG_GPO; 1213 } 1214 1215 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1216 { 1217 return pinctrl_gpio_direction_input(chip->base + offset); 1218 } 1219 1220 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1221 int value) 1222 { 1223 chv_gpio_set(chip, offset, value); 1224 return pinctrl_gpio_direction_output(chip->base + offset); 1225 } 1226 1227 static const struct gpio_chip chv_gpio_chip = { 1228 .owner = THIS_MODULE, 1229 .request = gpiochip_generic_request, 1230 .free = gpiochip_generic_free, 1231 .get_direction = chv_gpio_get_direction, 1232 .direction_input = chv_gpio_direction_input, 1233 .direction_output = chv_gpio_direction_output, 1234 .get = chv_gpio_get, 1235 .set = chv_gpio_set, 1236 }; 1237 1238 static void chv_gpio_irq_ack(struct irq_data *d) 1239 { 1240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1241 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1242 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1243 u32 intr_line; 1244 1245 raw_spin_lock(&pctrl->lock); 1246 1247 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1248 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1249 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1250 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 1251 1252 raw_spin_unlock(&pctrl->lock); 1253 } 1254 1255 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1256 { 1257 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1258 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1259 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1260 u32 value, intr_line; 1261 unsigned long flags; 1262 1263 raw_spin_lock_irqsave(&pctrl->lock, flags); 1264 1265 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1266 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1267 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1268 1269 value = readl(pctrl->regs + CHV_INTMASK); 1270 if (mask) 1271 value &= ~BIT(intr_line); 1272 else 1273 value |= BIT(intr_line); 1274 chv_writel(value, pctrl->regs + CHV_INTMASK); 1275 1276 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1277 } 1278 1279 static void chv_gpio_irq_mask(struct irq_data *d) 1280 { 1281 chv_gpio_irq_mask_unmask(d, true); 1282 } 1283 1284 static void chv_gpio_irq_unmask(struct irq_data *d) 1285 { 1286 chv_gpio_irq_mask_unmask(d, false); 1287 } 1288 1289 static unsigned chv_gpio_irq_startup(struct irq_data *d) 1290 { 1291 /* 1292 * Check if the interrupt has been requested with 0 as triggering 1293 * type. In that case it is assumed that the current values 1294 * programmed to the hardware are used (e.g BIOS configured 1295 * defaults). 1296 * 1297 * In that case ->irq_set_type() will never be called so we need to 1298 * read back the values from hardware now, set correct flow handler 1299 * and update mappings before the interrupt is being used. 1300 */ 1301 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1302 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1303 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1304 unsigned offset = irqd_to_hwirq(d); 1305 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1306 irq_flow_handler_t handler; 1307 unsigned long flags; 1308 u32 intsel, value; 1309 1310 raw_spin_lock_irqsave(&pctrl->lock, flags); 1311 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1312 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1313 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1314 1315 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1316 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1317 handler = handle_level_irq; 1318 else 1319 handler = handle_edge_irq; 1320 1321 if (!pctrl->intr_lines[intsel]) { 1322 irq_set_handler_locked(d, handler); 1323 pctrl->intr_lines[intsel] = offset; 1324 } 1325 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1326 } 1327 1328 chv_gpio_irq_unmask(d); 1329 return 0; 1330 } 1331 1332 static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 1333 { 1334 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1335 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1336 unsigned offset = irqd_to_hwirq(d); 1337 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1338 unsigned long flags; 1339 u32 value; 1340 1341 raw_spin_lock_irqsave(&pctrl->lock, flags); 1342 1343 /* 1344 * Pins which can be used as shared interrupt are configured in 1345 * BIOS. Driver trusts BIOS configurations and assigns different 1346 * handler according to the irq type. 1347 * 1348 * Driver needs to save the mapping between each pin and 1349 * its interrupt line. 1350 * 1. If the pin cfg is locked in BIOS: 1351 * Trust BIOS has programmed IntWakeCfg bits correctly, 1352 * driver just needs to save the mapping. 1353 * 2. If the pin cfg is not locked in BIOS: 1354 * Driver programs the IntWakeCfg bits and save the mapping. 1355 */ 1356 if (!chv_pad_locked(pctrl, pin)) { 1357 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1358 1359 value = readl(reg); 1360 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1361 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1362 1363 if (type & IRQ_TYPE_EDGE_BOTH) { 1364 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1365 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1366 else if (type & IRQ_TYPE_EDGE_RISING) 1367 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1368 else if (type & IRQ_TYPE_EDGE_FALLING) 1369 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1370 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1371 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1372 if (type & IRQ_TYPE_LEVEL_LOW) 1373 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1374 } 1375 1376 chv_writel(value, reg); 1377 } 1378 1379 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1380 value &= CHV_PADCTRL0_INTSEL_MASK; 1381 value >>= CHV_PADCTRL0_INTSEL_SHIFT; 1382 1383 pctrl->intr_lines[value] = offset; 1384 1385 if (type & IRQ_TYPE_EDGE_BOTH) 1386 irq_set_handler_locked(d, handle_edge_irq); 1387 else if (type & IRQ_TYPE_LEVEL_MASK) 1388 irq_set_handler_locked(d, handle_level_irq); 1389 1390 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1391 1392 return 0; 1393 } 1394 1395 static struct irq_chip chv_gpio_irqchip = { 1396 .name = "chv-gpio", 1397 .irq_startup = chv_gpio_irq_startup, 1398 .irq_ack = chv_gpio_irq_ack, 1399 .irq_mask = chv_gpio_irq_mask, 1400 .irq_unmask = chv_gpio_irq_unmask, 1401 .irq_set_type = chv_gpio_irq_type, 1402 .flags = IRQCHIP_SKIP_SET_WAKE, 1403 }; 1404 1405 static void chv_gpio_irq_handler(struct irq_desc *desc) 1406 { 1407 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1408 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1409 struct irq_chip *chip = irq_desc_get_chip(desc); 1410 unsigned long pending; 1411 u32 intr_line; 1412 1413 chained_irq_enter(chip, desc); 1414 1415 pending = readl(pctrl->regs + CHV_INTSTAT); 1416 for_each_set_bit(intr_line, &pending, 16) { 1417 unsigned irq, offset; 1418 1419 offset = pctrl->intr_lines[intr_line]; 1420 irq = irq_find_mapping(gc->irqdomain, offset); 1421 generic_handle_irq(irq); 1422 } 1423 1424 chained_irq_exit(chip, desc); 1425 } 1426 1427 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 1428 { 1429 const struct chv_gpio_pinrange *range; 1430 struct gpio_chip *chip = &pctrl->chip; 1431 int ret, i, offset; 1432 1433 *chip = chv_gpio_chip; 1434 1435 chip->ngpio = pctrl->community->ngpios; 1436 chip->label = dev_name(pctrl->dev); 1437 chip->parent = pctrl->dev; 1438 chip->base = -1; 1439 1440 ret = gpiochip_add_data(chip, pctrl); 1441 if (ret) { 1442 dev_err(pctrl->dev, "Failed to register gpiochip\n"); 1443 return ret; 1444 } 1445 1446 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { 1447 range = &pctrl->community->gpio_ranges[i]; 1448 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, 1449 range->base, range->npins); 1450 if (ret) { 1451 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1452 goto fail; 1453 } 1454 1455 offset += range->npins; 1456 } 1457 1458 /* Mask and clear all interrupts */ 1459 chv_writel(0, pctrl->regs + CHV_INTMASK); 1460 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1461 1462 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1463 handle_simple_irq, IRQ_TYPE_NONE); 1464 if (ret) { 1465 dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1466 goto fail; 1467 } 1468 1469 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 1470 chv_gpio_irq_handler); 1471 return 0; 1472 1473 fail: 1474 gpiochip_remove(chip); 1475 1476 return ret; 1477 } 1478 1479 static int chv_pinctrl_probe(struct platform_device *pdev) 1480 { 1481 struct chv_pinctrl *pctrl; 1482 struct acpi_device *adev; 1483 struct resource *res; 1484 int ret, irq, i; 1485 1486 adev = ACPI_COMPANION(&pdev->dev); 1487 if (!adev) 1488 return -ENODEV; 1489 1490 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1491 if (!pctrl) 1492 return -ENOMEM; 1493 1494 for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 1495 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 1496 pctrl->community = chv_communities[i]; 1497 break; 1498 } 1499 if (i == ARRAY_SIZE(chv_communities)) 1500 return -ENODEV; 1501 1502 raw_spin_lock_init(&pctrl->lock); 1503 pctrl->dev = &pdev->dev; 1504 1505 #ifdef CONFIG_PM_SLEEP 1506 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 1507 pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 1508 GFP_KERNEL); 1509 if (!pctrl->saved_pin_context) 1510 return -ENOMEM; 1511 #endif 1512 1513 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1514 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 1515 if (IS_ERR(pctrl->regs)) 1516 return PTR_ERR(pctrl->regs); 1517 1518 irq = platform_get_irq(pdev, 0); 1519 if (irq < 0) { 1520 dev_err(&pdev->dev, "failed to get interrupt number\n"); 1521 return irq; 1522 } 1523 1524 pctrl->pctldesc = chv_pinctrl_desc; 1525 pctrl->pctldesc.name = dev_name(&pdev->dev); 1526 pctrl->pctldesc.pins = pctrl->community->pins; 1527 pctrl->pctldesc.npins = pctrl->community->npins; 1528 1529 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 1530 pctrl); 1531 if (IS_ERR(pctrl->pctldev)) { 1532 dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1533 return PTR_ERR(pctrl->pctldev); 1534 } 1535 1536 ret = chv_gpio_probe(pctrl, irq); 1537 if (ret) 1538 return ret; 1539 1540 platform_set_drvdata(pdev, pctrl); 1541 1542 return 0; 1543 } 1544 1545 static int chv_pinctrl_remove(struct platform_device *pdev) 1546 { 1547 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1548 1549 gpiochip_remove(&pctrl->chip); 1550 1551 return 0; 1552 } 1553 1554 #ifdef CONFIG_PM_SLEEP 1555 static int chv_pinctrl_suspend(struct device *dev) 1556 { 1557 struct platform_device *pdev = to_platform_device(dev); 1558 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1559 int i; 1560 1561 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 1562 1563 for (i = 0; i < pctrl->community->npins; i++) { 1564 const struct pinctrl_pin_desc *desc; 1565 struct chv_pin_context *ctx; 1566 void __iomem *reg; 1567 1568 desc = &pctrl->community->pins[i]; 1569 if (chv_pad_locked(pctrl, desc->number)) 1570 continue; 1571 1572 ctx = &pctrl->saved_pin_context[i]; 1573 1574 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1575 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1576 1577 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1578 ctx->padctrl1 = readl(reg); 1579 } 1580 1581 return 0; 1582 } 1583 1584 static int chv_pinctrl_resume(struct device *dev) 1585 { 1586 struct platform_device *pdev = to_platform_device(dev); 1587 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1588 int i; 1589 1590 /* 1591 * Mask all interrupts before restoring per-pin configuration 1592 * registers because we don't know in which state BIOS left them 1593 * upon exiting suspend. 1594 */ 1595 chv_writel(0, pctrl->regs + CHV_INTMASK); 1596 1597 for (i = 0; i < pctrl->community->npins; i++) { 1598 const struct pinctrl_pin_desc *desc; 1599 const struct chv_pin_context *ctx; 1600 void __iomem *reg; 1601 u32 val; 1602 1603 desc = &pctrl->community->pins[i]; 1604 if (chv_pad_locked(pctrl, desc->number)) 1605 continue; 1606 1607 ctx = &pctrl->saved_pin_context[i]; 1608 1609 /* Only restore if our saved state differs from the current */ 1610 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 1611 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 1612 if (ctx->padctrl0 != val) { 1613 chv_writel(ctx->padctrl0, reg); 1614 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 1615 desc->number, readl(reg)); 1616 } 1617 1618 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 1619 val = readl(reg); 1620 if (ctx->padctrl1 != val) { 1621 chv_writel(ctx->padctrl1, reg); 1622 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 1623 desc->number, readl(reg)); 1624 } 1625 } 1626 1627 /* 1628 * Now that all pins are restored to known state, we can restore 1629 * the interrupt mask register as well. 1630 */ 1631 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 1632 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 1633 1634 return 0; 1635 } 1636 #endif 1637 1638 static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1639 SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) 1640 }; 1641 1642 static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1643 { "INT33FF" }, 1644 { } 1645 }; 1646 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1647 1648 static struct platform_driver chv_pinctrl_driver = { 1649 .probe = chv_pinctrl_probe, 1650 .remove = chv_pinctrl_remove, 1651 .driver = { 1652 .name = "cherryview-pinctrl", 1653 .pm = &chv_pinctrl_pm_ops, 1654 .acpi_match_table = chv_pinctrl_acpi_match, 1655 }, 1656 }; 1657 1658 static int __init chv_pinctrl_init(void) 1659 { 1660 return platform_driver_register(&chv_pinctrl_driver); 1661 } 1662 subsys_initcall(chv_pinctrl_init); 1663 1664 static void __exit chv_pinctrl_exit(void) 1665 { 1666 platform_driver_unregister(&chv_pinctrl_driver); 1667 } 1668 module_exit(chv_pinctrl_exit); 1669 1670 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1671 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1672 MODULE_LICENSE("GPL v2"); 1673