16e08d6bbSMika Westerberg /* 26e08d6bbSMika Westerberg * Cherryview/Braswell pinctrl driver 36e08d6bbSMika Westerberg * 46e08d6bbSMika Westerberg * Copyright (C) 2014, Intel Corporation 56e08d6bbSMika Westerberg * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 66e08d6bbSMika Westerberg * 76e08d6bbSMika Westerberg * This driver is based on the original Cherryview GPIO driver by 86e08d6bbSMika Westerberg * Ning Li <ning.li@intel.com> 96e08d6bbSMika Westerberg * Alan Cox <alan@linux.intel.com> 106e08d6bbSMika Westerberg * 116e08d6bbSMika Westerberg * This program is free software; you can redistribute it and/or modify 126e08d6bbSMika Westerberg * it under the terms of the GNU General Public License version 2 as 136e08d6bbSMika Westerberg * published by the Free Software Foundation. 146e08d6bbSMika Westerberg */ 156e08d6bbSMika Westerberg 166e08d6bbSMika Westerberg #include <linux/kernel.h> 176e08d6bbSMika Westerberg #include <linux/module.h> 186e08d6bbSMika Westerberg #include <linux/init.h> 196e08d6bbSMika Westerberg #include <linux/types.h> 206e08d6bbSMika Westerberg #include <linux/gpio.h> 216e08d6bbSMika Westerberg #include <linux/gpio/driver.h> 226e08d6bbSMika Westerberg #include <linux/acpi.h> 236e08d6bbSMika Westerberg #include <linux/pinctrl/pinctrl.h> 246e08d6bbSMika Westerberg #include <linux/pinctrl/pinmux.h> 256e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf.h> 266e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf-generic.h> 276e08d6bbSMika Westerberg #include <linux/platform_device.h> 286e08d6bbSMika Westerberg 296e08d6bbSMika Westerberg #define CHV_INTSTAT 0x300 306e08d6bbSMika Westerberg #define CHV_INTMASK 0x380 316e08d6bbSMika Westerberg 326e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_OFF 0x4400 336e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_SIZE 0x400 346e08d6bbSMika Westerberg #define MAX_FAMILY_PAD_GPIO_NO 15 356e08d6bbSMika Westerberg #define GPIO_REGS_SIZE 8 366e08d6bbSMika Westerberg 376e08d6bbSMika Westerberg #define CHV_PADCTRL0 0x000 386e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_SHIFT 28 396e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 406e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_UP BIT(23) 416e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_SHIFT 20 426e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 436e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_20K 1 446e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_5K 2 456e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_1K 4 466e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_SHIFT 16 476e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 486e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOEN BIT(15) 496e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 506e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 516e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPIO 0 526e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPO 1 536e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPI 2 546e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_HIZ 3 556e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 566e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 576e08d6bbSMika Westerberg 586e08d6bbSMika Westerberg #define CHV_PADCTRL1 0x004 596e08d6bbSMika Westerberg #define CHV_PADCTRL1_CFGLOCK BIT(31) 606e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_SHIFT 4 616e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 626e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 636e08d6bbSMika Westerberg #define CHV_PADCTRL1_ODEN BIT(3) 646e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 656e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_MASK 7 666e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 676e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_RISING 2 686e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 696e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 706e08d6bbSMika Westerberg 716e08d6bbSMika Westerberg /** 726e08d6bbSMika Westerberg * struct chv_alternate_function - A per group or per pin alternate function 736e08d6bbSMika Westerberg * @pin: Pin number (only used in per pin configs) 746e08d6bbSMika Westerberg * @mode: Mode the pin should be set in 756e08d6bbSMika Westerberg * @invert_oe: Invert OE for this pin 766e08d6bbSMika Westerberg */ 776e08d6bbSMika Westerberg struct chv_alternate_function { 786e08d6bbSMika Westerberg unsigned pin; 796e08d6bbSMika Westerberg u8 mode; 806e08d6bbSMika Westerberg bool invert_oe; 816e08d6bbSMika Westerberg }; 826e08d6bbSMika Westerberg 836e08d6bbSMika Westerberg /** 846e08d6bbSMika Westerberg * struct chv_pincgroup - describes a CHV pin group 856e08d6bbSMika Westerberg * @name: Name of the group 866e08d6bbSMika Westerberg * @pins: An array of pins in this group 876e08d6bbSMika Westerberg * @npins: Number of pins in this group 886e08d6bbSMika Westerberg * @altfunc: Alternate function applied to all pins in this group 896e08d6bbSMika Westerberg * @overrides: Alternate function override per pin or %NULL if not used 906e08d6bbSMika Westerberg * @noverrides: Number of per pin alternate function overrides if 916e08d6bbSMika Westerberg * @overrides != NULL. 926e08d6bbSMika Westerberg */ 936e08d6bbSMika Westerberg struct chv_pingroup { 946e08d6bbSMika Westerberg const char *name; 956e08d6bbSMika Westerberg const unsigned *pins; 966e08d6bbSMika Westerberg size_t npins; 976e08d6bbSMika Westerberg struct chv_alternate_function altfunc; 986e08d6bbSMika Westerberg const struct chv_alternate_function *overrides; 996e08d6bbSMika Westerberg size_t noverrides; 1006e08d6bbSMika Westerberg }; 1016e08d6bbSMika Westerberg 1026e08d6bbSMika Westerberg /** 1036e08d6bbSMika Westerberg * struct chv_function - A CHV pinmux function 1046e08d6bbSMika Westerberg * @name: Name of the function 1056e08d6bbSMika Westerberg * @groups: An array of groups for this function 1066e08d6bbSMika Westerberg * @ngroups: Number of groups in @groups 1076e08d6bbSMika Westerberg */ 1086e08d6bbSMika Westerberg struct chv_function { 1096e08d6bbSMika Westerberg const char *name; 1106e08d6bbSMika Westerberg const char * const *groups; 1116e08d6bbSMika Westerberg size_t ngroups; 1126e08d6bbSMika Westerberg }; 1136e08d6bbSMika Westerberg 1146e08d6bbSMika Westerberg /** 1156e08d6bbSMika Westerberg * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 1166e08d6bbSMika Westerberg * @base: Start pin number 1176e08d6bbSMika Westerberg * @npins: Number of pins in this range 1186e08d6bbSMika Westerberg */ 1196e08d6bbSMika Westerberg struct chv_gpio_pinrange { 1206e08d6bbSMika Westerberg unsigned base; 1216e08d6bbSMika Westerberg unsigned npins; 1226e08d6bbSMika Westerberg }; 1236e08d6bbSMika Westerberg 1246e08d6bbSMika Westerberg /** 1256e08d6bbSMika Westerberg * struct chv_community - A community specific configuration 1266e08d6bbSMika Westerberg * @uid: ACPI _UID used to match the community 1276e08d6bbSMika Westerberg * @pins: All pins in this community 1286e08d6bbSMika Westerberg * @npins: Number of pins 1296e08d6bbSMika Westerberg * @groups: All groups in this community 1306e08d6bbSMika Westerberg * @ngroups: Number of groups 1316e08d6bbSMika Westerberg * @functions: All functions in this community 1326e08d6bbSMika Westerberg * @nfunctions: Number of functions 1336e08d6bbSMika Westerberg * @ngpios: Number of GPIOs in this community 1346e08d6bbSMika Westerberg * @gpio_ranges: An array of GPIO ranges in this community 1356e08d6bbSMika Westerberg * @ngpio_ranges: Number of GPIO ranges 1366e08d6bbSMika Westerberg * @ngpios: Total number of GPIOs in this community 1376e08d6bbSMika Westerberg */ 1386e08d6bbSMika Westerberg struct chv_community { 1396e08d6bbSMika Westerberg const char *uid; 1406e08d6bbSMika Westerberg const struct pinctrl_pin_desc *pins; 1416e08d6bbSMika Westerberg size_t npins; 1426e08d6bbSMika Westerberg const struct chv_pingroup *groups; 1436e08d6bbSMika Westerberg size_t ngroups; 1446e08d6bbSMika Westerberg const struct chv_function *functions; 1456e08d6bbSMika Westerberg size_t nfunctions; 1466e08d6bbSMika Westerberg const struct chv_gpio_pinrange *gpio_ranges; 1476e08d6bbSMika Westerberg size_t ngpio_ranges; 1486e08d6bbSMika Westerberg size_t ngpios; 1496e08d6bbSMika Westerberg }; 1506e08d6bbSMika Westerberg 1519eb457b5SMika Westerberg struct chv_pin_context { 1529eb457b5SMika Westerberg u32 padctrl0; 1539eb457b5SMika Westerberg u32 padctrl1; 1549eb457b5SMika Westerberg }; 1559eb457b5SMika Westerberg 1566e08d6bbSMika Westerberg /** 1576e08d6bbSMika Westerberg * struct chv_pinctrl - CHV pinctrl private structure 1586e08d6bbSMika Westerberg * @dev: Pointer to the parent device 1596e08d6bbSMika Westerberg * @pctldesc: Pin controller description 1606e08d6bbSMika Westerberg * @pctldev: Pointer to the pin controller device 1616e08d6bbSMika Westerberg * @chip: GPIO chip in this pin controller 1626e08d6bbSMika Westerberg * @regs: MMIO registers 1636e08d6bbSMika Westerberg * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 1646e08d6bbSMika Westerberg * offset (in GPIO number space) 1656e08d6bbSMika Westerberg * @community: Community this pinctrl instance represents 1666e08d6bbSMika Westerberg * 1676e08d6bbSMika Westerberg * The first group in @groups is expected to contain all pins that can be 1686e08d6bbSMika Westerberg * used as GPIOs. 1696e08d6bbSMika Westerberg */ 1706e08d6bbSMika Westerberg struct chv_pinctrl { 1716e08d6bbSMika Westerberg struct device *dev; 1726e08d6bbSMika Westerberg struct pinctrl_desc pctldesc; 1736e08d6bbSMika Westerberg struct pinctrl_dev *pctldev; 1746e08d6bbSMika Westerberg struct gpio_chip chip; 1756e08d6bbSMika Westerberg void __iomem *regs; 1766e08d6bbSMika Westerberg unsigned intr_lines[16]; 1776e08d6bbSMika Westerberg const struct chv_community *community; 1789eb457b5SMika Westerberg u32 saved_intmask; 1799eb457b5SMika Westerberg struct chv_pin_context *saved_pin_context; 1806e08d6bbSMika Westerberg }; 1816e08d6bbSMika Westerberg 1826e08d6bbSMika Westerberg #define ALTERNATE_FUNCTION(p, m, i) \ 1836e08d6bbSMika Westerberg { \ 1846e08d6bbSMika Westerberg .pin = (p), \ 1856e08d6bbSMika Westerberg .mode = (m), \ 1866e08d6bbSMika Westerberg .invert_oe = (i), \ 1876e08d6bbSMika Westerberg } 1886e08d6bbSMika Westerberg 1896e08d6bbSMika Westerberg #define PIN_GROUP(n, p, m, i) \ 1906e08d6bbSMika Westerberg { \ 1916e08d6bbSMika Westerberg .name = (n), \ 1926e08d6bbSMika Westerberg .pins = (p), \ 1936e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 1946e08d6bbSMika Westerberg .altfunc.mode = (m), \ 1956e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 1966e08d6bbSMika Westerberg } 1976e08d6bbSMika Westerberg 1986e08d6bbSMika Westerberg #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 1996e08d6bbSMika Westerberg { \ 2006e08d6bbSMika Westerberg .name = (n), \ 2016e08d6bbSMika Westerberg .pins = (p), \ 2026e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 2036e08d6bbSMika Westerberg .altfunc.mode = (m), \ 2046e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 2056e08d6bbSMika Westerberg .overrides = (o), \ 2066e08d6bbSMika Westerberg .noverrides = ARRAY_SIZE((o)), \ 2076e08d6bbSMika Westerberg } 2086e08d6bbSMika Westerberg 2096e08d6bbSMika Westerberg #define FUNCTION(n, g) \ 2106e08d6bbSMika Westerberg { \ 2116e08d6bbSMika Westerberg .name = (n), \ 2126e08d6bbSMika Westerberg .groups = (g), \ 2136e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE((g)), \ 2146e08d6bbSMika Westerberg } 2156e08d6bbSMika Westerberg 2166e08d6bbSMika Westerberg #define GPIO_PINRANGE(start, end) \ 2176e08d6bbSMika Westerberg { \ 2186e08d6bbSMika Westerberg .base = (start), \ 2196e08d6bbSMika Westerberg .npins = (end) - (start) + 1, \ 2206e08d6bbSMika Westerberg } 2216e08d6bbSMika Westerberg 2226e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southwest_pins[] = { 2236e08d6bbSMika Westerberg PINCTRL_PIN(0, "FST_SPI_D2"), 2246e08d6bbSMika Westerberg PINCTRL_PIN(1, "FST_SPI_D0"), 2256e08d6bbSMika Westerberg PINCTRL_PIN(2, "FST_SPI_CLK"), 2266e08d6bbSMika Westerberg PINCTRL_PIN(3, "FST_SPI_D3"), 2276e08d6bbSMika Westerberg PINCTRL_PIN(4, "FST_SPI_CS1_B"), 2286e08d6bbSMika Westerberg PINCTRL_PIN(5, "FST_SPI_D1"), 2296e08d6bbSMika Westerberg PINCTRL_PIN(6, "FST_SPI_CS0_B"), 2306e08d6bbSMika Westerberg PINCTRL_PIN(7, "FST_SPI_CS2_B"), 2316e08d6bbSMika Westerberg 2326e08d6bbSMika Westerberg PINCTRL_PIN(15, "UART1_RTS_B"), 2336e08d6bbSMika Westerberg PINCTRL_PIN(16, "UART1_RXD"), 2346e08d6bbSMika Westerberg PINCTRL_PIN(17, "UART2_RXD"), 2356e08d6bbSMika Westerberg PINCTRL_PIN(18, "UART1_CTS_B"), 2366e08d6bbSMika Westerberg PINCTRL_PIN(19, "UART2_RTS_B"), 2376e08d6bbSMika Westerberg PINCTRL_PIN(20, "UART1_TXD"), 2386e08d6bbSMika Westerberg PINCTRL_PIN(21, "UART2_TXD"), 2396e08d6bbSMika Westerberg PINCTRL_PIN(22, "UART2_CTS_B"), 2406e08d6bbSMika Westerberg 2416e08d6bbSMika Westerberg PINCTRL_PIN(30, "MF_HDA_CLK"), 2426e08d6bbSMika Westerberg PINCTRL_PIN(31, "MF_HDA_RSTB"), 2436e08d6bbSMika Westerberg PINCTRL_PIN(32, "MF_HDA_SDIO"), 2446e08d6bbSMika Westerberg PINCTRL_PIN(33, "MF_HDA_SDO"), 2456e08d6bbSMika Westerberg PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 2466e08d6bbSMika Westerberg PINCTRL_PIN(35, "MF_HDA_SYNC"), 2476e08d6bbSMika Westerberg PINCTRL_PIN(36, "MF_HDA_SDI1"), 2486e08d6bbSMika Westerberg PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 2496e08d6bbSMika Westerberg 2506e08d6bbSMika Westerberg PINCTRL_PIN(45, "I2C5_SDA"), 2516e08d6bbSMika Westerberg PINCTRL_PIN(46, "I2C4_SDA"), 2526e08d6bbSMika Westerberg PINCTRL_PIN(47, "I2C6_SDA"), 2536e08d6bbSMika Westerberg PINCTRL_PIN(48, "I2C5_SCL"), 2546e08d6bbSMika Westerberg PINCTRL_PIN(49, "I2C_NFC_SDA"), 2556e08d6bbSMika Westerberg PINCTRL_PIN(50, "I2C4_SCL"), 2566e08d6bbSMika Westerberg PINCTRL_PIN(51, "I2C6_SCL"), 2576e08d6bbSMika Westerberg PINCTRL_PIN(52, "I2C_NFC_SCL"), 2586e08d6bbSMika Westerberg 2596e08d6bbSMika Westerberg PINCTRL_PIN(60, "I2C1_SDA"), 2606e08d6bbSMika Westerberg PINCTRL_PIN(61, "I2C0_SDA"), 2616e08d6bbSMika Westerberg PINCTRL_PIN(62, "I2C2_SDA"), 2626e08d6bbSMika Westerberg PINCTRL_PIN(63, "I2C1_SCL"), 2636e08d6bbSMika Westerberg PINCTRL_PIN(64, "I2C3_SDA"), 2646e08d6bbSMika Westerberg PINCTRL_PIN(65, "I2C0_SCL"), 2656e08d6bbSMika Westerberg PINCTRL_PIN(66, "I2C2_SCL"), 2666e08d6bbSMika Westerberg PINCTRL_PIN(67, "I2C3_SCL"), 2676e08d6bbSMika Westerberg 2686e08d6bbSMika Westerberg PINCTRL_PIN(75, "SATA_GP0"), 2696e08d6bbSMika Westerberg PINCTRL_PIN(76, "SATA_GP1"), 2706e08d6bbSMika Westerberg PINCTRL_PIN(77, "SATA_LEDN"), 2716e08d6bbSMika Westerberg PINCTRL_PIN(78, "SATA_GP2"), 2726e08d6bbSMika Westerberg PINCTRL_PIN(79, "MF_SMB_ALERTB"), 2736e08d6bbSMika Westerberg PINCTRL_PIN(80, "SATA_GP3"), 2746e08d6bbSMika Westerberg PINCTRL_PIN(81, "MF_SMB_CLK"), 2756e08d6bbSMika Westerberg PINCTRL_PIN(82, "MF_SMB_DATA"), 2766e08d6bbSMika Westerberg 2776e08d6bbSMika Westerberg PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 2786e08d6bbSMika Westerberg PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 2796e08d6bbSMika Westerberg PINCTRL_PIN(92, "GP_SSP_2_CLK"), 2806e08d6bbSMika Westerberg PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 2816e08d6bbSMika Westerberg PINCTRL_PIN(94, "GP_SSP_2_RXD"), 2826e08d6bbSMika Westerberg PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 2836e08d6bbSMika Westerberg PINCTRL_PIN(96, "GP_SSP_2_FS"), 2846e08d6bbSMika Westerberg PINCTRL_PIN(97, "GP_SSP_2_TXD"), 2856e08d6bbSMika Westerberg }; 2866e08d6bbSMika Westerberg 2876e08d6bbSMika Westerberg static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 2886e08d6bbSMika Westerberg static const unsigned southwest_uart0_pins[] = { 16, 20 }; 2896e08d6bbSMika Westerberg static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 2906e08d6bbSMika Westerberg static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 2916e08d6bbSMika Westerberg static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 2926e08d6bbSMika Westerberg static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 2936e08d6bbSMika Westerberg static const unsigned southwest_lpe_pins[] = { 2946e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 2956e08d6bbSMika Westerberg }; 2966e08d6bbSMika Westerberg static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 2976e08d6bbSMika Westerberg static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 2986e08d6bbSMika Westerberg static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 2996e08d6bbSMika Westerberg static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 3006e08d6bbSMika Westerberg static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 3016e08d6bbSMika Westerberg static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 3026e08d6bbSMika Westerberg static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 3036e08d6bbSMika Westerberg static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 3046e08d6bbSMika Westerberg static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 3056e08d6bbSMika Westerberg 3066e08d6bbSMika Westerberg /* LPE I2S TXD pins need to have invert_oe set */ 3076e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 3086e08d6bbSMika Westerberg ALTERNATE_FUNCTION(30, 1, true), 3096e08d6bbSMika Westerberg ALTERNATE_FUNCTION(34, 1, true), 3106e08d6bbSMika Westerberg ALTERNATE_FUNCTION(97, 1, true), 3116e08d6bbSMika Westerberg }; 3126e08d6bbSMika Westerberg 3136e08d6bbSMika Westerberg /* 3146e08d6bbSMika Westerberg * Two spi3 chipselects are available in different mode than the main spi3 3156e08d6bbSMika Westerberg * functionality, which is using mode 1. 3166e08d6bbSMika Westerberg */ 3176e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 3186e08d6bbSMika Westerberg ALTERNATE_FUNCTION(76, 3, false), 3196e08d6bbSMika Westerberg ALTERNATE_FUNCTION(80, 3, false), 3206e08d6bbSMika Westerberg }; 3216e08d6bbSMika Westerberg 3226e08d6bbSMika Westerberg static const struct chv_pingroup southwest_groups[] = { 3236e08d6bbSMika Westerberg PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 3246e08d6bbSMika Westerberg PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 3256e08d6bbSMika Westerberg PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 3266e08d6bbSMika Westerberg PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 3276e08d6bbSMika Westerberg PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 3286e08d6bbSMika Westerberg PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 3296e08d6bbSMika Westerberg PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 3306e08d6bbSMika Westerberg PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 3316e08d6bbSMika Westerberg PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 3326e08d6bbSMika Westerberg PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 3336e08d6bbSMika Westerberg PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 3346e08d6bbSMika Westerberg PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 3356e08d6bbSMika Westerberg 3366e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 3376e08d6bbSMika Westerberg southwest_lpe_altfuncs), 3386e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 3396e08d6bbSMika Westerberg southwest_spi3_altfuncs), 3406e08d6bbSMika Westerberg }; 3416e08d6bbSMika Westerberg 3426e08d6bbSMika Westerberg static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 3436e08d6bbSMika Westerberg static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 3446e08d6bbSMika Westerberg static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 3456e08d6bbSMika Westerberg static const char * const southwest_hda_groups[] = { "hda_grp" }; 3466e08d6bbSMika Westerberg static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 3476e08d6bbSMika Westerberg static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 3486e08d6bbSMika Westerberg static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 3496e08d6bbSMika Westerberg static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 3506e08d6bbSMika Westerberg static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 3516e08d6bbSMika Westerberg static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 3526e08d6bbSMika Westerberg static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 3536e08d6bbSMika Westerberg static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 3546e08d6bbSMika Westerberg static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 3556e08d6bbSMika Westerberg static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 3566e08d6bbSMika Westerberg 3576e08d6bbSMika Westerberg /* 3586e08d6bbSMika Westerberg * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 3596e08d6bbSMika Westerberg * enabled only as GPIOs. 3606e08d6bbSMika Westerberg */ 3616e08d6bbSMika Westerberg static const struct chv_function southwest_functions[] = { 3626e08d6bbSMika Westerberg FUNCTION("uart0", southwest_uart0_groups), 3636e08d6bbSMika Westerberg FUNCTION("uart1", southwest_uart1_groups), 3646e08d6bbSMika Westerberg FUNCTION("uart2", southwest_uart2_groups), 3656e08d6bbSMika Westerberg FUNCTION("hda", southwest_hda_groups), 3666e08d6bbSMika Westerberg FUNCTION("lpe", southwest_lpe_groups), 3676e08d6bbSMika Westerberg FUNCTION("i2c0", southwest_i2c0_groups), 3686e08d6bbSMika Westerberg FUNCTION("i2c1", southwest_i2c1_groups), 3696e08d6bbSMika Westerberg FUNCTION("i2c2", southwest_i2c2_groups), 3706e08d6bbSMika Westerberg FUNCTION("i2c3", southwest_i2c3_groups), 3716e08d6bbSMika Westerberg FUNCTION("i2c4", southwest_i2c4_groups), 3726e08d6bbSMika Westerberg FUNCTION("i2c5", southwest_i2c5_groups), 3736e08d6bbSMika Westerberg FUNCTION("i2c6", southwest_i2c6_groups), 3746e08d6bbSMika Westerberg FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 3756e08d6bbSMika Westerberg FUNCTION("spi3", southwest_spi3_groups), 3766e08d6bbSMika Westerberg }; 3776e08d6bbSMika Westerberg 3786e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 3796e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 3806e08d6bbSMika Westerberg GPIO_PINRANGE(15, 22), 3816e08d6bbSMika Westerberg GPIO_PINRANGE(30, 37), 3826e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 3836e08d6bbSMika Westerberg GPIO_PINRANGE(60, 67), 3846e08d6bbSMika Westerberg GPIO_PINRANGE(75, 82), 3856e08d6bbSMika Westerberg GPIO_PINRANGE(90, 97), 3866e08d6bbSMika Westerberg }; 3876e08d6bbSMika Westerberg 3886e08d6bbSMika Westerberg static const struct chv_community southwest_community = { 3896e08d6bbSMika Westerberg .uid = "1", 3906e08d6bbSMika Westerberg .pins = southwest_pins, 3916e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southwest_pins), 3926e08d6bbSMika Westerberg .groups = southwest_groups, 3936e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southwest_groups), 3946e08d6bbSMika Westerberg .functions = southwest_functions, 3956e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southwest_functions), 3966e08d6bbSMika Westerberg .gpio_ranges = southwest_gpio_ranges, 3976e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 3986e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(southwest_pins), 3996e08d6bbSMika Westerberg }; 4006e08d6bbSMika Westerberg 4016e08d6bbSMika Westerberg static const struct pinctrl_pin_desc north_pins[] = { 4026e08d6bbSMika Westerberg PINCTRL_PIN(0, "GPIO_DFX_0"), 4036e08d6bbSMika Westerberg PINCTRL_PIN(1, "GPIO_DFX_3"), 4046e08d6bbSMika Westerberg PINCTRL_PIN(2, "GPIO_DFX_7"), 4056e08d6bbSMika Westerberg PINCTRL_PIN(3, "GPIO_DFX_1"), 4066e08d6bbSMika Westerberg PINCTRL_PIN(4, "GPIO_DFX_5"), 4076e08d6bbSMika Westerberg PINCTRL_PIN(5, "GPIO_DFX_4"), 4086e08d6bbSMika Westerberg PINCTRL_PIN(6, "GPIO_DFX_8"), 4096e08d6bbSMika Westerberg PINCTRL_PIN(7, "GPIO_DFX_2"), 4106e08d6bbSMika Westerberg PINCTRL_PIN(8, "GPIO_DFX_6"), 4116e08d6bbSMika Westerberg 4126e08d6bbSMika Westerberg PINCTRL_PIN(15, "GPIO_SUS0"), 4136e08d6bbSMika Westerberg PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 4146e08d6bbSMika Westerberg PINCTRL_PIN(17, "GPIO_SUS3"), 4156e08d6bbSMika Westerberg PINCTRL_PIN(18, "GPIO_SUS7"), 4166e08d6bbSMika Westerberg PINCTRL_PIN(19, "GPIO_SUS1"), 4176e08d6bbSMika Westerberg PINCTRL_PIN(20, "GPIO_SUS5"), 4186e08d6bbSMika Westerberg PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 4196e08d6bbSMika Westerberg PINCTRL_PIN(22, "GPIO_SUS4"), 4206e08d6bbSMika Westerberg PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 4216e08d6bbSMika Westerberg PINCTRL_PIN(24, "GPIO_SUS2"), 4226e08d6bbSMika Westerberg PINCTRL_PIN(25, "GPIO_SUS6"), 4236e08d6bbSMika Westerberg PINCTRL_PIN(26, "CX_PREQ_B"), 4246e08d6bbSMika Westerberg PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 4256e08d6bbSMika Westerberg 4266e08d6bbSMika Westerberg PINCTRL_PIN(30, "TRST_B"), 4276e08d6bbSMika Westerberg PINCTRL_PIN(31, "TCK"), 4286e08d6bbSMika Westerberg PINCTRL_PIN(32, "PROCHOT_B"), 4296e08d6bbSMika Westerberg PINCTRL_PIN(33, "SVIDO_DATA"), 4306e08d6bbSMika Westerberg PINCTRL_PIN(34, "TMS"), 4316e08d6bbSMika Westerberg PINCTRL_PIN(35, "CX_PRDY_B_2"), 4326e08d6bbSMika Westerberg PINCTRL_PIN(36, "TDO_2"), 4336e08d6bbSMika Westerberg PINCTRL_PIN(37, "CX_PRDY_B"), 4346e08d6bbSMika Westerberg PINCTRL_PIN(38, "SVIDO_ALERT_B"), 4356e08d6bbSMika Westerberg PINCTRL_PIN(39, "TDO"), 4366e08d6bbSMika Westerberg PINCTRL_PIN(40, "SVIDO_CLK"), 4376e08d6bbSMika Westerberg PINCTRL_PIN(41, "TDI"), 4386e08d6bbSMika Westerberg 4396e08d6bbSMika Westerberg PINCTRL_PIN(45, "GP_CAMERASB_05"), 4406e08d6bbSMika Westerberg PINCTRL_PIN(46, "GP_CAMERASB_02"), 4416e08d6bbSMika Westerberg PINCTRL_PIN(47, "GP_CAMERASB_08"), 4426e08d6bbSMika Westerberg PINCTRL_PIN(48, "GP_CAMERASB_00"), 4436e08d6bbSMika Westerberg PINCTRL_PIN(49, "GP_CAMERASB_06"), 4446e08d6bbSMika Westerberg PINCTRL_PIN(50, "GP_CAMERASB_10"), 4456e08d6bbSMika Westerberg PINCTRL_PIN(51, "GP_CAMERASB_03"), 4466e08d6bbSMika Westerberg PINCTRL_PIN(52, "GP_CAMERASB_09"), 4476e08d6bbSMika Westerberg PINCTRL_PIN(53, "GP_CAMERASB_01"), 4486e08d6bbSMika Westerberg PINCTRL_PIN(54, "GP_CAMERASB_07"), 4496e08d6bbSMika Westerberg PINCTRL_PIN(55, "GP_CAMERASB_11"), 4506e08d6bbSMika Westerberg PINCTRL_PIN(56, "GP_CAMERASB_04"), 4516e08d6bbSMika Westerberg 4526e08d6bbSMika Westerberg PINCTRL_PIN(60, "PANEL0_BKLTEN"), 4536e08d6bbSMika Westerberg PINCTRL_PIN(61, "HV_DDI0_HPD"), 4546e08d6bbSMika Westerberg PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 4556e08d6bbSMika Westerberg PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 4566e08d6bbSMika Westerberg PINCTRL_PIN(64, "HV_DDI1_HPD"), 4576e08d6bbSMika Westerberg PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 4586e08d6bbSMika Westerberg PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 4596e08d6bbSMika Westerberg PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 4606e08d6bbSMika Westerberg PINCTRL_PIN(68, "HV_DDI2_HPD"), 4616e08d6bbSMika Westerberg PINCTRL_PIN(69, "PANEL1_VDDEN"), 4626e08d6bbSMika Westerberg PINCTRL_PIN(70, "PANEL1_BKLTEN"), 4636e08d6bbSMika Westerberg PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 4646e08d6bbSMika Westerberg PINCTRL_PIN(72, "PANEL0_VDDEN"), 4656e08d6bbSMika Westerberg }; 4666e08d6bbSMika Westerberg 4676e08d6bbSMika Westerberg static const struct chv_gpio_pinrange north_gpio_ranges[] = { 4686e08d6bbSMika Westerberg GPIO_PINRANGE(0, 8), 4696e08d6bbSMika Westerberg GPIO_PINRANGE(15, 27), 4706e08d6bbSMika Westerberg GPIO_PINRANGE(30, 41), 4716e08d6bbSMika Westerberg GPIO_PINRANGE(45, 56), 4726e08d6bbSMika Westerberg GPIO_PINRANGE(60, 72), 4736e08d6bbSMika Westerberg }; 4746e08d6bbSMika Westerberg 4756e08d6bbSMika Westerberg static const struct chv_community north_community = { 4766e08d6bbSMika Westerberg .uid = "2", 4776e08d6bbSMika Westerberg .pins = north_pins, 4786e08d6bbSMika Westerberg .npins = ARRAY_SIZE(north_pins), 4796e08d6bbSMika Westerberg .gpio_ranges = north_gpio_ranges, 4806e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 4816e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(north_pins), 4826e08d6bbSMika Westerberg }; 4836e08d6bbSMika Westerberg 4846e08d6bbSMika Westerberg static const struct pinctrl_pin_desc east_pins[] = { 4856e08d6bbSMika Westerberg PINCTRL_PIN(0, "PMU_SLP_S3_B"), 4866e08d6bbSMika Westerberg PINCTRL_PIN(1, "PMU_BATLOW_B"), 4876e08d6bbSMika Westerberg PINCTRL_PIN(2, "SUS_STAT_B"), 4886e08d6bbSMika Westerberg PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 4896e08d6bbSMika Westerberg PINCTRL_PIN(4, "PMU_AC_PRESENT"), 4906e08d6bbSMika Westerberg PINCTRL_PIN(5, "PMU_PLTRST_B"), 4916e08d6bbSMika Westerberg PINCTRL_PIN(6, "PMU_SUSCLK"), 4926e08d6bbSMika Westerberg PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 4936e08d6bbSMika Westerberg PINCTRL_PIN(8, "PMU_PWRBTN_B"), 4946e08d6bbSMika Westerberg PINCTRL_PIN(9, "PMU_SLP_S4_B"), 4956e08d6bbSMika Westerberg PINCTRL_PIN(10, "PMU_WAKE_B"), 4966e08d6bbSMika Westerberg PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 4976e08d6bbSMika Westerberg 4986e08d6bbSMika Westerberg PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 4996e08d6bbSMika Westerberg PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 5006e08d6bbSMika Westerberg PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 5016e08d6bbSMika Westerberg PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 5026e08d6bbSMika Westerberg PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 5036e08d6bbSMika Westerberg PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 5046e08d6bbSMika Westerberg PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 5056e08d6bbSMika Westerberg PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 5066e08d6bbSMika Westerberg PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 5076e08d6bbSMika Westerberg PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 5086e08d6bbSMika Westerberg PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 5096e08d6bbSMika Westerberg PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 5106e08d6bbSMika Westerberg }; 5116e08d6bbSMika Westerberg 5126e08d6bbSMika Westerberg static const struct chv_gpio_pinrange east_gpio_ranges[] = { 5136e08d6bbSMika Westerberg GPIO_PINRANGE(0, 11), 5146e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 5156e08d6bbSMika Westerberg }; 5166e08d6bbSMika Westerberg 5176e08d6bbSMika Westerberg static const struct chv_community east_community = { 5186e08d6bbSMika Westerberg .uid = "3", 5196e08d6bbSMika Westerberg .pins = east_pins, 5206e08d6bbSMika Westerberg .npins = ARRAY_SIZE(east_pins), 5216e08d6bbSMika Westerberg .gpio_ranges = east_gpio_ranges, 5226e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 5236e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(east_pins), 5246e08d6bbSMika Westerberg }; 5256e08d6bbSMika Westerberg 5266e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southeast_pins[] = { 5276e08d6bbSMika Westerberg PINCTRL_PIN(0, "MF_PLT_CLK0"), 5286e08d6bbSMika Westerberg PINCTRL_PIN(1, "PWM1"), 5296e08d6bbSMika Westerberg PINCTRL_PIN(2, "MF_PLT_CLK1"), 5306e08d6bbSMika Westerberg PINCTRL_PIN(3, "MF_PLT_CLK4"), 5316e08d6bbSMika Westerberg PINCTRL_PIN(4, "MF_PLT_CLK3"), 5326e08d6bbSMika Westerberg PINCTRL_PIN(5, "PWM0"), 5336e08d6bbSMika Westerberg PINCTRL_PIN(6, "MF_PLT_CLK5"), 5346e08d6bbSMika Westerberg PINCTRL_PIN(7, "MF_PLT_CLK2"), 5356e08d6bbSMika Westerberg 5366e08d6bbSMika Westerberg PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 5376e08d6bbSMika Westerberg PINCTRL_PIN(16, "SDMMC1_CLK"), 5386e08d6bbSMika Westerberg PINCTRL_PIN(17, "SDMMC1_D0"), 5396e08d6bbSMika Westerberg PINCTRL_PIN(18, "SDMMC2_D1"), 5406e08d6bbSMika Westerberg PINCTRL_PIN(19, "SDMMC2_CLK"), 5416e08d6bbSMika Westerberg PINCTRL_PIN(20, "SDMMC1_D2"), 5426e08d6bbSMika Westerberg PINCTRL_PIN(21, "SDMMC2_D2"), 5436e08d6bbSMika Westerberg PINCTRL_PIN(22, "SDMMC2_CMD"), 5446e08d6bbSMika Westerberg PINCTRL_PIN(23, "SDMMC1_CMD"), 5456e08d6bbSMika Westerberg PINCTRL_PIN(24, "SDMMC1_D1"), 5466e08d6bbSMika Westerberg PINCTRL_PIN(25, "SDMMC2_D0"), 5476e08d6bbSMika Westerberg PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 5486e08d6bbSMika Westerberg 5496e08d6bbSMika Westerberg PINCTRL_PIN(30, "SDMMC3_D1"), 5506e08d6bbSMika Westerberg PINCTRL_PIN(31, "SDMMC3_CLK"), 5516e08d6bbSMika Westerberg PINCTRL_PIN(32, "SDMMC3_D3"), 5526e08d6bbSMika Westerberg PINCTRL_PIN(33, "SDMMC3_D2"), 5536e08d6bbSMika Westerberg PINCTRL_PIN(34, "SDMMC3_CMD"), 5546e08d6bbSMika Westerberg PINCTRL_PIN(35, "SDMMC3_D0"), 5556e08d6bbSMika Westerberg 5566e08d6bbSMika Westerberg PINCTRL_PIN(45, "MF_LPC_AD2"), 5576e08d6bbSMika Westerberg PINCTRL_PIN(46, "LPC_CLKRUNB"), 5586e08d6bbSMika Westerberg PINCTRL_PIN(47, "MF_LPC_AD0"), 5596e08d6bbSMika Westerberg PINCTRL_PIN(48, "LPC_FRAMEB"), 5606e08d6bbSMika Westerberg PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 5616e08d6bbSMika Westerberg PINCTRL_PIN(50, "MF_LPC_AD3"), 5626e08d6bbSMika Westerberg PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 5636e08d6bbSMika Westerberg PINCTRL_PIN(52, "MF_LPC_AD1"), 5646e08d6bbSMika Westerberg 5656e08d6bbSMika Westerberg PINCTRL_PIN(60, "SPI1_MISO"), 5666e08d6bbSMika Westerberg PINCTRL_PIN(61, "SPI1_CSO_B"), 5676e08d6bbSMika Westerberg PINCTRL_PIN(62, "SPI1_CLK"), 5686e08d6bbSMika Westerberg PINCTRL_PIN(63, "MMC1_D6"), 5696e08d6bbSMika Westerberg PINCTRL_PIN(64, "SPI1_MOSI"), 5706e08d6bbSMika Westerberg PINCTRL_PIN(65, "MMC1_D5"), 5716e08d6bbSMika Westerberg PINCTRL_PIN(66, "SPI1_CS1_B"), 5726e08d6bbSMika Westerberg PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 5736e08d6bbSMika Westerberg PINCTRL_PIN(68, "MMC1_D7"), 5746e08d6bbSMika Westerberg PINCTRL_PIN(69, "MMC1_RCLK"), 5756e08d6bbSMika Westerberg 5766e08d6bbSMika Westerberg PINCTRL_PIN(75, "USB_OC1_B"), 5776e08d6bbSMika Westerberg PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 5786e08d6bbSMika Westerberg PINCTRL_PIN(77, "GPIO_ALERT"), 5796e08d6bbSMika Westerberg PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 5806e08d6bbSMika Westerberg PINCTRL_PIN(79, "ILB_SERIRQ"), 5816e08d6bbSMika Westerberg PINCTRL_PIN(80, "USB_OC0_B"), 5826e08d6bbSMika Westerberg PINCTRL_PIN(81, "SDMMC3_CD_B"), 5836e08d6bbSMika Westerberg PINCTRL_PIN(82, "SPKR"), 5846e08d6bbSMika Westerberg PINCTRL_PIN(83, "SUSPWRDNACK"), 5856e08d6bbSMika Westerberg PINCTRL_PIN(84, "SPARE_PIN"), 5866e08d6bbSMika Westerberg PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 5876e08d6bbSMika Westerberg }; 5886e08d6bbSMika Westerberg 5896e08d6bbSMika Westerberg static const unsigned southeast_pwm0_pins[] = { 5 }; 5906e08d6bbSMika Westerberg static const unsigned southeast_pwm1_pins[] = { 1 }; 5916e08d6bbSMika Westerberg static const unsigned southeast_sdmmc1_pins[] = { 5926e08d6bbSMika Westerberg 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 5936e08d6bbSMika Westerberg }; 5946e08d6bbSMika Westerberg static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 5956e08d6bbSMika Westerberg static const unsigned southeast_sdmmc3_pins[] = { 5966e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 78, 81, 85, 5976e08d6bbSMika Westerberg }; 5986e08d6bbSMika Westerberg static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 5996e08d6bbSMika Westerberg static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 6006e08d6bbSMika Westerberg 6016e08d6bbSMika Westerberg static const struct chv_pingroup southeast_groups[] = { 6026e08d6bbSMika Westerberg PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 6036e08d6bbSMika Westerberg PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 6046e08d6bbSMika Westerberg PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 6056e08d6bbSMika Westerberg PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 6066e08d6bbSMika Westerberg PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 6076e08d6bbSMika Westerberg PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 6086e08d6bbSMika Westerberg PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 6096e08d6bbSMika Westerberg }; 6106e08d6bbSMika Westerberg 6116e08d6bbSMika Westerberg static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 6126e08d6bbSMika Westerberg static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 6136e08d6bbSMika Westerberg static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 6146e08d6bbSMika Westerberg static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 6156e08d6bbSMika Westerberg static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 6166e08d6bbSMika Westerberg static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 6176e08d6bbSMika Westerberg static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 6186e08d6bbSMika Westerberg 6196e08d6bbSMika Westerberg static const struct chv_function southeast_functions[] = { 6206e08d6bbSMika Westerberg FUNCTION("pwm0", southeast_pwm0_groups), 6216e08d6bbSMika Westerberg FUNCTION("pwm1", southeast_pwm1_groups), 6226e08d6bbSMika Westerberg FUNCTION("sdmmc1", southeast_sdmmc1_groups), 6236e08d6bbSMika Westerberg FUNCTION("sdmmc2", southeast_sdmmc2_groups), 6246e08d6bbSMika Westerberg FUNCTION("sdmmc3", southeast_sdmmc3_groups), 6256e08d6bbSMika Westerberg FUNCTION("spi1", southeast_spi1_groups), 6266e08d6bbSMika Westerberg FUNCTION("spi2", southeast_spi2_groups), 6276e08d6bbSMika Westerberg }; 6286e08d6bbSMika Westerberg 6296e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 6306e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 6316e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 6326e08d6bbSMika Westerberg GPIO_PINRANGE(30, 35), 6336e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 6346e08d6bbSMika Westerberg GPIO_PINRANGE(60, 69), 6356e08d6bbSMika Westerberg GPIO_PINRANGE(75, 85), 6366e08d6bbSMika Westerberg }; 6376e08d6bbSMika Westerberg 6386e08d6bbSMika Westerberg static const struct chv_community southeast_community = { 6396e08d6bbSMika Westerberg .uid = "4", 6406e08d6bbSMika Westerberg .pins = southeast_pins, 6416e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southeast_pins), 6426e08d6bbSMika Westerberg .groups = southeast_groups, 6436e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southeast_groups), 6446e08d6bbSMika Westerberg .functions = southeast_functions, 6456e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southeast_functions), 6466e08d6bbSMika Westerberg .gpio_ranges = southeast_gpio_ranges, 6476e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 6486e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(southeast_pins), 6496e08d6bbSMika Westerberg }; 6506e08d6bbSMika Westerberg 6516e08d6bbSMika Westerberg static const struct chv_community *chv_communities[] = { 6526e08d6bbSMika Westerberg &southwest_community, 6536e08d6bbSMika Westerberg &north_community, 6546e08d6bbSMika Westerberg &east_community, 6556e08d6bbSMika Westerberg &southeast_community, 6566e08d6bbSMika Westerberg }; 6576e08d6bbSMika Westerberg 6580bd50d71SDan O'Donovan /* 6590bd50d71SDan O'Donovan * Lock to serialize register accesses 6600bd50d71SDan O'Donovan * 6610bd50d71SDan O'Donovan * Due to a silicon issue, a shared lock must be used to prevent 6620bd50d71SDan O'Donovan * concurrent accesses across the 4 GPIO controllers. 6630bd50d71SDan O'Donovan * 6640bd50d71SDan O'Donovan * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 6650bd50d71SDan O'Donovan * errata #CHT34, for further information. 6660bd50d71SDan O'Donovan */ 6670bd50d71SDan O'Donovan static DEFINE_RAW_SPINLOCK(chv_lock); 6680bd50d71SDan O'Donovan 6696e08d6bbSMika Westerberg static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 6706e08d6bbSMika Westerberg unsigned reg) 6716e08d6bbSMika Westerberg { 6726e08d6bbSMika Westerberg unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 6736e08d6bbSMika Westerberg unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 6746e08d6bbSMika Westerberg 6756e08d6bbSMika Westerberg offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 6766e08d6bbSMika Westerberg GPIO_REGS_SIZE * pad_no; 6776e08d6bbSMika Westerberg 6786e08d6bbSMika Westerberg return pctrl->regs + offset + reg; 6796e08d6bbSMika Westerberg } 6806e08d6bbSMika Westerberg 6816e08d6bbSMika Westerberg static void chv_writel(u32 value, void __iomem *reg) 6826e08d6bbSMika Westerberg { 6836e08d6bbSMika Westerberg writel(value, reg); 6846e08d6bbSMika Westerberg /* simple readback to confirm the bus transferring done */ 6856e08d6bbSMika Westerberg readl(reg); 6866e08d6bbSMika Westerberg } 6876e08d6bbSMika Westerberg 6886e08d6bbSMika Westerberg /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 6896e08d6bbSMika Westerberg static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 6906e08d6bbSMika Westerberg { 6916e08d6bbSMika Westerberg void __iomem *reg; 6926e08d6bbSMika Westerberg 6936e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 6946e08d6bbSMika Westerberg return readl(reg) & CHV_PADCTRL1_CFGLOCK; 6956e08d6bbSMika Westerberg } 6966e08d6bbSMika Westerberg 6976e08d6bbSMika Westerberg static int chv_get_groups_count(struct pinctrl_dev *pctldev) 6986e08d6bbSMika Westerberg { 6996e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7006e08d6bbSMika Westerberg 7016e08d6bbSMika Westerberg return pctrl->community->ngroups; 7026e08d6bbSMika Westerberg } 7036e08d6bbSMika Westerberg 7046e08d6bbSMika Westerberg static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 7056e08d6bbSMika Westerberg unsigned group) 7066e08d6bbSMika Westerberg { 7076e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7086e08d6bbSMika Westerberg 7096e08d6bbSMika Westerberg return pctrl->community->groups[group].name; 7106e08d6bbSMika Westerberg } 7116e08d6bbSMika Westerberg 7126e08d6bbSMika Westerberg static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 7136e08d6bbSMika Westerberg const unsigned **pins, unsigned *npins) 7146e08d6bbSMika Westerberg { 7156e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7166e08d6bbSMika Westerberg 7176e08d6bbSMika Westerberg *pins = pctrl->community->groups[group].pins; 7186e08d6bbSMika Westerberg *npins = pctrl->community->groups[group].npins; 7196e08d6bbSMika Westerberg return 0; 7206e08d6bbSMika Westerberg } 7216e08d6bbSMika Westerberg 7226e08d6bbSMika Westerberg static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 7236e08d6bbSMika Westerberg unsigned offset) 7246e08d6bbSMika Westerberg { 7256e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7266e08d6bbSMika Westerberg unsigned long flags; 7276e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 7286e08d6bbSMika Westerberg bool locked; 7296e08d6bbSMika Westerberg 7300bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 7316e08d6bbSMika Westerberg 7326e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 7336e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 7346e08d6bbSMika Westerberg locked = chv_pad_locked(pctrl, offset); 7356e08d6bbSMika Westerberg 7360bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 7376e08d6bbSMika Westerberg 7386e08d6bbSMika Westerberg if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 7396e08d6bbSMika Westerberg seq_puts(s, "GPIO "); 7406e08d6bbSMika Westerberg } else { 7416e08d6bbSMika Westerberg u32 mode; 7426e08d6bbSMika Westerberg 7436e08d6bbSMika Westerberg mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 7446e08d6bbSMika Westerberg mode >>= CHV_PADCTRL0_PMODE_SHIFT; 7456e08d6bbSMika Westerberg 7466e08d6bbSMika Westerberg seq_printf(s, "mode %d ", mode); 7476e08d6bbSMika Westerberg } 7486e08d6bbSMika Westerberg 7496e08d6bbSMika Westerberg seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1); 7506e08d6bbSMika Westerberg 7516e08d6bbSMika Westerberg if (locked) 7526e08d6bbSMika Westerberg seq_puts(s, " [LOCKED]"); 7536e08d6bbSMika Westerberg } 7546e08d6bbSMika Westerberg 7556e08d6bbSMika Westerberg static const struct pinctrl_ops chv_pinctrl_ops = { 7566e08d6bbSMika Westerberg .get_groups_count = chv_get_groups_count, 7576e08d6bbSMika Westerberg .get_group_name = chv_get_group_name, 7586e08d6bbSMika Westerberg .get_group_pins = chv_get_group_pins, 7596e08d6bbSMika Westerberg .pin_dbg_show = chv_pin_dbg_show, 7606e08d6bbSMika Westerberg }; 7616e08d6bbSMika Westerberg 7626e08d6bbSMika Westerberg static int chv_get_functions_count(struct pinctrl_dev *pctldev) 7636e08d6bbSMika Westerberg { 7646e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7656e08d6bbSMika Westerberg 7666e08d6bbSMika Westerberg return pctrl->community->nfunctions; 7676e08d6bbSMika Westerberg } 7686e08d6bbSMika Westerberg 7696e08d6bbSMika Westerberg static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 7706e08d6bbSMika Westerberg unsigned function) 7716e08d6bbSMika Westerberg { 7726e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7736e08d6bbSMika Westerberg 7746e08d6bbSMika Westerberg return pctrl->community->functions[function].name; 7756e08d6bbSMika Westerberg } 7766e08d6bbSMika Westerberg 7776e08d6bbSMika Westerberg static int chv_get_function_groups(struct pinctrl_dev *pctldev, 7786e08d6bbSMika Westerberg unsigned function, 7796e08d6bbSMika Westerberg const char * const **groups, 7806e08d6bbSMika Westerberg unsigned * const ngroups) 7816e08d6bbSMika Westerberg { 7826e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7836e08d6bbSMika Westerberg 7846e08d6bbSMika Westerberg *groups = pctrl->community->functions[function].groups; 7856e08d6bbSMika Westerberg *ngroups = pctrl->community->functions[function].ngroups; 7866e08d6bbSMika Westerberg return 0; 7876e08d6bbSMika Westerberg } 7886e08d6bbSMika Westerberg 7896e08d6bbSMika Westerberg static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 7906e08d6bbSMika Westerberg unsigned group) 7916e08d6bbSMika Westerberg { 7926e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7936e08d6bbSMika Westerberg const struct chv_pingroup *grp; 7946e08d6bbSMika Westerberg unsigned long flags; 7956e08d6bbSMika Westerberg int i; 7966e08d6bbSMika Westerberg 7976e08d6bbSMika Westerberg grp = &pctrl->community->groups[group]; 7986e08d6bbSMika Westerberg 7990bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 8006e08d6bbSMika Westerberg 8016e08d6bbSMika Westerberg /* Check first that the pad is not locked */ 8026e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 8036e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, grp->pins[i])) { 8046e08d6bbSMika Westerberg dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 8056e08d6bbSMika Westerberg grp->pins[i]); 8060bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8076e08d6bbSMika Westerberg return -EBUSY; 8086e08d6bbSMika Westerberg } 8096e08d6bbSMika Westerberg } 8106e08d6bbSMika Westerberg 8116e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 8126e08d6bbSMika Westerberg const struct chv_alternate_function *altfunc = &grp->altfunc; 8136e08d6bbSMika Westerberg int pin = grp->pins[i]; 8146e08d6bbSMika Westerberg void __iomem *reg; 8156e08d6bbSMika Westerberg u32 value; 8166e08d6bbSMika Westerberg 8176e08d6bbSMika Westerberg /* Check if there is pin-specific config */ 8186e08d6bbSMika Westerberg if (grp->overrides) { 8196e08d6bbSMika Westerberg int j; 8206e08d6bbSMika Westerberg 8216e08d6bbSMika Westerberg for (j = 0; j < grp->noverrides; j++) { 8226e08d6bbSMika Westerberg if (grp->overrides[j].pin == pin) { 8236e08d6bbSMika Westerberg altfunc = &grp->overrides[j]; 8246e08d6bbSMika Westerberg break; 8256e08d6bbSMika Westerberg } 8266e08d6bbSMika Westerberg } 8276e08d6bbSMika Westerberg } 8286e08d6bbSMika Westerberg 8296e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 8306e08d6bbSMika Westerberg value = readl(reg); 8316e08d6bbSMika Westerberg /* Disable GPIO mode */ 8326e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_GPIOEN; 8336e08d6bbSMika Westerberg /* Set to desired mode */ 8346e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_PMODE_MASK; 8356e08d6bbSMika Westerberg value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 8366e08d6bbSMika Westerberg chv_writel(value, reg); 8376e08d6bbSMika Westerberg 8386e08d6bbSMika Westerberg /* Update for invert_oe */ 8396e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 8406e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 8416e08d6bbSMika Westerberg if (altfunc->invert_oe) 8426e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 8436e08d6bbSMika Westerberg chv_writel(value, reg); 8446e08d6bbSMika Westerberg 8456e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 8466e08d6bbSMika Westerberg pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 8476e08d6bbSMika Westerberg } 8486e08d6bbSMika Westerberg 8490bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8506e08d6bbSMika Westerberg 8516e08d6bbSMika Westerberg return 0; 8526e08d6bbSMika Westerberg } 8536e08d6bbSMika Westerberg 8546e08d6bbSMika Westerberg static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 8556e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 8566e08d6bbSMika Westerberg unsigned offset) 8576e08d6bbSMika Westerberg { 8586e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 8596e08d6bbSMika Westerberg unsigned long flags; 8606e08d6bbSMika Westerberg void __iomem *reg; 8616e08d6bbSMika Westerberg u32 value; 8626e08d6bbSMika Westerberg 8630bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 8646e08d6bbSMika Westerberg 8656e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, offset)) { 8666e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 8676e08d6bbSMika Westerberg if (!(value & CHV_PADCTRL0_GPIOEN)) { 8686e08d6bbSMika Westerberg /* Locked so cannot enable */ 8690bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8706e08d6bbSMika Westerberg return -EBUSY; 8716e08d6bbSMika Westerberg } 8726e08d6bbSMika Westerberg } else { 8736e08d6bbSMika Westerberg int i; 8746e08d6bbSMika Westerberg 8756e08d6bbSMika Westerberg /* Reset the interrupt mapping */ 8766e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 8776e08d6bbSMika Westerberg if (pctrl->intr_lines[i] == offset) { 8786e08d6bbSMika Westerberg pctrl->intr_lines[i] = 0; 8796e08d6bbSMika Westerberg break; 8806e08d6bbSMika Westerberg } 8816e08d6bbSMika Westerberg } 8826e08d6bbSMika Westerberg 8836e08d6bbSMika Westerberg /* Disable interrupt generation */ 8846e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 8856e08d6bbSMika Westerberg value = readl(reg); 8866e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 8876e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 8886e08d6bbSMika Westerberg chv_writel(value, reg); 8896e08d6bbSMika Westerberg 8906e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 8912479c730SMika Westerberg value = readl(reg); 8922479c730SMika Westerberg 8932479c730SMika Westerberg /* 8942479c730SMika Westerberg * If the pin is in HiZ mode (both TX and RX buffers are 8952479c730SMika Westerberg * disabled) we turn it to be input now. 8962479c730SMika Westerberg */ 8972479c730SMika Westerberg if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 8982479c730SMika Westerberg (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 8992479c730SMika Westerberg value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 9002479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOCFG_GPI << 9012479c730SMika Westerberg CHV_PADCTRL0_GPIOCFG_SHIFT; 9022479c730SMika Westerberg } 9032479c730SMika Westerberg 9042479c730SMika Westerberg /* Switch to a GPIO mode */ 9052479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOEN; 9066e08d6bbSMika Westerberg chv_writel(value, reg); 9076e08d6bbSMika Westerberg } 9086e08d6bbSMika Westerberg 9090bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9106e08d6bbSMika Westerberg 9116e08d6bbSMika Westerberg return 0; 9126e08d6bbSMika Westerberg } 9136e08d6bbSMika Westerberg 9146e08d6bbSMika Westerberg static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 9156e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9166e08d6bbSMika Westerberg unsigned offset) 9176e08d6bbSMika Westerberg { 9186e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9196e08d6bbSMika Westerberg unsigned long flags; 9206e08d6bbSMika Westerberg void __iomem *reg; 9216e08d6bbSMika Westerberg u32 value; 9226e08d6bbSMika Westerberg 9230bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9246e08d6bbSMika Westerberg 9256e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9266e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 9276e08d6bbSMika Westerberg chv_writel(value, reg); 9286e08d6bbSMika Westerberg 9290bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9306e08d6bbSMika Westerberg } 9316e08d6bbSMika Westerberg 9326e08d6bbSMika Westerberg static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 9336e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9346e08d6bbSMika Westerberg unsigned offset, bool input) 9356e08d6bbSMika Westerberg { 9366e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9376e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9386e08d6bbSMika Westerberg unsigned long flags; 9396e08d6bbSMika Westerberg u32 ctrl0; 9406e08d6bbSMika Westerberg 9410bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9426e08d6bbSMika Westerberg 9436e08d6bbSMika Westerberg ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 9446e08d6bbSMika Westerberg if (input) 9456e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 9466e08d6bbSMika Westerberg else 9476e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 9486e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 9496e08d6bbSMika Westerberg 9500bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9516e08d6bbSMika Westerberg 9526e08d6bbSMika Westerberg return 0; 9536e08d6bbSMika Westerberg } 9546e08d6bbSMika Westerberg 9556e08d6bbSMika Westerberg static const struct pinmux_ops chv_pinmux_ops = { 9566e08d6bbSMika Westerberg .get_functions_count = chv_get_functions_count, 9576e08d6bbSMika Westerberg .get_function_name = chv_get_function_name, 9586e08d6bbSMika Westerberg .get_function_groups = chv_get_function_groups, 9596e08d6bbSMika Westerberg .set_mux = chv_pinmux_set_mux, 9606e08d6bbSMika Westerberg .gpio_request_enable = chv_gpio_request_enable, 9616e08d6bbSMika Westerberg .gpio_disable_free = chv_gpio_disable_free, 9626e08d6bbSMika Westerberg .gpio_set_direction = chv_gpio_set_direction, 9636e08d6bbSMika Westerberg }; 9646e08d6bbSMika Westerberg 9656e08d6bbSMika Westerberg static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 9666e08d6bbSMika Westerberg unsigned long *config) 9676e08d6bbSMika Westerberg { 9686e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9696e08d6bbSMika Westerberg enum pin_config_param param = pinconf_to_config_param(*config); 9706e08d6bbSMika Westerberg unsigned long flags; 9716e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 9726e08d6bbSMika Westerberg u16 arg = 0; 9736e08d6bbSMika Westerberg u32 term; 9746e08d6bbSMika Westerberg 9750bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9766e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 9776e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 9780bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9796e08d6bbSMika Westerberg 9806e08d6bbSMika Westerberg term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 9816e08d6bbSMika Westerberg 9826e08d6bbSMika Westerberg switch (param) { 9836e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 9846e08d6bbSMika Westerberg if (term) 9856e08d6bbSMika Westerberg return -EINVAL; 9866e08d6bbSMika Westerberg break; 9876e08d6bbSMika Westerberg 9886e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 9896e08d6bbSMika Westerberg if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 9906e08d6bbSMika Westerberg return -EINVAL; 9916e08d6bbSMika Westerberg 9926e08d6bbSMika Westerberg switch (term) { 9936e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 9946e08d6bbSMika Westerberg arg = 20000; 9956e08d6bbSMika Westerberg break; 9966e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 9976e08d6bbSMika Westerberg arg = 5000; 9986e08d6bbSMika Westerberg break; 9996e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_1K: 10006e08d6bbSMika Westerberg arg = 1000; 10016e08d6bbSMika Westerberg break; 10026e08d6bbSMika Westerberg } 10036e08d6bbSMika Westerberg 10046e08d6bbSMika Westerberg break; 10056e08d6bbSMika Westerberg 10066e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 10076e08d6bbSMika Westerberg if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 10086e08d6bbSMika Westerberg return -EINVAL; 10096e08d6bbSMika Westerberg 10106e08d6bbSMika Westerberg switch (term) { 10116e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 10126e08d6bbSMika Westerberg arg = 20000; 10136e08d6bbSMika Westerberg break; 10146e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 10156e08d6bbSMika Westerberg arg = 5000; 10166e08d6bbSMika Westerberg break; 10176e08d6bbSMika Westerberg } 10186e08d6bbSMika Westerberg 10196e08d6bbSMika Westerberg break; 10206e08d6bbSMika Westerberg 10216e08d6bbSMika Westerberg case PIN_CONFIG_DRIVE_OPEN_DRAIN: 10226e08d6bbSMika Westerberg if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 10236e08d6bbSMika Westerberg return -EINVAL; 10246e08d6bbSMika Westerberg break; 10256e08d6bbSMika Westerberg 10266e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 10276e08d6bbSMika Westerberg u32 cfg; 10286e08d6bbSMika Westerberg 10296e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 10306e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 10316e08d6bbSMika Westerberg if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 10326e08d6bbSMika Westerberg return -EINVAL; 10336e08d6bbSMika Westerberg 10346e08d6bbSMika Westerberg break; 10356e08d6bbSMika Westerberg } 10366e08d6bbSMika Westerberg 10376e08d6bbSMika Westerberg default: 10386e08d6bbSMika Westerberg return -ENOTSUPP; 10396e08d6bbSMika Westerberg } 10406e08d6bbSMika Westerberg 10416e08d6bbSMika Westerberg *config = pinconf_to_config_packed(param, arg); 10426e08d6bbSMika Westerberg return 0; 10436e08d6bbSMika Westerberg } 10446e08d6bbSMika Westerberg 10456e08d6bbSMika Westerberg static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 10466e08d6bbSMika Westerberg enum pin_config_param param, u16 arg) 10476e08d6bbSMika Westerberg { 10486e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 10496e08d6bbSMika Westerberg unsigned long flags; 10506e08d6bbSMika Westerberg u32 ctrl0, pull; 10516e08d6bbSMika Westerberg 10520bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 10536e08d6bbSMika Westerberg ctrl0 = readl(reg); 10546e08d6bbSMika Westerberg 10556e08d6bbSMika Westerberg switch (param) { 10566e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 10576e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10586e08d6bbSMika Westerberg break; 10596e08d6bbSMika Westerberg 10606e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 10616e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10626e08d6bbSMika Westerberg 10636e08d6bbSMika Westerberg switch (arg) { 10646e08d6bbSMika Westerberg case 1000: 10656e08d6bbSMika Westerberg /* For 1k there is only pull up */ 10666e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 10676e08d6bbSMika Westerberg break; 10686e08d6bbSMika Westerberg case 5000: 10696e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 10706e08d6bbSMika Westerberg break; 10716e08d6bbSMika Westerberg case 20000: 10726e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 10736e08d6bbSMika Westerberg break; 10746e08d6bbSMika Westerberg default: 10750bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10766e08d6bbSMika Westerberg return -EINVAL; 10776e08d6bbSMika Westerberg } 10786e08d6bbSMika Westerberg 10796e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 10806e08d6bbSMika Westerberg break; 10816e08d6bbSMika Westerberg 10826e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 10836e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10846e08d6bbSMika Westerberg 10856e08d6bbSMika Westerberg switch (arg) { 10866e08d6bbSMika Westerberg case 5000: 10876e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 10886e08d6bbSMika Westerberg break; 10896e08d6bbSMika Westerberg case 20000: 10906e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 10916e08d6bbSMika Westerberg break; 10926e08d6bbSMika Westerberg default: 10930bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10946e08d6bbSMika Westerberg return -EINVAL; 10956e08d6bbSMika Westerberg } 10966e08d6bbSMika Westerberg 10976e08d6bbSMika Westerberg ctrl0 |= pull; 10986e08d6bbSMika Westerberg break; 10996e08d6bbSMika Westerberg 11006e08d6bbSMika Westerberg default: 11010bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11026e08d6bbSMika Westerberg return -EINVAL; 11036e08d6bbSMika Westerberg } 11046e08d6bbSMika Westerberg 11056e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 11060bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11076e08d6bbSMika Westerberg 11086e08d6bbSMika Westerberg return 0; 11096e08d6bbSMika Westerberg } 11106e08d6bbSMika Westerberg 1111ccdf81d0SDan O'Donovan static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1112ccdf81d0SDan O'Donovan bool enable) 1113ccdf81d0SDan O'Donovan { 1114ccdf81d0SDan O'Donovan void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1115ccdf81d0SDan O'Donovan unsigned long flags; 1116ccdf81d0SDan O'Donovan u32 ctrl1; 1117ccdf81d0SDan O'Donovan 1118ccdf81d0SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1119ccdf81d0SDan O'Donovan ctrl1 = readl(reg); 1120ccdf81d0SDan O'Donovan 1121ccdf81d0SDan O'Donovan if (enable) 1122ccdf81d0SDan O'Donovan ctrl1 |= CHV_PADCTRL1_ODEN; 1123ccdf81d0SDan O'Donovan else 1124ccdf81d0SDan O'Donovan ctrl1 &= ~CHV_PADCTRL1_ODEN; 1125ccdf81d0SDan O'Donovan 1126ccdf81d0SDan O'Donovan chv_writel(ctrl1, reg); 1127ccdf81d0SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1128ccdf81d0SDan O'Donovan 1129ccdf81d0SDan O'Donovan return 0; 1130ccdf81d0SDan O'Donovan } 1131ccdf81d0SDan O'Donovan 11326e08d6bbSMika Westerberg static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 11336e08d6bbSMika Westerberg unsigned long *configs, unsigned nconfigs) 11346e08d6bbSMika Westerberg { 11356e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 11366e08d6bbSMika Westerberg enum pin_config_param param; 11376e08d6bbSMika Westerberg int i, ret; 11386e08d6bbSMika Westerberg u16 arg; 11396e08d6bbSMika Westerberg 11406e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, pin)) 11416e08d6bbSMika Westerberg return -EBUSY; 11426e08d6bbSMika Westerberg 11436e08d6bbSMika Westerberg for (i = 0; i < nconfigs; i++) { 11446e08d6bbSMika Westerberg param = pinconf_to_config_param(configs[i]); 11456e08d6bbSMika Westerberg arg = pinconf_to_config_argument(configs[i]); 11466e08d6bbSMika Westerberg 11476e08d6bbSMika Westerberg switch (param) { 11486e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 11496e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 11506e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 11516e08d6bbSMika Westerberg ret = chv_config_set_pull(pctrl, pin, param, arg); 11526e08d6bbSMika Westerberg if (ret) 11536e08d6bbSMika Westerberg return ret; 11546e08d6bbSMika Westerberg break; 11556e08d6bbSMika Westerberg 1156ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_PUSH_PULL: 1157ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, false); 1158ccdf81d0SDan O'Donovan if (ret) 1159ccdf81d0SDan O'Donovan return ret; 1160ccdf81d0SDan O'Donovan break; 1161ccdf81d0SDan O'Donovan 1162ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1163ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, true); 1164ccdf81d0SDan O'Donovan if (ret) 1165ccdf81d0SDan O'Donovan return ret; 1166ccdf81d0SDan O'Donovan break; 1167ccdf81d0SDan O'Donovan 11686e08d6bbSMika Westerberg default: 11696e08d6bbSMika Westerberg return -ENOTSUPP; 11706e08d6bbSMika Westerberg } 11716e08d6bbSMika Westerberg 11726e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 11736e08d6bbSMika Westerberg param, arg); 11746e08d6bbSMika Westerberg } 11756e08d6bbSMika Westerberg 11766e08d6bbSMika Westerberg return 0; 11776e08d6bbSMika Westerberg } 11786e08d6bbSMika Westerberg 117977401d7fSDan O'Donovan static int chv_config_group_get(struct pinctrl_dev *pctldev, 118077401d7fSDan O'Donovan unsigned int group, 118177401d7fSDan O'Donovan unsigned long *config) 118277401d7fSDan O'Donovan { 118377401d7fSDan O'Donovan const unsigned int *pins; 118477401d7fSDan O'Donovan unsigned int npins; 118577401d7fSDan O'Donovan int ret; 118677401d7fSDan O'Donovan 118777401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 118877401d7fSDan O'Donovan if (ret) 118977401d7fSDan O'Donovan return ret; 119077401d7fSDan O'Donovan 119177401d7fSDan O'Donovan ret = chv_config_get(pctldev, pins[0], config); 119277401d7fSDan O'Donovan if (ret) 119377401d7fSDan O'Donovan return ret; 119477401d7fSDan O'Donovan 119577401d7fSDan O'Donovan return 0; 119677401d7fSDan O'Donovan } 119777401d7fSDan O'Donovan 119877401d7fSDan O'Donovan static int chv_config_group_set(struct pinctrl_dev *pctldev, 119977401d7fSDan O'Donovan unsigned int group, unsigned long *configs, 120077401d7fSDan O'Donovan unsigned int num_configs) 120177401d7fSDan O'Donovan { 120277401d7fSDan O'Donovan const unsigned int *pins; 120377401d7fSDan O'Donovan unsigned int npins; 120477401d7fSDan O'Donovan int i, ret; 120577401d7fSDan O'Donovan 120677401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 120777401d7fSDan O'Donovan if (ret) 120877401d7fSDan O'Donovan return ret; 120977401d7fSDan O'Donovan 121077401d7fSDan O'Donovan for (i = 0; i < npins; i++) { 121177401d7fSDan O'Donovan ret = chv_config_set(pctldev, pins[i], configs, num_configs); 121277401d7fSDan O'Donovan if (ret) 121377401d7fSDan O'Donovan return ret; 121477401d7fSDan O'Donovan } 121577401d7fSDan O'Donovan 121677401d7fSDan O'Donovan return 0; 121777401d7fSDan O'Donovan } 121877401d7fSDan O'Donovan 12196e08d6bbSMika Westerberg static const struct pinconf_ops chv_pinconf_ops = { 12206e08d6bbSMika Westerberg .is_generic = true, 12216e08d6bbSMika Westerberg .pin_config_set = chv_config_set, 12226e08d6bbSMika Westerberg .pin_config_get = chv_config_get, 122377401d7fSDan O'Donovan .pin_config_group_get = chv_config_group_get, 122477401d7fSDan O'Donovan .pin_config_group_set = chv_config_group_set, 12256e08d6bbSMika Westerberg }; 12266e08d6bbSMika Westerberg 12276e08d6bbSMika Westerberg static struct pinctrl_desc chv_pinctrl_desc = { 12286e08d6bbSMika Westerberg .pctlops = &chv_pinctrl_ops, 12296e08d6bbSMika Westerberg .pmxops = &chv_pinmux_ops, 12306e08d6bbSMika Westerberg .confops = &chv_pinconf_ops, 12316e08d6bbSMika Westerberg .owner = THIS_MODULE, 12326e08d6bbSMika Westerberg }; 12336e08d6bbSMika Westerberg 12346e08d6bbSMika Westerberg static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, 12356e08d6bbSMika Westerberg unsigned offset) 12366e08d6bbSMika Westerberg { 12376e08d6bbSMika Westerberg return pctrl->community->pins[offset].number; 12386e08d6bbSMika Westerberg } 12396e08d6bbSMika Westerberg 12406e08d6bbSMika Westerberg static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 12416e08d6bbSMika Westerberg { 12420587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12436e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 12444585b000SMika Westerberg unsigned long flags; 12456e08d6bbSMika Westerberg u32 ctrl0, cfg; 12466e08d6bbSMika Westerberg 12470bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12486e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 12490bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12506e08d6bbSMika Westerberg 12516e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 12526e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 12536e08d6bbSMika Westerberg 12546e08d6bbSMika Westerberg if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 12556e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 12566e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 12576e08d6bbSMika Westerberg } 12586e08d6bbSMika Westerberg 12596e08d6bbSMika Westerberg static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 12606e08d6bbSMika Westerberg { 12610587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12626e08d6bbSMika Westerberg unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 12636e08d6bbSMika Westerberg unsigned long flags; 12646e08d6bbSMika Westerberg void __iomem *reg; 12656e08d6bbSMika Westerberg u32 ctrl0; 12666e08d6bbSMika Westerberg 12670bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12686e08d6bbSMika Westerberg 12696e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 12706e08d6bbSMika Westerberg ctrl0 = readl(reg); 12716e08d6bbSMika Westerberg 12726e08d6bbSMika Westerberg if (value) 12736e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 12746e08d6bbSMika Westerberg else 12756e08d6bbSMika Westerberg ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 12766e08d6bbSMika Westerberg 12776e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 12786e08d6bbSMika Westerberg 12790bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12806e08d6bbSMika Westerberg } 12816e08d6bbSMika Westerberg 12826e08d6bbSMika Westerberg static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 12836e08d6bbSMika Westerberg { 12840587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12856e08d6bbSMika Westerberg unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 12866e08d6bbSMika Westerberg u32 ctrl0, direction; 12874585b000SMika Westerberg unsigned long flags; 12886e08d6bbSMika Westerberg 12890bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12906e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 12910bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12926e08d6bbSMika Westerberg 12936e08d6bbSMika Westerberg direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 12946e08d6bbSMika Westerberg direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 12956e08d6bbSMika Westerberg 12966e08d6bbSMika Westerberg return direction != CHV_PADCTRL0_GPIOCFG_GPO; 12976e08d6bbSMika Westerberg } 12986e08d6bbSMika Westerberg 12996e08d6bbSMika Westerberg static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 13006e08d6bbSMika Westerberg { 13016e08d6bbSMika Westerberg return pinctrl_gpio_direction_input(chip->base + offset); 13026e08d6bbSMika Westerberg } 13036e08d6bbSMika Westerberg 13046e08d6bbSMika Westerberg static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 13056e08d6bbSMika Westerberg int value) 13066e08d6bbSMika Westerberg { 1307549e783fSqipeng.zha chv_gpio_set(chip, offset, value); 13086e08d6bbSMika Westerberg return pinctrl_gpio_direction_output(chip->base + offset); 13096e08d6bbSMika Westerberg } 13106e08d6bbSMika Westerberg 13116e08d6bbSMika Westerberg static const struct gpio_chip chv_gpio_chip = { 13126e08d6bbSMika Westerberg .owner = THIS_MODULE, 131398c85d58SJonas Gorski .request = gpiochip_generic_request, 131498c85d58SJonas Gorski .free = gpiochip_generic_free, 13156e08d6bbSMika Westerberg .get_direction = chv_gpio_get_direction, 13166e08d6bbSMika Westerberg .direction_input = chv_gpio_direction_input, 13176e08d6bbSMika Westerberg .direction_output = chv_gpio_direction_output, 13186e08d6bbSMika Westerberg .get = chv_gpio_get, 13196e08d6bbSMika Westerberg .set = chv_gpio_set, 13206e08d6bbSMika Westerberg }; 13216e08d6bbSMika Westerberg 13226e08d6bbSMika Westerberg static void chv_gpio_irq_ack(struct irq_data *d) 13236e08d6bbSMika Westerberg { 13246e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13250587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 13266e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 13276e08d6bbSMika Westerberg u32 intr_line; 13286e08d6bbSMika Westerberg 13290bd50d71SDan O'Donovan raw_spin_lock(&chv_lock); 13306e08d6bbSMika Westerberg 13316e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13326e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13336e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13346e08d6bbSMika Westerberg chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 13356e08d6bbSMika Westerberg 13360bd50d71SDan O'Donovan raw_spin_unlock(&chv_lock); 13376e08d6bbSMika Westerberg } 13386e08d6bbSMika Westerberg 13396e08d6bbSMika Westerberg static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 13406e08d6bbSMika Westerberg { 13416e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13420587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 13436e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 13446e08d6bbSMika Westerberg u32 value, intr_line; 13456e08d6bbSMika Westerberg unsigned long flags; 13466e08d6bbSMika Westerberg 13470bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 13486e08d6bbSMika Westerberg 13496e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13506e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13516e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13526e08d6bbSMika Westerberg 13536e08d6bbSMika Westerberg value = readl(pctrl->regs + CHV_INTMASK); 13546e08d6bbSMika Westerberg if (mask) 13556e08d6bbSMika Westerberg value &= ~BIT(intr_line); 13566e08d6bbSMika Westerberg else 13576e08d6bbSMika Westerberg value |= BIT(intr_line); 13586e08d6bbSMika Westerberg chv_writel(value, pctrl->regs + CHV_INTMASK); 13596e08d6bbSMika Westerberg 13600bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 13616e08d6bbSMika Westerberg } 13626e08d6bbSMika Westerberg 13636e08d6bbSMika Westerberg static void chv_gpio_irq_mask(struct irq_data *d) 13646e08d6bbSMika Westerberg { 13656e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, true); 13666e08d6bbSMika Westerberg } 13676e08d6bbSMika Westerberg 13686e08d6bbSMika Westerberg static void chv_gpio_irq_unmask(struct irq_data *d) 13696e08d6bbSMika Westerberg { 13706e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, false); 13716e08d6bbSMika Westerberg } 13726e08d6bbSMika Westerberg 1373e6c906deSMika Westerberg static unsigned chv_gpio_irq_startup(struct irq_data *d) 1374e6c906deSMika Westerberg { 1375e6c906deSMika Westerberg /* 1376e6c906deSMika Westerberg * Check if the interrupt has been requested with 0 as triggering 1377e6c906deSMika Westerberg * type. In that case it is assumed that the current values 1378e6c906deSMika Westerberg * programmed to the hardware are used (e.g BIOS configured 1379e6c906deSMika Westerberg * defaults). 1380e6c906deSMika Westerberg * 1381e6c906deSMika Westerberg * In that case ->irq_set_type() will never be called so we need to 1382e6c906deSMika Westerberg * read back the values from hardware now, set correct flow handler 1383e6c906deSMika Westerberg * and update mappings before the interrupt is being used. 1384e6c906deSMika Westerberg */ 1385e6c906deSMika Westerberg if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1386e6c906deSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13870587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1388e6c906deSMika Westerberg unsigned offset = irqd_to_hwirq(d); 1389e6c906deSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 1390e6c906deSMika Westerberg irq_flow_handler_t handler; 1391e6c906deSMika Westerberg unsigned long flags; 1392e6c906deSMika Westerberg u32 intsel, value; 1393e6c906deSMika Westerberg 13940bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1395e6c906deSMika Westerberg intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1396e6c906deSMika Westerberg intsel &= CHV_PADCTRL0_INTSEL_MASK; 1397e6c906deSMika Westerberg intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1398e6c906deSMika Westerberg 1399e6c906deSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1400e6c906deSMika Westerberg if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1401e6c906deSMika Westerberg handler = handle_level_irq; 1402e6c906deSMika Westerberg else 1403e6c906deSMika Westerberg handler = handle_edge_irq; 1404e6c906deSMika Westerberg 1405e6c906deSMika Westerberg if (!pctrl->intr_lines[intsel]) { 1406a4e3f783SThomas Gleixner irq_set_handler_locked(d, handler); 1407e6c906deSMika Westerberg pctrl->intr_lines[intsel] = offset; 1408e6c906deSMika Westerberg } 14090bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1410e6c906deSMika Westerberg } 1411e6c906deSMika Westerberg 1412e6c906deSMika Westerberg chv_gpio_irq_unmask(d); 1413e6c906deSMika Westerberg return 0; 1414e6c906deSMika Westerberg } 1415e6c906deSMika Westerberg 14166e08d6bbSMika Westerberg static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 14176e08d6bbSMika Westerberg { 14186e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 14190587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 14206e08d6bbSMika Westerberg unsigned offset = irqd_to_hwirq(d); 14216e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 14226e08d6bbSMika Westerberg unsigned long flags; 14236e08d6bbSMika Westerberg u32 value; 14246e08d6bbSMika Westerberg 14250bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 14266e08d6bbSMika Westerberg 14276e08d6bbSMika Westerberg /* 14286e08d6bbSMika Westerberg * Pins which can be used as shared interrupt are configured in 14296e08d6bbSMika Westerberg * BIOS. Driver trusts BIOS configurations and assigns different 14306e08d6bbSMika Westerberg * handler according to the irq type. 14316e08d6bbSMika Westerberg * 14326e08d6bbSMika Westerberg * Driver needs to save the mapping between each pin and 14336e08d6bbSMika Westerberg * its interrupt line. 14346e08d6bbSMika Westerberg * 1. If the pin cfg is locked in BIOS: 14356e08d6bbSMika Westerberg * Trust BIOS has programmed IntWakeCfg bits correctly, 14366e08d6bbSMika Westerberg * driver just needs to save the mapping. 14376e08d6bbSMika Westerberg * 2. If the pin cfg is not locked in BIOS: 14386e08d6bbSMika Westerberg * Driver programs the IntWakeCfg bits and save the mapping. 14396e08d6bbSMika Westerberg */ 14406e08d6bbSMika Westerberg if (!chv_pad_locked(pctrl, pin)) { 14416e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 14426e08d6bbSMika Westerberg 14436e08d6bbSMika Westerberg value = readl(reg); 14446e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 14456e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 14466e08d6bbSMika Westerberg 14476e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) { 14486e08d6bbSMika Westerberg if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 14496e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 14506e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_RISING) 14516e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_RISING; 14526e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_FALLING) 14536e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 14546e08d6bbSMika Westerberg } else if (type & IRQ_TYPE_LEVEL_MASK) { 14556e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 14566e08d6bbSMika Westerberg if (type & IRQ_TYPE_LEVEL_LOW) 14576e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_RXDATA; 14586e08d6bbSMika Westerberg } 14596e08d6bbSMika Westerberg 14606e08d6bbSMika Westerberg chv_writel(value, reg); 14616e08d6bbSMika Westerberg } 14626e08d6bbSMika Westerberg 14636e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 14646e08d6bbSMika Westerberg value &= CHV_PADCTRL0_INTSEL_MASK; 14656e08d6bbSMika Westerberg value >>= CHV_PADCTRL0_INTSEL_SHIFT; 14666e08d6bbSMika Westerberg 14676e08d6bbSMika Westerberg pctrl->intr_lines[value] = offset; 14686e08d6bbSMika Westerberg 14696e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) 1470a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 14716e08d6bbSMika Westerberg else if (type & IRQ_TYPE_LEVEL_MASK) 1472a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 14736e08d6bbSMika Westerberg 14740bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 14756e08d6bbSMika Westerberg 14766e08d6bbSMika Westerberg return 0; 14776e08d6bbSMika Westerberg } 14786e08d6bbSMika Westerberg 14796e08d6bbSMika Westerberg static struct irq_chip chv_gpio_irqchip = { 14806e08d6bbSMika Westerberg .name = "chv-gpio", 1481e6c906deSMika Westerberg .irq_startup = chv_gpio_irq_startup, 14826e08d6bbSMika Westerberg .irq_ack = chv_gpio_irq_ack, 14836e08d6bbSMika Westerberg .irq_mask = chv_gpio_irq_mask, 14846e08d6bbSMika Westerberg .irq_unmask = chv_gpio_irq_unmask, 14856e08d6bbSMika Westerberg .irq_set_type = chv_gpio_irq_type, 14866e08d6bbSMika Westerberg .flags = IRQCHIP_SKIP_SET_WAKE, 14876e08d6bbSMika Westerberg }; 14886e08d6bbSMika Westerberg 1489bd0b9ac4SThomas Gleixner static void chv_gpio_irq_handler(struct irq_desc *desc) 14906e08d6bbSMika Westerberg { 14916e08d6bbSMika Westerberg struct gpio_chip *gc = irq_desc_get_handler_data(desc); 14920587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 14935663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 14946e08d6bbSMika Westerberg unsigned long pending; 14956e08d6bbSMika Westerberg u32 intr_line; 14966e08d6bbSMika Westerberg 14976e08d6bbSMika Westerberg chained_irq_enter(chip, desc); 14986e08d6bbSMika Westerberg 14996e08d6bbSMika Westerberg pending = readl(pctrl->regs + CHV_INTSTAT); 15006e08d6bbSMika Westerberg for_each_set_bit(intr_line, &pending, 16) { 15016e08d6bbSMika Westerberg unsigned irq, offset; 15026e08d6bbSMika Westerberg 15036e08d6bbSMika Westerberg offset = pctrl->intr_lines[intr_line]; 15046e08d6bbSMika Westerberg irq = irq_find_mapping(gc->irqdomain, offset); 15056e08d6bbSMika Westerberg generic_handle_irq(irq); 15066e08d6bbSMika Westerberg } 15076e08d6bbSMika Westerberg 15086e08d6bbSMika Westerberg chained_irq_exit(chip, desc); 15096e08d6bbSMika Westerberg } 15106e08d6bbSMika Westerberg 15116e08d6bbSMika Westerberg static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 15126e08d6bbSMika Westerberg { 15136e08d6bbSMika Westerberg const struct chv_gpio_pinrange *range; 15146e08d6bbSMika Westerberg struct gpio_chip *chip = &pctrl->chip; 15156e08d6bbSMika Westerberg int ret, i, offset; 15166e08d6bbSMika Westerberg 15176e08d6bbSMika Westerberg *chip = chv_gpio_chip; 15186e08d6bbSMika Westerberg 15196e08d6bbSMika Westerberg chip->ngpio = pctrl->community->ngpios; 15206e08d6bbSMika Westerberg chip->label = dev_name(pctrl->dev); 152158383c78SLinus Walleij chip->parent = pctrl->dev; 15226e08d6bbSMika Westerberg chip->base = -1; 15236e08d6bbSMika Westerberg 15240587d3dbSLinus Walleij ret = gpiochip_add_data(chip, pctrl); 15256e08d6bbSMika Westerberg if (ret) { 15266e08d6bbSMika Westerberg dev_err(pctrl->dev, "Failed to register gpiochip\n"); 15276e08d6bbSMika Westerberg return ret; 15286e08d6bbSMika Westerberg } 15296e08d6bbSMika Westerberg 15306e08d6bbSMika Westerberg for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { 15316e08d6bbSMika Westerberg range = &pctrl->community->gpio_ranges[i]; 15326e08d6bbSMika Westerberg ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, 15336e08d6bbSMika Westerberg range->base, range->npins); 15346e08d6bbSMika Westerberg if (ret) { 15356e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 15366e08d6bbSMika Westerberg goto fail; 15376e08d6bbSMika Westerberg } 15386e08d6bbSMika Westerberg 15396e08d6bbSMika Westerberg offset += range->npins; 15406e08d6bbSMika Westerberg } 15416e08d6bbSMika Westerberg 1542bcb48ccaSMika Westerberg /* Clear all interrupts */ 15436e08d6bbSMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 15446e08d6bbSMika Westerberg 15456e08d6bbSMika Westerberg ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1546bcb48ccaSMika Westerberg handle_bad_irq, IRQ_TYPE_NONE); 15476e08d6bbSMika Westerberg if (ret) { 15486e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add IRQ chip\n"); 15496e08d6bbSMika Westerberg goto fail; 15506e08d6bbSMika Westerberg } 15516e08d6bbSMika Westerberg 15526e08d6bbSMika Westerberg gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 15536e08d6bbSMika Westerberg chv_gpio_irq_handler); 15546e08d6bbSMika Westerberg return 0; 15556e08d6bbSMika Westerberg 15566e08d6bbSMika Westerberg fail: 15576e08d6bbSMika Westerberg gpiochip_remove(chip); 15586e08d6bbSMika Westerberg 15596e08d6bbSMika Westerberg return ret; 15606e08d6bbSMika Westerberg } 15616e08d6bbSMika Westerberg 15626e08d6bbSMika Westerberg static int chv_pinctrl_probe(struct platform_device *pdev) 15636e08d6bbSMika Westerberg { 15646e08d6bbSMika Westerberg struct chv_pinctrl *pctrl; 15656e08d6bbSMika Westerberg struct acpi_device *adev; 15666e08d6bbSMika Westerberg struct resource *res; 15676e08d6bbSMika Westerberg int ret, irq, i; 15686e08d6bbSMika Westerberg 15696e08d6bbSMika Westerberg adev = ACPI_COMPANION(&pdev->dev); 15706e08d6bbSMika Westerberg if (!adev) 15716e08d6bbSMika Westerberg return -ENODEV; 15726e08d6bbSMika Westerberg 15736e08d6bbSMika Westerberg pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 15746e08d6bbSMika Westerberg if (!pctrl) 15756e08d6bbSMika Westerberg return -ENOMEM; 15766e08d6bbSMika Westerberg 15776e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 15786e08d6bbSMika Westerberg if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 15796e08d6bbSMika Westerberg pctrl->community = chv_communities[i]; 15806e08d6bbSMika Westerberg break; 15816e08d6bbSMika Westerberg } 15826e08d6bbSMika Westerberg if (i == ARRAY_SIZE(chv_communities)) 15836e08d6bbSMika Westerberg return -ENODEV; 15846e08d6bbSMika Westerberg 15856e08d6bbSMika Westerberg pctrl->dev = &pdev->dev; 15866e08d6bbSMika Westerberg 15879eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 15889eb457b5SMika Westerberg pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 15899eb457b5SMika Westerberg pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 15909eb457b5SMika Westerberg GFP_KERNEL); 15919eb457b5SMika Westerberg if (!pctrl->saved_pin_context) 15929eb457b5SMika Westerberg return -ENOMEM; 15939eb457b5SMika Westerberg #endif 15949eb457b5SMika Westerberg 15956e08d6bbSMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 15966e08d6bbSMika Westerberg pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 15976e08d6bbSMika Westerberg if (IS_ERR(pctrl->regs)) 15986e08d6bbSMika Westerberg return PTR_ERR(pctrl->regs); 15996e08d6bbSMika Westerberg 16006e08d6bbSMika Westerberg irq = platform_get_irq(pdev, 0); 16016e08d6bbSMika Westerberg if (irq < 0) { 16026e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to get interrupt number\n"); 16036e08d6bbSMika Westerberg return irq; 16046e08d6bbSMika Westerberg } 16056e08d6bbSMika Westerberg 16066e08d6bbSMika Westerberg pctrl->pctldesc = chv_pinctrl_desc; 16076e08d6bbSMika Westerberg pctrl->pctldesc.name = dev_name(&pdev->dev); 16086e08d6bbSMika Westerberg pctrl->pctldesc.pins = pctrl->community->pins; 16096e08d6bbSMika Westerberg pctrl->pctldesc.npins = pctrl->community->npins; 16106e08d6bbSMika Westerberg 16117cf061faSLaxman Dewangan pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 16127cf061faSLaxman Dewangan pctrl); 1613323de9efSMasahiro Yamada if (IS_ERR(pctrl->pctldev)) { 16146e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1615323de9efSMasahiro Yamada return PTR_ERR(pctrl->pctldev); 16166e08d6bbSMika Westerberg } 16176e08d6bbSMika Westerberg 16186e08d6bbSMika Westerberg ret = chv_gpio_probe(pctrl, irq); 16197cf061faSLaxman Dewangan if (ret) 16206e08d6bbSMika Westerberg return ret; 16216e08d6bbSMika Westerberg 16226e08d6bbSMika Westerberg platform_set_drvdata(pdev, pctrl); 16236e08d6bbSMika Westerberg 16246e08d6bbSMika Westerberg return 0; 16256e08d6bbSMika Westerberg } 16266e08d6bbSMika Westerberg 16276e08d6bbSMika Westerberg static int chv_pinctrl_remove(struct platform_device *pdev) 16286e08d6bbSMika Westerberg { 16296e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 16306e08d6bbSMika Westerberg 16316e08d6bbSMika Westerberg gpiochip_remove(&pctrl->chip); 16326e08d6bbSMika Westerberg 16336e08d6bbSMika Westerberg return 0; 16346e08d6bbSMika Westerberg } 16356e08d6bbSMika Westerberg 16369eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 16379eb457b5SMika Westerberg static int chv_pinctrl_suspend(struct device *dev) 16389eb457b5SMika Westerberg { 16399eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 16409eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 16419eb457b5SMika Westerberg int i; 16429eb457b5SMika Westerberg 16439eb457b5SMika Westerberg pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 16449eb457b5SMika Westerberg 16459eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 16469eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 16479eb457b5SMika Westerberg struct chv_pin_context *ctx; 16489eb457b5SMika Westerberg void __iomem *reg; 16499eb457b5SMika Westerberg 16509eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 16519eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 16529eb457b5SMika Westerberg continue; 16539eb457b5SMika Westerberg 16549eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 16559eb457b5SMika Westerberg 16569eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 16579eb457b5SMika Westerberg ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 16589eb457b5SMika Westerberg 16599eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 16609eb457b5SMika Westerberg ctx->padctrl1 = readl(reg); 16619eb457b5SMika Westerberg } 16629eb457b5SMika Westerberg 16639eb457b5SMika Westerberg return 0; 16649eb457b5SMika Westerberg } 16659eb457b5SMika Westerberg 16669eb457b5SMika Westerberg static int chv_pinctrl_resume(struct device *dev) 16679eb457b5SMika Westerberg { 16689eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 16699eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 16709eb457b5SMika Westerberg int i; 16719eb457b5SMika Westerberg 16729eb457b5SMika Westerberg /* 16739eb457b5SMika Westerberg * Mask all interrupts before restoring per-pin configuration 16749eb457b5SMika Westerberg * registers because we don't know in which state BIOS left them 16759eb457b5SMika Westerberg * upon exiting suspend. 16769eb457b5SMika Westerberg */ 16779eb457b5SMika Westerberg chv_writel(0, pctrl->regs + CHV_INTMASK); 16789eb457b5SMika Westerberg 16799eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 16809eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 16819eb457b5SMika Westerberg const struct chv_pin_context *ctx; 16829eb457b5SMika Westerberg void __iomem *reg; 16839eb457b5SMika Westerberg u32 val; 16849eb457b5SMika Westerberg 16859eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 16869eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 16879eb457b5SMika Westerberg continue; 16889eb457b5SMika Westerberg 16899eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 16909eb457b5SMika Westerberg 16919eb457b5SMika Westerberg /* Only restore if our saved state differs from the current */ 16929eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 16939eb457b5SMika Westerberg val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 16949eb457b5SMika Westerberg if (ctx->padctrl0 != val) { 16959eb457b5SMika Westerberg chv_writel(ctx->padctrl0, reg); 16969eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 16979eb457b5SMika Westerberg desc->number, readl(reg)); 16989eb457b5SMika Westerberg } 16999eb457b5SMika Westerberg 17009eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 17019eb457b5SMika Westerberg val = readl(reg); 17029eb457b5SMika Westerberg if (ctx->padctrl1 != val) { 17039eb457b5SMika Westerberg chv_writel(ctx->padctrl1, reg); 17049eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 17059eb457b5SMika Westerberg desc->number, readl(reg)); 17069eb457b5SMika Westerberg } 17079eb457b5SMika Westerberg } 17089eb457b5SMika Westerberg 17099eb457b5SMika Westerberg /* 17109eb457b5SMika Westerberg * Now that all pins are restored to known state, we can restore 17119eb457b5SMika Westerberg * the interrupt mask register as well. 17129eb457b5SMika Westerberg */ 17139eb457b5SMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 17149eb457b5SMika Westerberg chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 17159eb457b5SMika Westerberg 17169eb457b5SMika Westerberg return 0; 17179eb457b5SMika Westerberg } 17189eb457b5SMika Westerberg #endif 17199eb457b5SMika Westerberg 17209eb457b5SMika Westerberg static const struct dev_pm_ops chv_pinctrl_pm_ops = { 17219eb457b5SMika Westerberg SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) 17229eb457b5SMika Westerberg }; 17239eb457b5SMika Westerberg 17246e08d6bbSMika Westerberg static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 17256e08d6bbSMika Westerberg { "INT33FF" }, 17266e08d6bbSMika Westerberg { } 17276e08d6bbSMika Westerberg }; 17286e08d6bbSMika Westerberg MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 17296e08d6bbSMika Westerberg 17306e08d6bbSMika Westerberg static struct platform_driver chv_pinctrl_driver = { 17316e08d6bbSMika Westerberg .probe = chv_pinctrl_probe, 17326e08d6bbSMika Westerberg .remove = chv_pinctrl_remove, 17336e08d6bbSMika Westerberg .driver = { 17346e08d6bbSMika Westerberg .name = "cherryview-pinctrl", 17359eb457b5SMika Westerberg .pm = &chv_pinctrl_pm_ops, 17366e08d6bbSMika Westerberg .acpi_match_table = chv_pinctrl_acpi_match, 17376e08d6bbSMika Westerberg }, 17386e08d6bbSMika Westerberg }; 17396e08d6bbSMika Westerberg 17406e08d6bbSMika Westerberg static int __init chv_pinctrl_init(void) 17416e08d6bbSMika Westerberg { 17426e08d6bbSMika Westerberg return platform_driver_register(&chv_pinctrl_driver); 17436e08d6bbSMika Westerberg } 17446e08d6bbSMika Westerberg subsys_initcall(chv_pinctrl_init); 17456e08d6bbSMika Westerberg 17466e08d6bbSMika Westerberg static void __exit chv_pinctrl_exit(void) 17476e08d6bbSMika Westerberg { 17486e08d6bbSMika Westerberg platform_driver_unregister(&chv_pinctrl_driver); 17496e08d6bbSMika Westerberg } 17506e08d6bbSMika Westerberg module_exit(chv_pinctrl_exit); 17516e08d6bbSMika Westerberg 17526e08d6bbSMika Westerberg MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 17536e08d6bbSMika Westerberg MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 17546e08d6bbSMika Westerberg MODULE_LICENSE("GPL v2"); 1755