1875a92b3SAndy Shevchenko // SPDX-License-Identifier: GPL-2.0 26e08d6bbSMika Westerberg /* 36e08d6bbSMika Westerberg * Cherryview/Braswell pinctrl driver 46e08d6bbSMika Westerberg * 56e08d6bbSMika Westerberg * Copyright (C) 2014, Intel Corporation 66e08d6bbSMika Westerberg * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 76e08d6bbSMika Westerberg * 86e08d6bbSMika Westerberg * This driver is based on the original Cherryview GPIO driver by 96e08d6bbSMika Westerberg * Ning Li <ning.li@intel.com> 106e08d6bbSMika Westerberg * Alan Cox <alan@linux.intel.com> 116e08d6bbSMika Westerberg */ 126e08d6bbSMika Westerberg 13994f8865SAndy Shevchenko #include <linux/acpi.h> 1470365027SMika Westerberg #include <linux/dmi.h> 15994f8865SAndy Shevchenko #include <linux/gpio/driver.h> 166e08d6bbSMika Westerberg #include <linux/kernel.h> 176e08d6bbSMika Westerberg #include <linux/module.h> 18994f8865SAndy Shevchenko #include <linux/platform_device.h> 196e08d6bbSMika Westerberg #include <linux/types.h> 20994f8865SAndy Shevchenko 216e08d6bbSMika Westerberg #include <linux/pinctrl/pinctrl.h> 226e08d6bbSMika Westerberg #include <linux/pinctrl/pinmux.h> 236e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf.h> 246e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf-generic.h> 256e08d6bbSMika Westerberg 265458b7ceSAndy Shevchenko #include "pinctrl-intel.h" 275458b7ceSAndy Shevchenko 286e08d6bbSMika Westerberg #define CHV_INTSTAT 0x300 296e08d6bbSMika Westerberg #define CHV_INTMASK 0x380 306e08d6bbSMika Westerberg 316e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_OFF 0x4400 326e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_SIZE 0x400 336e08d6bbSMika Westerberg #define MAX_FAMILY_PAD_GPIO_NO 15 346e08d6bbSMika Westerberg #define GPIO_REGS_SIZE 8 356e08d6bbSMika Westerberg 366e08d6bbSMika Westerberg #define CHV_PADCTRL0 0x000 376e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_SHIFT 28 386e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 396e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_UP BIT(23) 406e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_SHIFT 20 416e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 426e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_20K 1 436e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_5K 2 446e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_1K 4 456e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_SHIFT 16 466e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 476e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOEN BIT(15) 486e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 496e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 506e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPIO 0 516e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPO 1 526e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPI 2 536e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_HIZ 3 546e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 556e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 566e08d6bbSMika Westerberg 576e08d6bbSMika Westerberg #define CHV_PADCTRL1 0x004 586e08d6bbSMika Westerberg #define CHV_PADCTRL1_CFGLOCK BIT(31) 596e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_SHIFT 4 606e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 616e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 626e08d6bbSMika Westerberg #define CHV_PADCTRL1_ODEN BIT(3) 636e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 646e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_MASK 7 656e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 666e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_RISING 2 676e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 686e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 696e08d6bbSMika Westerberg 706e08d6bbSMika Westerberg /** 716e08d6bbSMika Westerberg * struct chv_alternate_function - A per group or per pin alternate function 726e08d6bbSMika Westerberg * @pin: Pin number (only used in per pin configs) 736e08d6bbSMika Westerberg * @mode: Mode the pin should be set in 746e08d6bbSMika Westerberg * @invert_oe: Invert OE for this pin 756e08d6bbSMika Westerberg */ 766e08d6bbSMika Westerberg struct chv_alternate_function { 776e08d6bbSMika Westerberg unsigned pin; 786e08d6bbSMika Westerberg u8 mode; 796e08d6bbSMika Westerberg bool invert_oe; 806e08d6bbSMika Westerberg }; 816e08d6bbSMika Westerberg 826e08d6bbSMika Westerberg /** 836e08d6bbSMika Westerberg * struct chv_pincgroup - describes a CHV pin group 846e08d6bbSMika Westerberg * @name: Name of the group 856e08d6bbSMika Westerberg * @pins: An array of pins in this group 866e08d6bbSMika Westerberg * @npins: Number of pins in this group 876e08d6bbSMika Westerberg * @altfunc: Alternate function applied to all pins in this group 886e08d6bbSMika Westerberg * @overrides: Alternate function override per pin or %NULL if not used 896e08d6bbSMika Westerberg * @noverrides: Number of per pin alternate function overrides if 906e08d6bbSMika Westerberg * @overrides != NULL. 916e08d6bbSMika Westerberg */ 926e08d6bbSMika Westerberg struct chv_pingroup { 936e08d6bbSMika Westerberg const char *name; 946e08d6bbSMika Westerberg const unsigned *pins; 956e08d6bbSMika Westerberg size_t npins; 966e08d6bbSMika Westerberg struct chv_alternate_function altfunc; 976e08d6bbSMika Westerberg const struct chv_alternate_function *overrides; 986e08d6bbSMika Westerberg size_t noverrides; 996e08d6bbSMika Westerberg }; 1006e08d6bbSMika Westerberg 1016e08d6bbSMika Westerberg /** 1026e08d6bbSMika Westerberg * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 1036e08d6bbSMika Westerberg * @base: Start pin number 1046e08d6bbSMika Westerberg * @npins: Number of pins in this range 1056e08d6bbSMika Westerberg */ 1066e08d6bbSMika Westerberg struct chv_gpio_pinrange { 1076e08d6bbSMika Westerberg unsigned base; 1086e08d6bbSMika Westerberg unsigned npins; 1096e08d6bbSMika Westerberg }; 1106e08d6bbSMika Westerberg 1116e08d6bbSMika Westerberg /** 1126e08d6bbSMika Westerberg * struct chv_community - A community specific configuration 1136e08d6bbSMika Westerberg * @uid: ACPI _UID used to match the community 1146e08d6bbSMika Westerberg * @pins: All pins in this community 1156e08d6bbSMika Westerberg * @npins: Number of pins 1166e08d6bbSMika Westerberg * @groups: All groups in this community 1176e08d6bbSMika Westerberg * @ngroups: Number of groups 1186e08d6bbSMika Westerberg * @functions: All functions in this community 1196e08d6bbSMika Westerberg * @nfunctions: Number of functions 1206e08d6bbSMika Westerberg * @gpio_ranges: An array of GPIO ranges in this community 1216e08d6bbSMika Westerberg * @ngpio_ranges: Number of GPIO ranges 12247c950d1SMika Westerberg * @nirqs: Total number of IRQs this community can generate 123a919684fSAndy Shevchenko * @acpi_space_id: An address space ID for ACPI OpRegion handler 1246e08d6bbSMika Westerberg */ 1256e08d6bbSMika Westerberg struct chv_community { 1266e08d6bbSMika Westerberg const char *uid; 1276e08d6bbSMika Westerberg const struct pinctrl_pin_desc *pins; 1286e08d6bbSMika Westerberg size_t npins; 1296e08d6bbSMika Westerberg const struct chv_pingroup *groups; 1306e08d6bbSMika Westerberg size_t ngroups; 1315458b7ceSAndy Shevchenko const struct intel_function *functions; 1326e08d6bbSMika Westerberg size_t nfunctions; 1336e08d6bbSMika Westerberg const struct chv_gpio_pinrange *gpio_ranges; 1346e08d6bbSMika Westerberg size_t ngpio_ranges; 13547c950d1SMika Westerberg size_t nirqs; 136a0b02859SHans de Goede acpi_adr_space_type acpi_space_id; 1376e08d6bbSMika Westerberg }; 1386e08d6bbSMika Westerberg 1399eb457b5SMika Westerberg struct chv_pin_context { 1409eb457b5SMika Westerberg u32 padctrl0; 1419eb457b5SMika Westerberg u32 padctrl1; 1429eb457b5SMika Westerberg }; 1439eb457b5SMika Westerberg 1446e08d6bbSMika Westerberg /** 1456e08d6bbSMika Westerberg * struct chv_pinctrl - CHV pinctrl private structure 1466e08d6bbSMika Westerberg * @dev: Pointer to the parent device 1476e08d6bbSMika Westerberg * @pctldesc: Pin controller description 1486e08d6bbSMika Westerberg * @pctldev: Pointer to the pin controller device 1496e08d6bbSMika Westerberg * @chip: GPIO chip in this pin controller 1506e08d6bbSMika Westerberg * @regs: MMIO registers 1516e08d6bbSMika Westerberg * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 1526e08d6bbSMika Westerberg * offset (in GPIO number space) 1536e08d6bbSMika Westerberg * @community: Community this pinctrl instance represents 154a919684fSAndy Shevchenko * @saved_intmask: Interrupt mask saved for system sleep 155a919684fSAndy Shevchenko * @saved_pin_context: Pointer to a context of the pins saved for system sleep 1566e08d6bbSMika Westerberg * 1576e08d6bbSMika Westerberg * The first group in @groups is expected to contain all pins that can be 1586e08d6bbSMika Westerberg * used as GPIOs. 1596e08d6bbSMika Westerberg */ 1606e08d6bbSMika Westerberg struct chv_pinctrl { 1616e08d6bbSMika Westerberg struct device *dev; 1626e08d6bbSMika Westerberg struct pinctrl_desc pctldesc; 1636e08d6bbSMika Westerberg struct pinctrl_dev *pctldev; 1646e08d6bbSMika Westerberg struct gpio_chip chip; 1656e08d6bbSMika Westerberg void __iomem *regs; 1666e08d6bbSMika Westerberg unsigned intr_lines[16]; 1676e08d6bbSMika Westerberg const struct chv_community *community; 1689eb457b5SMika Westerberg u32 saved_intmask; 1699eb457b5SMika Westerberg struct chv_pin_context *saved_pin_context; 1706e08d6bbSMika Westerberg }; 1716e08d6bbSMika Westerberg 1726e08d6bbSMika Westerberg #define ALTERNATE_FUNCTION(p, m, i) \ 1736e08d6bbSMika Westerberg { \ 1746e08d6bbSMika Westerberg .pin = (p), \ 1756e08d6bbSMika Westerberg .mode = (m), \ 1766e08d6bbSMika Westerberg .invert_oe = (i), \ 1776e08d6bbSMika Westerberg } 1786e08d6bbSMika Westerberg 1795458b7ceSAndy Shevchenko #define PIN_GROUP_WITH_ALT(n, p, m, i) \ 1806e08d6bbSMika Westerberg { \ 1816e08d6bbSMika Westerberg .name = (n), \ 1826e08d6bbSMika Westerberg .pins = (p), \ 1836e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 1846e08d6bbSMika Westerberg .altfunc.mode = (m), \ 1856e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 1866e08d6bbSMika Westerberg } 1876e08d6bbSMika Westerberg 1886e08d6bbSMika Westerberg #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 1896e08d6bbSMika Westerberg { \ 1906e08d6bbSMika Westerberg .name = (n), \ 1916e08d6bbSMika Westerberg .pins = (p), \ 1926e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 1936e08d6bbSMika Westerberg .altfunc.mode = (m), \ 1946e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 1956e08d6bbSMika Westerberg .overrides = (o), \ 1966e08d6bbSMika Westerberg .noverrides = ARRAY_SIZE((o)), \ 1976e08d6bbSMika Westerberg } 1986e08d6bbSMika Westerberg 1996e08d6bbSMika Westerberg #define GPIO_PINRANGE(start, end) \ 2006e08d6bbSMika Westerberg { \ 2016e08d6bbSMika Westerberg .base = (start), \ 2026e08d6bbSMika Westerberg .npins = (end) - (start) + 1, \ 2036e08d6bbSMika Westerberg } 2046e08d6bbSMika Westerberg 2056e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southwest_pins[] = { 2066e08d6bbSMika Westerberg PINCTRL_PIN(0, "FST_SPI_D2"), 2076e08d6bbSMika Westerberg PINCTRL_PIN(1, "FST_SPI_D0"), 2086e08d6bbSMika Westerberg PINCTRL_PIN(2, "FST_SPI_CLK"), 2096e08d6bbSMika Westerberg PINCTRL_PIN(3, "FST_SPI_D3"), 2106e08d6bbSMika Westerberg PINCTRL_PIN(4, "FST_SPI_CS1_B"), 2116e08d6bbSMika Westerberg PINCTRL_PIN(5, "FST_SPI_D1"), 2126e08d6bbSMika Westerberg PINCTRL_PIN(6, "FST_SPI_CS0_B"), 2136e08d6bbSMika Westerberg PINCTRL_PIN(7, "FST_SPI_CS2_B"), 2146e08d6bbSMika Westerberg 2156e08d6bbSMika Westerberg PINCTRL_PIN(15, "UART1_RTS_B"), 2166e08d6bbSMika Westerberg PINCTRL_PIN(16, "UART1_RXD"), 2176e08d6bbSMika Westerberg PINCTRL_PIN(17, "UART2_RXD"), 2186e08d6bbSMika Westerberg PINCTRL_PIN(18, "UART1_CTS_B"), 2196e08d6bbSMika Westerberg PINCTRL_PIN(19, "UART2_RTS_B"), 2206e08d6bbSMika Westerberg PINCTRL_PIN(20, "UART1_TXD"), 2216e08d6bbSMika Westerberg PINCTRL_PIN(21, "UART2_TXD"), 2226e08d6bbSMika Westerberg PINCTRL_PIN(22, "UART2_CTS_B"), 2236e08d6bbSMika Westerberg 2246e08d6bbSMika Westerberg PINCTRL_PIN(30, "MF_HDA_CLK"), 2256e08d6bbSMika Westerberg PINCTRL_PIN(31, "MF_HDA_RSTB"), 2266e08d6bbSMika Westerberg PINCTRL_PIN(32, "MF_HDA_SDIO"), 2276e08d6bbSMika Westerberg PINCTRL_PIN(33, "MF_HDA_SDO"), 2286e08d6bbSMika Westerberg PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 2296e08d6bbSMika Westerberg PINCTRL_PIN(35, "MF_HDA_SYNC"), 2306e08d6bbSMika Westerberg PINCTRL_PIN(36, "MF_HDA_SDI1"), 2316e08d6bbSMika Westerberg PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 2326e08d6bbSMika Westerberg 2336e08d6bbSMika Westerberg PINCTRL_PIN(45, "I2C5_SDA"), 2346e08d6bbSMika Westerberg PINCTRL_PIN(46, "I2C4_SDA"), 2356e08d6bbSMika Westerberg PINCTRL_PIN(47, "I2C6_SDA"), 2366e08d6bbSMika Westerberg PINCTRL_PIN(48, "I2C5_SCL"), 2376e08d6bbSMika Westerberg PINCTRL_PIN(49, "I2C_NFC_SDA"), 2386e08d6bbSMika Westerberg PINCTRL_PIN(50, "I2C4_SCL"), 2396e08d6bbSMika Westerberg PINCTRL_PIN(51, "I2C6_SCL"), 2406e08d6bbSMika Westerberg PINCTRL_PIN(52, "I2C_NFC_SCL"), 2416e08d6bbSMika Westerberg 2426e08d6bbSMika Westerberg PINCTRL_PIN(60, "I2C1_SDA"), 2436e08d6bbSMika Westerberg PINCTRL_PIN(61, "I2C0_SDA"), 2446e08d6bbSMika Westerberg PINCTRL_PIN(62, "I2C2_SDA"), 2456e08d6bbSMika Westerberg PINCTRL_PIN(63, "I2C1_SCL"), 2466e08d6bbSMika Westerberg PINCTRL_PIN(64, "I2C3_SDA"), 2476e08d6bbSMika Westerberg PINCTRL_PIN(65, "I2C0_SCL"), 2486e08d6bbSMika Westerberg PINCTRL_PIN(66, "I2C2_SCL"), 2496e08d6bbSMika Westerberg PINCTRL_PIN(67, "I2C3_SCL"), 2506e08d6bbSMika Westerberg 2516e08d6bbSMika Westerberg PINCTRL_PIN(75, "SATA_GP0"), 2526e08d6bbSMika Westerberg PINCTRL_PIN(76, "SATA_GP1"), 2536e08d6bbSMika Westerberg PINCTRL_PIN(77, "SATA_LEDN"), 2546e08d6bbSMika Westerberg PINCTRL_PIN(78, "SATA_GP2"), 2556e08d6bbSMika Westerberg PINCTRL_PIN(79, "MF_SMB_ALERTB"), 2566e08d6bbSMika Westerberg PINCTRL_PIN(80, "SATA_GP3"), 2576e08d6bbSMika Westerberg PINCTRL_PIN(81, "MF_SMB_CLK"), 2586e08d6bbSMika Westerberg PINCTRL_PIN(82, "MF_SMB_DATA"), 2596e08d6bbSMika Westerberg 2606e08d6bbSMika Westerberg PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 2616e08d6bbSMika Westerberg PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 2626e08d6bbSMika Westerberg PINCTRL_PIN(92, "GP_SSP_2_CLK"), 2636e08d6bbSMika Westerberg PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 2646e08d6bbSMika Westerberg PINCTRL_PIN(94, "GP_SSP_2_RXD"), 2656e08d6bbSMika Westerberg PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 2666e08d6bbSMika Westerberg PINCTRL_PIN(96, "GP_SSP_2_FS"), 2676e08d6bbSMika Westerberg PINCTRL_PIN(97, "GP_SSP_2_TXD"), 2686e08d6bbSMika Westerberg }; 2696e08d6bbSMika Westerberg 2706e08d6bbSMika Westerberg static const unsigned southwest_uart0_pins[] = { 16, 20 }; 2716e08d6bbSMika Westerberg static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 2726e08d6bbSMika Westerberg static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 2736e08d6bbSMika Westerberg static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 2746e08d6bbSMika Westerberg static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 2756e08d6bbSMika Westerberg static const unsigned southwest_lpe_pins[] = { 2766e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 2776e08d6bbSMika Westerberg }; 2786e08d6bbSMika Westerberg static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 2796e08d6bbSMika Westerberg static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 2806e08d6bbSMika Westerberg static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 2816e08d6bbSMika Westerberg static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 2826e08d6bbSMika Westerberg static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 2836e08d6bbSMika Westerberg static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 2846e08d6bbSMika Westerberg static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 2856e08d6bbSMika Westerberg static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 2866e08d6bbSMika Westerberg 2876e08d6bbSMika Westerberg /* LPE I2S TXD pins need to have invert_oe set */ 2886e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 2896e08d6bbSMika Westerberg ALTERNATE_FUNCTION(30, 1, true), 2906e08d6bbSMika Westerberg ALTERNATE_FUNCTION(34, 1, true), 2916e08d6bbSMika Westerberg ALTERNATE_FUNCTION(97, 1, true), 2926e08d6bbSMika Westerberg }; 2936e08d6bbSMika Westerberg 2946e08d6bbSMika Westerberg /* 2956e08d6bbSMika Westerberg * Two spi3 chipselects are available in different mode than the main spi3 2966e08d6bbSMika Westerberg * functionality, which is using mode 1. 2976e08d6bbSMika Westerberg */ 2986e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 2996e08d6bbSMika Westerberg ALTERNATE_FUNCTION(76, 3, false), 3006e08d6bbSMika Westerberg ALTERNATE_FUNCTION(80, 3, false), 3016e08d6bbSMika Westerberg }; 3026e08d6bbSMika Westerberg 3036e08d6bbSMika Westerberg static const struct chv_pingroup southwest_groups[] = { 3045458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false), 3055458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false), 3065458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false), 3075458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false), 3085458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true), 3095458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true), 3105458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true), 3115458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true), 3125458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true), 3135458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true), 3145458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true), 3155458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 3166e08d6bbSMika Westerberg 3176e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 3186e08d6bbSMika Westerberg southwest_lpe_altfuncs), 3196e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 3206e08d6bbSMika Westerberg southwest_spi3_altfuncs), 3216e08d6bbSMika Westerberg }; 3226e08d6bbSMika Westerberg 3236e08d6bbSMika Westerberg static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 3246e08d6bbSMika Westerberg static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 3256e08d6bbSMika Westerberg static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 3266e08d6bbSMika Westerberg static const char * const southwest_hda_groups[] = { "hda_grp" }; 3276e08d6bbSMika Westerberg static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 3286e08d6bbSMika Westerberg static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 3296e08d6bbSMika Westerberg static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 3306e08d6bbSMika Westerberg static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 3316e08d6bbSMika Westerberg static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 3326e08d6bbSMika Westerberg static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 3336e08d6bbSMika Westerberg static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 3346e08d6bbSMika Westerberg static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 3356e08d6bbSMika Westerberg static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 3366e08d6bbSMika Westerberg static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 3376e08d6bbSMika Westerberg 3386e08d6bbSMika Westerberg /* 3396e08d6bbSMika Westerberg * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 3406e08d6bbSMika Westerberg * enabled only as GPIOs. 3416e08d6bbSMika Westerberg */ 3425458b7ceSAndy Shevchenko static const struct intel_function southwest_functions[] = { 3436e08d6bbSMika Westerberg FUNCTION("uart0", southwest_uart0_groups), 3446e08d6bbSMika Westerberg FUNCTION("uart1", southwest_uart1_groups), 3456e08d6bbSMika Westerberg FUNCTION("uart2", southwest_uart2_groups), 3466e08d6bbSMika Westerberg FUNCTION("hda", southwest_hda_groups), 3476e08d6bbSMika Westerberg FUNCTION("lpe", southwest_lpe_groups), 3486e08d6bbSMika Westerberg FUNCTION("i2c0", southwest_i2c0_groups), 3496e08d6bbSMika Westerberg FUNCTION("i2c1", southwest_i2c1_groups), 3506e08d6bbSMika Westerberg FUNCTION("i2c2", southwest_i2c2_groups), 3516e08d6bbSMika Westerberg FUNCTION("i2c3", southwest_i2c3_groups), 3526e08d6bbSMika Westerberg FUNCTION("i2c4", southwest_i2c4_groups), 3536e08d6bbSMika Westerberg FUNCTION("i2c5", southwest_i2c5_groups), 3546e08d6bbSMika Westerberg FUNCTION("i2c6", southwest_i2c6_groups), 3556e08d6bbSMika Westerberg FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 3566e08d6bbSMika Westerberg FUNCTION("spi3", southwest_spi3_groups), 3576e08d6bbSMika Westerberg }; 3586e08d6bbSMika Westerberg 3596e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 3606e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 3616e08d6bbSMika Westerberg GPIO_PINRANGE(15, 22), 3626e08d6bbSMika Westerberg GPIO_PINRANGE(30, 37), 3636e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 3646e08d6bbSMika Westerberg GPIO_PINRANGE(60, 67), 3656e08d6bbSMika Westerberg GPIO_PINRANGE(75, 82), 3666e08d6bbSMika Westerberg GPIO_PINRANGE(90, 97), 3676e08d6bbSMika Westerberg }; 3686e08d6bbSMika Westerberg 3696e08d6bbSMika Westerberg static const struct chv_community southwest_community = { 3706e08d6bbSMika Westerberg .uid = "1", 3716e08d6bbSMika Westerberg .pins = southwest_pins, 3726e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southwest_pins), 3736e08d6bbSMika Westerberg .groups = southwest_groups, 3746e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southwest_groups), 3756e08d6bbSMika Westerberg .functions = southwest_functions, 3766e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southwest_functions), 3776e08d6bbSMika Westerberg .gpio_ranges = southwest_gpio_ranges, 3786e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 37947c950d1SMika Westerberg /* 38047c950d1SMika Westerberg * Southwest community can benerate GPIO interrupts only for the 38147c950d1SMika Westerberg * first 8 interrupts. The upper half (8-15) can only be used to 38247c950d1SMika Westerberg * trigger GPEs. 38347c950d1SMika Westerberg */ 38447c950d1SMika Westerberg .nirqs = 8, 385a0b02859SHans de Goede .acpi_space_id = 0x91, 3866e08d6bbSMika Westerberg }; 3876e08d6bbSMika Westerberg 3886e08d6bbSMika Westerberg static const struct pinctrl_pin_desc north_pins[] = { 3896e08d6bbSMika Westerberg PINCTRL_PIN(0, "GPIO_DFX_0"), 3906e08d6bbSMika Westerberg PINCTRL_PIN(1, "GPIO_DFX_3"), 3916e08d6bbSMika Westerberg PINCTRL_PIN(2, "GPIO_DFX_7"), 3926e08d6bbSMika Westerberg PINCTRL_PIN(3, "GPIO_DFX_1"), 3936e08d6bbSMika Westerberg PINCTRL_PIN(4, "GPIO_DFX_5"), 3946e08d6bbSMika Westerberg PINCTRL_PIN(5, "GPIO_DFX_4"), 3956e08d6bbSMika Westerberg PINCTRL_PIN(6, "GPIO_DFX_8"), 3966e08d6bbSMika Westerberg PINCTRL_PIN(7, "GPIO_DFX_2"), 3976e08d6bbSMika Westerberg PINCTRL_PIN(8, "GPIO_DFX_6"), 3986e08d6bbSMika Westerberg 3996e08d6bbSMika Westerberg PINCTRL_PIN(15, "GPIO_SUS0"), 4006e08d6bbSMika Westerberg PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 4016e08d6bbSMika Westerberg PINCTRL_PIN(17, "GPIO_SUS3"), 4026e08d6bbSMika Westerberg PINCTRL_PIN(18, "GPIO_SUS7"), 4036e08d6bbSMika Westerberg PINCTRL_PIN(19, "GPIO_SUS1"), 4046e08d6bbSMika Westerberg PINCTRL_PIN(20, "GPIO_SUS5"), 4056e08d6bbSMika Westerberg PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 4066e08d6bbSMika Westerberg PINCTRL_PIN(22, "GPIO_SUS4"), 4076e08d6bbSMika Westerberg PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 4086e08d6bbSMika Westerberg PINCTRL_PIN(24, "GPIO_SUS2"), 4096e08d6bbSMika Westerberg PINCTRL_PIN(25, "GPIO_SUS6"), 4106e08d6bbSMika Westerberg PINCTRL_PIN(26, "CX_PREQ_B"), 4116e08d6bbSMika Westerberg PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 4126e08d6bbSMika Westerberg 4136e08d6bbSMika Westerberg PINCTRL_PIN(30, "TRST_B"), 4146e08d6bbSMika Westerberg PINCTRL_PIN(31, "TCK"), 4156e08d6bbSMika Westerberg PINCTRL_PIN(32, "PROCHOT_B"), 4166e08d6bbSMika Westerberg PINCTRL_PIN(33, "SVIDO_DATA"), 4176e08d6bbSMika Westerberg PINCTRL_PIN(34, "TMS"), 4186e08d6bbSMika Westerberg PINCTRL_PIN(35, "CX_PRDY_B_2"), 4196e08d6bbSMika Westerberg PINCTRL_PIN(36, "TDO_2"), 4206e08d6bbSMika Westerberg PINCTRL_PIN(37, "CX_PRDY_B"), 4216e08d6bbSMika Westerberg PINCTRL_PIN(38, "SVIDO_ALERT_B"), 4226e08d6bbSMika Westerberg PINCTRL_PIN(39, "TDO"), 4236e08d6bbSMika Westerberg PINCTRL_PIN(40, "SVIDO_CLK"), 4246e08d6bbSMika Westerberg PINCTRL_PIN(41, "TDI"), 4256e08d6bbSMika Westerberg 4266e08d6bbSMika Westerberg PINCTRL_PIN(45, "GP_CAMERASB_05"), 4276e08d6bbSMika Westerberg PINCTRL_PIN(46, "GP_CAMERASB_02"), 4286e08d6bbSMika Westerberg PINCTRL_PIN(47, "GP_CAMERASB_08"), 4296e08d6bbSMika Westerberg PINCTRL_PIN(48, "GP_CAMERASB_00"), 4306e08d6bbSMika Westerberg PINCTRL_PIN(49, "GP_CAMERASB_06"), 4316e08d6bbSMika Westerberg PINCTRL_PIN(50, "GP_CAMERASB_10"), 4326e08d6bbSMika Westerberg PINCTRL_PIN(51, "GP_CAMERASB_03"), 4336e08d6bbSMika Westerberg PINCTRL_PIN(52, "GP_CAMERASB_09"), 4346e08d6bbSMika Westerberg PINCTRL_PIN(53, "GP_CAMERASB_01"), 4356e08d6bbSMika Westerberg PINCTRL_PIN(54, "GP_CAMERASB_07"), 4366e08d6bbSMika Westerberg PINCTRL_PIN(55, "GP_CAMERASB_11"), 4376e08d6bbSMika Westerberg PINCTRL_PIN(56, "GP_CAMERASB_04"), 4386e08d6bbSMika Westerberg 4396e08d6bbSMika Westerberg PINCTRL_PIN(60, "PANEL0_BKLTEN"), 4406e08d6bbSMika Westerberg PINCTRL_PIN(61, "HV_DDI0_HPD"), 4416e08d6bbSMika Westerberg PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 4426e08d6bbSMika Westerberg PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 4436e08d6bbSMika Westerberg PINCTRL_PIN(64, "HV_DDI1_HPD"), 4446e08d6bbSMika Westerberg PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 4456e08d6bbSMika Westerberg PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 4466e08d6bbSMika Westerberg PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 4476e08d6bbSMika Westerberg PINCTRL_PIN(68, "HV_DDI2_HPD"), 4486e08d6bbSMika Westerberg PINCTRL_PIN(69, "PANEL1_VDDEN"), 4496e08d6bbSMika Westerberg PINCTRL_PIN(70, "PANEL1_BKLTEN"), 4506e08d6bbSMika Westerberg PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 4516e08d6bbSMika Westerberg PINCTRL_PIN(72, "PANEL0_VDDEN"), 4526e08d6bbSMika Westerberg }; 4536e08d6bbSMika Westerberg 4546e08d6bbSMika Westerberg static const struct chv_gpio_pinrange north_gpio_ranges[] = { 4556e08d6bbSMika Westerberg GPIO_PINRANGE(0, 8), 4566e08d6bbSMika Westerberg GPIO_PINRANGE(15, 27), 4576e08d6bbSMika Westerberg GPIO_PINRANGE(30, 41), 4586e08d6bbSMika Westerberg GPIO_PINRANGE(45, 56), 4596e08d6bbSMika Westerberg GPIO_PINRANGE(60, 72), 4606e08d6bbSMika Westerberg }; 4616e08d6bbSMika Westerberg 4626e08d6bbSMika Westerberg static const struct chv_community north_community = { 4636e08d6bbSMika Westerberg .uid = "2", 4646e08d6bbSMika Westerberg .pins = north_pins, 4656e08d6bbSMika Westerberg .npins = ARRAY_SIZE(north_pins), 4666e08d6bbSMika Westerberg .gpio_ranges = north_gpio_ranges, 4676e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 46847c950d1SMika Westerberg /* 469505485a8SChris Gorman * North community can generate GPIO interrupts only for the first 47047c950d1SMika Westerberg * 8 interrupts. The upper half (8-15) can only be used to trigger 47147c950d1SMika Westerberg * GPEs. 47247c950d1SMika Westerberg */ 47347c950d1SMika Westerberg .nirqs = 8, 474a0b02859SHans de Goede .acpi_space_id = 0x92, 4756e08d6bbSMika Westerberg }; 4766e08d6bbSMika Westerberg 4776e08d6bbSMika Westerberg static const struct pinctrl_pin_desc east_pins[] = { 4786e08d6bbSMika Westerberg PINCTRL_PIN(0, "PMU_SLP_S3_B"), 4796e08d6bbSMika Westerberg PINCTRL_PIN(1, "PMU_BATLOW_B"), 4806e08d6bbSMika Westerberg PINCTRL_PIN(2, "SUS_STAT_B"), 4816e08d6bbSMika Westerberg PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 4826e08d6bbSMika Westerberg PINCTRL_PIN(4, "PMU_AC_PRESENT"), 4836e08d6bbSMika Westerberg PINCTRL_PIN(5, "PMU_PLTRST_B"), 4846e08d6bbSMika Westerberg PINCTRL_PIN(6, "PMU_SUSCLK"), 4856e08d6bbSMika Westerberg PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 4866e08d6bbSMika Westerberg PINCTRL_PIN(8, "PMU_PWRBTN_B"), 4876e08d6bbSMika Westerberg PINCTRL_PIN(9, "PMU_SLP_S4_B"), 4886e08d6bbSMika Westerberg PINCTRL_PIN(10, "PMU_WAKE_B"), 4896e08d6bbSMika Westerberg PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 4906e08d6bbSMika Westerberg 4916e08d6bbSMika Westerberg PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 4926e08d6bbSMika Westerberg PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 4936e08d6bbSMika Westerberg PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 4946e08d6bbSMika Westerberg PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 4956e08d6bbSMika Westerberg PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 4966e08d6bbSMika Westerberg PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 4976e08d6bbSMika Westerberg PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 4986e08d6bbSMika Westerberg PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 4996e08d6bbSMika Westerberg PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 5006e08d6bbSMika Westerberg PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 5016e08d6bbSMika Westerberg PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 5026e08d6bbSMika Westerberg PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 5036e08d6bbSMika Westerberg }; 5046e08d6bbSMika Westerberg 5056e08d6bbSMika Westerberg static const struct chv_gpio_pinrange east_gpio_ranges[] = { 5066e08d6bbSMika Westerberg GPIO_PINRANGE(0, 11), 5076e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 5086e08d6bbSMika Westerberg }; 5096e08d6bbSMika Westerberg 5106e08d6bbSMika Westerberg static const struct chv_community east_community = { 5116e08d6bbSMika Westerberg .uid = "3", 5126e08d6bbSMika Westerberg .pins = east_pins, 5136e08d6bbSMika Westerberg .npins = ARRAY_SIZE(east_pins), 5146e08d6bbSMika Westerberg .gpio_ranges = east_gpio_ranges, 5156e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 51647c950d1SMika Westerberg .nirqs = 16, 517a0b02859SHans de Goede .acpi_space_id = 0x93, 5186e08d6bbSMika Westerberg }; 5196e08d6bbSMika Westerberg 5206e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southeast_pins[] = { 5216e08d6bbSMika Westerberg PINCTRL_PIN(0, "MF_PLT_CLK0"), 5226e08d6bbSMika Westerberg PINCTRL_PIN(1, "PWM1"), 5236e08d6bbSMika Westerberg PINCTRL_PIN(2, "MF_PLT_CLK1"), 5246e08d6bbSMika Westerberg PINCTRL_PIN(3, "MF_PLT_CLK4"), 5256e08d6bbSMika Westerberg PINCTRL_PIN(4, "MF_PLT_CLK3"), 5266e08d6bbSMika Westerberg PINCTRL_PIN(5, "PWM0"), 5276e08d6bbSMika Westerberg PINCTRL_PIN(6, "MF_PLT_CLK5"), 5286e08d6bbSMika Westerberg PINCTRL_PIN(7, "MF_PLT_CLK2"), 5296e08d6bbSMika Westerberg 5306e08d6bbSMika Westerberg PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 5316e08d6bbSMika Westerberg PINCTRL_PIN(16, "SDMMC1_CLK"), 5326e08d6bbSMika Westerberg PINCTRL_PIN(17, "SDMMC1_D0"), 5336e08d6bbSMika Westerberg PINCTRL_PIN(18, "SDMMC2_D1"), 5346e08d6bbSMika Westerberg PINCTRL_PIN(19, "SDMMC2_CLK"), 5356e08d6bbSMika Westerberg PINCTRL_PIN(20, "SDMMC1_D2"), 5366e08d6bbSMika Westerberg PINCTRL_PIN(21, "SDMMC2_D2"), 5376e08d6bbSMika Westerberg PINCTRL_PIN(22, "SDMMC2_CMD"), 5386e08d6bbSMika Westerberg PINCTRL_PIN(23, "SDMMC1_CMD"), 5396e08d6bbSMika Westerberg PINCTRL_PIN(24, "SDMMC1_D1"), 5406e08d6bbSMika Westerberg PINCTRL_PIN(25, "SDMMC2_D0"), 5416e08d6bbSMika Westerberg PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 5426e08d6bbSMika Westerberg 5436e08d6bbSMika Westerberg PINCTRL_PIN(30, "SDMMC3_D1"), 5446e08d6bbSMika Westerberg PINCTRL_PIN(31, "SDMMC3_CLK"), 5456e08d6bbSMika Westerberg PINCTRL_PIN(32, "SDMMC3_D3"), 5466e08d6bbSMika Westerberg PINCTRL_PIN(33, "SDMMC3_D2"), 5476e08d6bbSMika Westerberg PINCTRL_PIN(34, "SDMMC3_CMD"), 5486e08d6bbSMika Westerberg PINCTRL_PIN(35, "SDMMC3_D0"), 5496e08d6bbSMika Westerberg 5506e08d6bbSMika Westerberg PINCTRL_PIN(45, "MF_LPC_AD2"), 5516e08d6bbSMika Westerberg PINCTRL_PIN(46, "LPC_CLKRUNB"), 5526e08d6bbSMika Westerberg PINCTRL_PIN(47, "MF_LPC_AD0"), 5536e08d6bbSMika Westerberg PINCTRL_PIN(48, "LPC_FRAMEB"), 5546e08d6bbSMika Westerberg PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 5556e08d6bbSMika Westerberg PINCTRL_PIN(50, "MF_LPC_AD3"), 5566e08d6bbSMika Westerberg PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 5576e08d6bbSMika Westerberg PINCTRL_PIN(52, "MF_LPC_AD1"), 5586e08d6bbSMika Westerberg 5596e08d6bbSMika Westerberg PINCTRL_PIN(60, "SPI1_MISO"), 5606e08d6bbSMika Westerberg PINCTRL_PIN(61, "SPI1_CSO_B"), 5616e08d6bbSMika Westerberg PINCTRL_PIN(62, "SPI1_CLK"), 5626e08d6bbSMika Westerberg PINCTRL_PIN(63, "MMC1_D6"), 5636e08d6bbSMika Westerberg PINCTRL_PIN(64, "SPI1_MOSI"), 5646e08d6bbSMika Westerberg PINCTRL_PIN(65, "MMC1_D5"), 5656e08d6bbSMika Westerberg PINCTRL_PIN(66, "SPI1_CS1_B"), 5666e08d6bbSMika Westerberg PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 5676e08d6bbSMika Westerberg PINCTRL_PIN(68, "MMC1_D7"), 5686e08d6bbSMika Westerberg PINCTRL_PIN(69, "MMC1_RCLK"), 5696e08d6bbSMika Westerberg 5706e08d6bbSMika Westerberg PINCTRL_PIN(75, "USB_OC1_B"), 5716e08d6bbSMika Westerberg PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 5726e08d6bbSMika Westerberg PINCTRL_PIN(77, "GPIO_ALERT"), 5736e08d6bbSMika Westerberg PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 5746e08d6bbSMika Westerberg PINCTRL_PIN(79, "ILB_SERIRQ"), 5756e08d6bbSMika Westerberg PINCTRL_PIN(80, "USB_OC0_B"), 5766e08d6bbSMika Westerberg PINCTRL_PIN(81, "SDMMC3_CD_B"), 5776e08d6bbSMika Westerberg PINCTRL_PIN(82, "SPKR"), 5786e08d6bbSMika Westerberg PINCTRL_PIN(83, "SUSPWRDNACK"), 5796e08d6bbSMika Westerberg PINCTRL_PIN(84, "SPARE_PIN"), 5806e08d6bbSMika Westerberg PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 5816e08d6bbSMika Westerberg }; 5826e08d6bbSMika Westerberg 5836e08d6bbSMika Westerberg static const unsigned southeast_pwm0_pins[] = { 5 }; 5846e08d6bbSMika Westerberg static const unsigned southeast_pwm1_pins[] = { 1 }; 5856e08d6bbSMika Westerberg static const unsigned southeast_sdmmc1_pins[] = { 5866e08d6bbSMika Westerberg 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 5876e08d6bbSMika Westerberg }; 5886e08d6bbSMika Westerberg static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 5896e08d6bbSMika Westerberg static const unsigned southeast_sdmmc3_pins[] = { 5906e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 78, 81, 85, 5916e08d6bbSMika Westerberg }; 5926e08d6bbSMika Westerberg static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 5936e08d6bbSMika Westerberg static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 5946e08d6bbSMika Westerberg 5956e08d6bbSMika Westerberg static const struct chv_pingroup southeast_groups[] = { 5965458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false), 5975458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false), 5985458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 5995458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 6005458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 6015458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false), 6025458b7ceSAndy Shevchenko PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false), 6036e08d6bbSMika Westerberg }; 6046e08d6bbSMika Westerberg 6056e08d6bbSMika Westerberg static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 6066e08d6bbSMika Westerberg static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 6076e08d6bbSMika Westerberg static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 6086e08d6bbSMika Westerberg static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 6096e08d6bbSMika Westerberg static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 6106e08d6bbSMika Westerberg static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 6116e08d6bbSMika Westerberg static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 6126e08d6bbSMika Westerberg 6135458b7ceSAndy Shevchenko static const struct intel_function southeast_functions[] = { 6146e08d6bbSMika Westerberg FUNCTION("pwm0", southeast_pwm0_groups), 6156e08d6bbSMika Westerberg FUNCTION("pwm1", southeast_pwm1_groups), 6166e08d6bbSMika Westerberg FUNCTION("sdmmc1", southeast_sdmmc1_groups), 6176e08d6bbSMika Westerberg FUNCTION("sdmmc2", southeast_sdmmc2_groups), 6186e08d6bbSMika Westerberg FUNCTION("sdmmc3", southeast_sdmmc3_groups), 6196e08d6bbSMika Westerberg FUNCTION("spi1", southeast_spi1_groups), 6206e08d6bbSMika Westerberg FUNCTION("spi2", southeast_spi2_groups), 6216e08d6bbSMika Westerberg }; 6226e08d6bbSMika Westerberg 6236e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 6246e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 6256e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 6266e08d6bbSMika Westerberg GPIO_PINRANGE(30, 35), 6276e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 6286e08d6bbSMika Westerberg GPIO_PINRANGE(60, 69), 6296e08d6bbSMika Westerberg GPIO_PINRANGE(75, 85), 6306e08d6bbSMika Westerberg }; 6316e08d6bbSMika Westerberg 6326e08d6bbSMika Westerberg static const struct chv_community southeast_community = { 6336e08d6bbSMika Westerberg .uid = "4", 6346e08d6bbSMika Westerberg .pins = southeast_pins, 6356e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southeast_pins), 6366e08d6bbSMika Westerberg .groups = southeast_groups, 6376e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southeast_groups), 6386e08d6bbSMika Westerberg .functions = southeast_functions, 6396e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southeast_functions), 6406e08d6bbSMika Westerberg .gpio_ranges = southeast_gpio_ranges, 6416e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 64247c950d1SMika Westerberg .nirqs = 16, 643a0b02859SHans de Goede .acpi_space_id = 0x94, 6446e08d6bbSMika Westerberg }; 6456e08d6bbSMika Westerberg 6466e08d6bbSMika Westerberg static const struct chv_community *chv_communities[] = { 6476e08d6bbSMika Westerberg &southwest_community, 6486e08d6bbSMika Westerberg &north_community, 6496e08d6bbSMika Westerberg &east_community, 6506e08d6bbSMika Westerberg &southeast_community, 6516e08d6bbSMika Westerberg }; 6526e08d6bbSMika Westerberg 6530bd50d71SDan O'Donovan /* 6540bd50d71SDan O'Donovan * Lock to serialize register accesses 6550bd50d71SDan O'Donovan * 6560bd50d71SDan O'Donovan * Due to a silicon issue, a shared lock must be used to prevent 6570bd50d71SDan O'Donovan * concurrent accesses across the 4 GPIO controllers. 6580bd50d71SDan O'Donovan * 6590bd50d71SDan O'Donovan * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 6600bd50d71SDan O'Donovan * errata #CHT34, for further information. 6610bd50d71SDan O'Donovan */ 6620bd50d71SDan O'Donovan static DEFINE_RAW_SPINLOCK(chv_lock); 6630bd50d71SDan O'Donovan 6646e08d6bbSMika Westerberg static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 6656e08d6bbSMika Westerberg unsigned reg) 6666e08d6bbSMika Westerberg { 6676e08d6bbSMika Westerberg unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 6686e08d6bbSMika Westerberg unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 6696e08d6bbSMika Westerberg 6706e08d6bbSMika Westerberg offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 6716e08d6bbSMika Westerberg GPIO_REGS_SIZE * pad_no; 6726e08d6bbSMika Westerberg 6736e08d6bbSMika Westerberg return pctrl->regs + offset + reg; 6746e08d6bbSMika Westerberg } 6756e08d6bbSMika Westerberg 6766e08d6bbSMika Westerberg static void chv_writel(u32 value, void __iomem *reg) 6776e08d6bbSMika Westerberg { 6786e08d6bbSMika Westerberg writel(value, reg); 6796e08d6bbSMika Westerberg /* simple readback to confirm the bus transferring done */ 6806e08d6bbSMika Westerberg readl(reg); 6816e08d6bbSMika Westerberg } 6826e08d6bbSMika Westerberg 6836e08d6bbSMika Westerberg /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 6846e08d6bbSMika Westerberg static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 6856e08d6bbSMika Westerberg { 6866e08d6bbSMika Westerberg void __iomem *reg; 6876e08d6bbSMika Westerberg 6886e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 6896e08d6bbSMika Westerberg return readl(reg) & CHV_PADCTRL1_CFGLOCK; 6906e08d6bbSMika Westerberg } 6916e08d6bbSMika Westerberg 6926e08d6bbSMika Westerberg static int chv_get_groups_count(struct pinctrl_dev *pctldev) 6936e08d6bbSMika Westerberg { 6946e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 6956e08d6bbSMika Westerberg 6966e08d6bbSMika Westerberg return pctrl->community->ngroups; 6976e08d6bbSMika Westerberg } 6986e08d6bbSMika Westerberg 6996e08d6bbSMika Westerberg static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 7006e08d6bbSMika Westerberg unsigned group) 7016e08d6bbSMika Westerberg { 7026e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7036e08d6bbSMika Westerberg 7046e08d6bbSMika Westerberg return pctrl->community->groups[group].name; 7056e08d6bbSMika Westerberg } 7066e08d6bbSMika Westerberg 7076e08d6bbSMika Westerberg static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 7086e08d6bbSMika Westerberg const unsigned **pins, unsigned *npins) 7096e08d6bbSMika Westerberg { 7106e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7116e08d6bbSMika Westerberg 7126e08d6bbSMika Westerberg *pins = pctrl->community->groups[group].pins; 7136e08d6bbSMika Westerberg *npins = pctrl->community->groups[group].npins; 7146e08d6bbSMika Westerberg return 0; 7156e08d6bbSMika Westerberg } 7166e08d6bbSMika Westerberg 7176e08d6bbSMika Westerberg static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 7186e08d6bbSMika Westerberg unsigned offset) 7196e08d6bbSMika Westerberg { 7206e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7216e08d6bbSMika Westerberg unsigned long flags; 7226e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 7236e08d6bbSMika Westerberg bool locked; 7246e08d6bbSMika Westerberg 7250bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 7266e08d6bbSMika Westerberg 7276e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 7286e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 7296e08d6bbSMika Westerberg locked = chv_pad_locked(pctrl, offset); 7306e08d6bbSMika Westerberg 7310bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 7326e08d6bbSMika Westerberg 7336e08d6bbSMika Westerberg if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 7346e08d6bbSMika Westerberg seq_puts(s, "GPIO "); 7356e08d6bbSMika Westerberg } else { 7366e08d6bbSMika Westerberg u32 mode; 7376e08d6bbSMika Westerberg 7386e08d6bbSMika Westerberg mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 7396e08d6bbSMika Westerberg mode >>= CHV_PADCTRL0_PMODE_SHIFT; 7406e08d6bbSMika Westerberg 7416e08d6bbSMika Westerberg seq_printf(s, "mode %d ", mode); 7426e08d6bbSMika Westerberg } 7436e08d6bbSMika Westerberg 744684373eaSMika Westerberg seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 7456e08d6bbSMika Westerberg 7466e08d6bbSMika Westerberg if (locked) 7476e08d6bbSMika Westerberg seq_puts(s, " [LOCKED]"); 7486e08d6bbSMika Westerberg } 7496e08d6bbSMika Westerberg 7506e08d6bbSMika Westerberg static const struct pinctrl_ops chv_pinctrl_ops = { 7516e08d6bbSMika Westerberg .get_groups_count = chv_get_groups_count, 7526e08d6bbSMika Westerberg .get_group_name = chv_get_group_name, 7536e08d6bbSMika Westerberg .get_group_pins = chv_get_group_pins, 7546e08d6bbSMika Westerberg .pin_dbg_show = chv_pin_dbg_show, 7556e08d6bbSMika Westerberg }; 7566e08d6bbSMika Westerberg 7576e08d6bbSMika Westerberg static int chv_get_functions_count(struct pinctrl_dev *pctldev) 7586e08d6bbSMika Westerberg { 7596e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7606e08d6bbSMika Westerberg 7616e08d6bbSMika Westerberg return pctrl->community->nfunctions; 7626e08d6bbSMika Westerberg } 7636e08d6bbSMika Westerberg 7646e08d6bbSMika Westerberg static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 7656e08d6bbSMika Westerberg unsigned function) 7666e08d6bbSMika Westerberg { 7676e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7686e08d6bbSMika Westerberg 7696e08d6bbSMika Westerberg return pctrl->community->functions[function].name; 7706e08d6bbSMika Westerberg } 7716e08d6bbSMika Westerberg 7726e08d6bbSMika Westerberg static int chv_get_function_groups(struct pinctrl_dev *pctldev, 7736e08d6bbSMika Westerberg unsigned function, 7746e08d6bbSMika Westerberg const char * const **groups, 7756e08d6bbSMika Westerberg unsigned * const ngroups) 7766e08d6bbSMika Westerberg { 7776e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7786e08d6bbSMika Westerberg 7796e08d6bbSMika Westerberg *groups = pctrl->community->functions[function].groups; 7806e08d6bbSMika Westerberg *ngroups = pctrl->community->functions[function].ngroups; 7816e08d6bbSMika Westerberg return 0; 7826e08d6bbSMika Westerberg } 7836e08d6bbSMika Westerberg 7846e08d6bbSMika Westerberg static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 7856e08d6bbSMika Westerberg unsigned group) 7866e08d6bbSMika Westerberg { 7876e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7886e08d6bbSMika Westerberg const struct chv_pingroup *grp; 7896e08d6bbSMika Westerberg unsigned long flags; 7906e08d6bbSMika Westerberg int i; 7916e08d6bbSMika Westerberg 7926e08d6bbSMika Westerberg grp = &pctrl->community->groups[group]; 7936e08d6bbSMika Westerberg 7940bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 7956e08d6bbSMika Westerberg 7966e08d6bbSMika Westerberg /* Check first that the pad is not locked */ 7976e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 7986e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, grp->pins[i])) { 7996e08d6bbSMika Westerberg dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 8006e08d6bbSMika Westerberg grp->pins[i]); 8010bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8026e08d6bbSMika Westerberg return -EBUSY; 8036e08d6bbSMika Westerberg } 8046e08d6bbSMika Westerberg } 8056e08d6bbSMika Westerberg 8066e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 8076e08d6bbSMika Westerberg const struct chv_alternate_function *altfunc = &grp->altfunc; 8086e08d6bbSMika Westerberg int pin = grp->pins[i]; 8096e08d6bbSMika Westerberg void __iomem *reg; 8106e08d6bbSMika Westerberg u32 value; 8116e08d6bbSMika Westerberg 8126e08d6bbSMika Westerberg /* Check if there is pin-specific config */ 8136e08d6bbSMika Westerberg if (grp->overrides) { 8146e08d6bbSMika Westerberg int j; 8156e08d6bbSMika Westerberg 8166e08d6bbSMika Westerberg for (j = 0; j < grp->noverrides; j++) { 8176e08d6bbSMika Westerberg if (grp->overrides[j].pin == pin) { 8186e08d6bbSMika Westerberg altfunc = &grp->overrides[j]; 8196e08d6bbSMika Westerberg break; 8206e08d6bbSMika Westerberg } 8216e08d6bbSMika Westerberg } 8226e08d6bbSMika Westerberg } 8236e08d6bbSMika Westerberg 8246e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 8256e08d6bbSMika Westerberg value = readl(reg); 8266e08d6bbSMika Westerberg /* Disable GPIO mode */ 8276e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_GPIOEN; 8286e08d6bbSMika Westerberg /* Set to desired mode */ 8296e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_PMODE_MASK; 8306e08d6bbSMika Westerberg value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 8316e08d6bbSMika Westerberg chv_writel(value, reg); 8326e08d6bbSMika Westerberg 8336e08d6bbSMika Westerberg /* Update for invert_oe */ 8346e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 8356e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 8366e08d6bbSMika Westerberg if (altfunc->invert_oe) 8376e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 8386e08d6bbSMika Westerberg chv_writel(value, reg); 8396e08d6bbSMika Westerberg 8406e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 8416e08d6bbSMika Westerberg pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 8426e08d6bbSMika Westerberg } 8436e08d6bbSMika Westerberg 8440bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8456e08d6bbSMika Westerberg 8466e08d6bbSMika Westerberg return 0; 8476e08d6bbSMika Westerberg } 8486e08d6bbSMika Westerberg 8496e08d6bbSMika Westerberg static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 8506e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 8516e08d6bbSMika Westerberg unsigned offset) 8526e08d6bbSMika Westerberg { 8536e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 8546e08d6bbSMika Westerberg unsigned long flags; 8556e08d6bbSMika Westerberg void __iomem *reg; 8566e08d6bbSMika Westerberg u32 value; 8576e08d6bbSMika Westerberg 8580bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 8596e08d6bbSMika Westerberg 8606e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, offset)) { 8616e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 8626e08d6bbSMika Westerberg if (!(value & CHV_PADCTRL0_GPIOEN)) { 8636e08d6bbSMika Westerberg /* Locked so cannot enable */ 8640bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8656e08d6bbSMika Westerberg return -EBUSY; 8666e08d6bbSMika Westerberg } 8676e08d6bbSMika Westerberg } else { 8686e08d6bbSMika Westerberg int i; 8696e08d6bbSMika Westerberg 8706e08d6bbSMika Westerberg /* Reset the interrupt mapping */ 8716e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 8726e08d6bbSMika Westerberg if (pctrl->intr_lines[i] == offset) { 8736e08d6bbSMika Westerberg pctrl->intr_lines[i] = 0; 8746e08d6bbSMika Westerberg break; 8756e08d6bbSMika Westerberg } 8766e08d6bbSMika Westerberg } 8776e08d6bbSMika Westerberg 8786e08d6bbSMika Westerberg /* Disable interrupt generation */ 8796e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 8806e08d6bbSMika Westerberg value = readl(reg); 8816e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 8826e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 8836e08d6bbSMika Westerberg chv_writel(value, reg); 8846e08d6bbSMika Westerberg 8856e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 8862479c730SMika Westerberg value = readl(reg); 8872479c730SMika Westerberg 8882479c730SMika Westerberg /* 8892479c730SMika Westerberg * If the pin is in HiZ mode (both TX and RX buffers are 8902479c730SMika Westerberg * disabled) we turn it to be input now. 8912479c730SMika Westerberg */ 8922479c730SMika Westerberg if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 8932479c730SMika Westerberg (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 8942479c730SMika Westerberg value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 8952479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOCFG_GPI << 8962479c730SMika Westerberg CHV_PADCTRL0_GPIOCFG_SHIFT; 8972479c730SMika Westerberg } 8982479c730SMika Westerberg 8992479c730SMika Westerberg /* Switch to a GPIO mode */ 9002479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOEN; 9016e08d6bbSMika Westerberg chv_writel(value, reg); 9026e08d6bbSMika Westerberg } 9036e08d6bbSMika Westerberg 9040bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9056e08d6bbSMika Westerberg 9066e08d6bbSMika Westerberg return 0; 9076e08d6bbSMika Westerberg } 9086e08d6bbSMika Westerberg 9096e08d6bbSMika Westerberg static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 9106e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9116e08d6bbSMika Westerberg unsigned offset) 9126e08d6bbSMika Westerberg { 9136e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9146e08d6bbSMika Westerberg unsigned long flags; 9156e08d6bbSMika Westerberg void __iomem *reg; 9166e08d6bbSMika Westerberg u32 value; 9176e08d6bbSMika Westerberg 9180bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9196e08d6bbSMika Westerberg 9206e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9216e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 9226e08d6bbSMika Westerberg chv_writel(value, reg); 9236e08d6bbSMika Westerberg 9240bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9256e08d6bbSMika Westerberg } 9266e08d6bbSMika Westerberg 9276e08d6bbSMika Westerberg static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 9286e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9296e08d6bbSMika Westerberg unsigned offset, bool input) 9306e08d6bbSMika Westerberg { 9316e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9326e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9336e08d6bbSMika Westerberg unsigned long flags; 9346e08d6bbSMika Westerberg u32 ctrl0; 9356e08d6bbSMika Westerberg 9360bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9376e08d6bbSMika Westerberg 9386e08d6bbSMika Westerberg ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 9396e08d6bbSMika Westerberg if (input) 9406e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 9416e08d6bbSMika Westerberg else 9426e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 9436e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 9446e08d6bbSMika Westerberg 9450bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9466e08d6bbSMika Westerberg 9476e08d6bbSMika Westerberg return 0; 9486e08d6bbSMika Westerberg } 9496e08d6bbSMika Westerberg 9506e08d6bbSMika Westerberg static const struct pinmux_ops chv_pinmux_ops = { 9516e08d6bbSMika Westerberg .get_functions_count = chv_get_functions_count, 9526e08d6bbSMika Westerberg .get_function_name = chv_get_function_name, 9536e08d6bbSMika Westerberg .get_function_groups = chv_get_function_groups, 9546e08d6bbSMika Westerberg .set_mux = chv_pinmux_set_mux, 9556e08d6bbSMika Westerberg .gpio_request_enable = chv_gpio_request_enable, 9566e08d6bbSMika Westerberg .gpio_disable_free = chv_gpio_disable_free, 9576e08d6bbSMika Westerberg .gpio_set_direction = chv_gpio_set_direction, 9586e08d6bbSMika Westerberg }; 9596e08d6bbSMika Westerberg 9606e08d6bbSMika Westerberg static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 9616e08d6bbSMika Westerberg unsigned long *config) 9626e08d6bbSMika Westerberg { 9636e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9646e08d6bbSMika Westerberg enum pin_config_param param = pinconf_to_config_param(*config); 9656e08d6bbSMika Westerberg unsigned long flags; 9666e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 9676e08d6bbSMika Westerberg u16 arg = 0; 9686e08d6bbSMika Westerberg u32 term; 9696e08d6bbSMika Westerberg 9700bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9716e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 9726e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 9730bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9746e08d6bbSMika Westerberg 9756e08d6bbSMika Westerberg term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 9766e08d6bbSMika Westerberg 9776e08d6bbSMika Westerberg switch (param) { 9786e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 9796e08d6bbSMika Westerberg if (term) 9806e08d6bbSMika Westerberg return -EINVAL; 9816e08d6bbSMika Westerberg break; 9826e08d6bbSMika Westerberg 9836e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 9846e08d6bbSMika Westerberg if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 9856e08d6bbSMika Westerberg return -EINVAL; 9866e08d6bbSMika Westerberg 9876e08d6bbSMika Westerberg switch (term) { 9886e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 9896e08d6bbSMika Westerberg arg = 20000; 9906e08d6bbSMika Westerberg break; 9916e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 9926e08d6bbSMika Westerberg arg = 5000; 9936e08d6bbSMika Westerberg break; 9946e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_1K: 9956e08d6bbSMika Westerberg arg = 1000; 9966e08d6bbSMika Westerberg break; 9976e08d6bbSMika Westerberg } 9986e08d6bbSMika Westerberg 9996e08d6bbSMika Westerberg break; 10006e08d6bbSMika Westerberg 10016e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 10026e08d6bbSMika Westerberg if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 10036e08d6bbSMika Westerberg return -EINVAL; 10046e08d6bbSMika Westerberg 10056e08d6bbSMika Westerberg switch (term) { 10066e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 10076e08d6bbSMika Westerberg arg = 20000; 10086e08d6bbSMika Westerberg break; 10096e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 10106e08d6bbSMika Westerberg arg = 5000; 10116e08d6bbSMika Westerberg break; 10126e08d6bbSMika Westerberg } 10136e08d6bbSMika Westerberg 10146e08d6bbSMika Westerberg break; 10156e08d6bbSMika Westerberg 10166e08d6bbSMika Westerberg case PIN_CONFIG_DRIVE_OPEN_DRAIN: 10176e08d6bbSMika Westerberg if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 10186e08d6bbSMika Westerberg return -EINVAL; 10196e08d6bbSMika Westerberg break; 10206e08d6bbSMika Westerberg 10216e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 10226e08d6bbSMika Westerberg u32 cfg; 10236e08d6bbSMika Westerberg 10246e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 10256e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 10266e08d6bbSMika Westerberg if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 10276e08d6bbSMika Westerberg return -EINVAL; 10286e08d6bbSMika Westerberg 10296e08d6bbSMika Westerberg break; 10306e08d6bbSMika Westerberg } 10316e08d6bbSMika Westerberg 10326e08d6bbSMika Westerberg default: 10336e08d6bbSMika Westerberg return -ENOTSUPP; 10346e08d6bbSMika Westerberg } 10356e08d6bbSMika Westerberg 10366e08d6bbSMika Westerberg *config = pinconf_to_config_packed(param, arg); 10376e08d6bbSMika Westerberg return 0; 10386e08d6bbSMika Westerberg } 10396e08d6bbSMika Westerberg 10406e08d6bbSMika Westerberg static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 104158957d2eSMika Westerberg enum pin_config_param param, u32 arg) 10426e08d6bbSMika Westerberg { 10436e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 10446e08d6bbSMika Westerberg unsigned long flags; 10456e08d6bbSMika Westerberg u32 ctrl0, pull; 10466e08d6bbSMika Westerberg 10470bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 10486e08d6bbSMika Westerberg ctrl0 = readl(reg); 10496e08d6bbSMika Westerberg 10506e08d6bbSMika Westerberg switch (param) { 10516e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 10526e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10536e08d6bbSMika Westerberg break; 10546e08d6bbSMika Westerberg 10556e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 10566e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10576e08d6bbSMika Westerberg 10586e08d6bbSMika Westerberg switch (arg) { 10596e08d6bbSMika Westerberg case 1000: 10606e08d6bbSMika Westerberg /* For 1k there is only pull up */ 10616e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 10626e08d6bbSMika Westerberg break; 10636e08d6bbSMika Westerberg case 5000: 10646e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 10656e08d6bbSMika Westerberg break; 10666e08d6bbSMika Westerberg case 20000: 10676e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 10686e08d6bbSMika Westerberg break; 10696e08d6bbSMika Westerberg default: 10700bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10716e08d6bbSMika Westerberg return -EINVAL; 10726e08d6bbSMika Westerberg } 10736e08d6bbSMika Westerberg 10746e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 10756e08d6bbSMika Westerberg break; 10766e08d6bbSMika Westerberg 10776e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 10786e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10796e08d6bbSMika Westerberg 10806e08d6bbSMika Westerberg switch (arg) { 10816e08d6bbSMika Westerberg case 5000: 10826e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 10836e08d6bbSMika Westerberg break; 10846e08d6bbSMika Westerberg case 20000: 10856e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 10866e08d6bbSMika Westerberg break; 10876e08d6bbSMika Westerberg default: 10880bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10896e08d6bbSMika Westerberg return -EINVAL; 10906e08d6bbSMika Westerberg } 10916e08d6bbSMika Westerberg 10926e08d6bbSMika Westerberg ctrl0 |= pull; 10936e08d6bbSMika Westerberg break; 10946e08d6bbSMika Westerberg 10956e08d6bbSMika Westerberg default: 10960bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10976e08d6bbSMika Westerberg return -EINVAL; 10986e08d6bbSMika Westerberg } 10996e08d6bbSMika Westerberg 11006e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 11010bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11026e08d6bbSMika Westerberg 11036e08d6bbSMika Westerberg return 0; 11046e08d6bbSMika Westerberg } 11056e08d6bbSMika Westerberg 1106ccdf81d0SDan O'Donovan static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1107ccdf81d0SDan O'Donovan bool enable) 1108ccdf81d0SDan O'Donovan { 1109ccdf81d0SDan O'Donovan void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1110ccdf81d0SDan O'Donovan unsigned long flags; 1111ccdf81d0SDan O'Donovan u32 ctrl1; 1112ccdf81d0SDan O'Donovan 1113ccdf81d0SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1114ccdf81d0SDan O'Donovan ctrl1 = readl(reg); 1115ccdf81d0SDan O'Donovan 1116ccdf81d0SDan O'Donovan if (enable) 1117ccdf81d0SDan O'Donovan ctrl1 |= CHV_PADCTRL1_ODEN; 1118ccdf81d0SDan O'Donovan else 1119ccdf81d0SDan O'Donovan ctrl1 &= ~CHV_PADCTRL1_ODEN; 1120ccdf81d0SDan O'Donovan 1121ccdf81d0SDan O'Donovan chv_writel(ctrl1, reg); 1122ccdf81d0SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1123ccdf81d0SDan O'Donovan 1124ccdf81d0SDan O'Donovan return 0; 1125ccdf81d0SDan O'Donovan } 1126ccdf81d0SDan O'Donovan 11276e08d6bbSMika Westerberg static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 11286e08d6bbSMika Westerberg unsigned long *configs, unsigned nconfigs) 11296e08d6bbSMika Westerberg { 11306e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 11316e08d6bbSMika Westerberg enum pin_config_param param; 11326e08d6bbSMika Westerberg int i, ret; 113358957d2eSMika Westerberg u32 arg; 11346e08d6bbSMika Westerberg 11356e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, pin)) 11366e08d6bbSMika Westerberg return -EBUSY; 11376e08d6bbSMika Westerberg 11386e08d6bbSMika Westerberg for (i = 0; i < nconfigs; i++) { 11396e08d6bbSMika Westerberg param = pinconf_to_config_param(configs[i]); 11406e08d6bbSMika Westerberg arg = pinconf_to_config_argument(configs[i]); 11416e08d6bbSMika Westerberg 11426e08d6bbSMika Westerberg switch (param) { 11436e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 11446e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 11456e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 11466e08d6bbSMika Westerberg ret = chv_config_set_pull(pctrl, pin, param, arg); 11476e08d6bbSMika Westerberg if (ret) 11486e08d6bbSMika Westerberg return ret; 11496e08d6bbSMika Westerberg break; 11506e08d6bbSMika Westerberg 1151ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_PUSH_PULL: 1152ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, false); 1153ccdf81d0SDan O'Donovan if (ret) 1154ccdf81d0SDan O'Donovan return ret; 1155ccdf81d0SDan O'Donovan break; 1156ccdf81d0SDan O'Donovan 1157ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1158ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, true); 1159ccdf81d0SDan O'Donovan if (ret) 1160ccdf81d0SDan O'Donovan return ret; 1161ccdf81d0SDan O'Donovan break; 1162ccdf81d0SDan O'Donovan 11636e08d6bbSMika Westerberg default: 11646e08d6bbSMika Westerberg return -ENOTSUPP; 11656e08d6bbSMika Westerberg } 11666e08d6bbSMika Westerberg 11676e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 11686e08d6bbSMika Westerberg param, arg); 11696e08d6bbSMika Westerberg } 11706e08d6bbSMika Westerberg 11716e08d6bbSMika Westerberg return 0; 11726e08d6bbSMika Westerberg } 11736e08d6bbSMika Westerberg 117477401d7fSDan O'Donovan static int chv_config_group_get(struct pinctrl_dev *pctldev, 117577401d7fSDan O'Donovan unsigned int group, 117677401d7fSDan O'Donovan unsigned long *config) 117777401d7fSDan O'Donovan { 117877401d7fSDan O'Donovan const unsigned int *pins; 117977401d7fSDan O'Donovan unsigned int npins; 118077401d7fSDan O'Donovan int ret; 118177401d7fSDan O'Donovan 118277401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 118377401d7fSDan O'Donovan if (ret) 118477401d7fSDan O'Donovan return ret; 118577401d7fSDan O'Donovan 118677401d7fSDan O'Donovan ret = chv_config_get(pctldev, pins[0], config); 118777401d7fSDan O'Donovan if (ret) 118877401d7fSDan O'Donovan return ret; 118977401d7fSDan O'Donovan 119077401d7fSDan O'Donovan return 0; 119177401d7fSDan O'Donovan } 119277401d7fSDan O'Donovan 119377401d7fSDan O'Donovan static int chv_config_group_set(struct pinctrl_dev *pctldev, 119477401d7fSDan O'Donovan unsigned int group, unsigned long *configs, 119577401d7fSDan O'Donovan unsigned int num_configs) 119677401d7fSDan O'Donovan { 119777401d7fSDan O'Donovan const unsigned int *pins; 119877401d7fSDan O'Donovan unsigned int npins; 119977401d7fSDan O'Donovan int i, ret; 120077401d7fSDan O'Donovan 120177401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 120277401d7fSDan O'Donovan if (ret) 120377401d7fSDan O'Donovan return ret; 120477401d7fSDan O'Donovan 120577401d7fSDan O'Donovan for (i = 0; i < npins; i++) { 120677401d7fSDan O'Donovan ret = chv_config_set(pctldev, pins[i], configs, num_configs); 120777401d7fSDan O'Donovan if (ret) 120877401d7fSDan O'Donovan return ret; 120977401d7fSDan O'Donovan } 121077401d7fSDan O'Donovan 121177401d7fSDan O'Donovan return 0; 121277401d7fSDan O'Donovan } 121377401d7fSDan O'Donovan 12146e08d6bbSMika Westerberg static const struct pinconf_ops chv_pinconf_ops = { 12156e08d6bbSMika Westerberg .is_generic = true, 12166e08d6bbSMika Westerberg .pin_config_set = chv_config_set, 12176e08d6bbSMika Westerberg .pin_config_get = chv_config_get, 121877401d7fSDan O'Donovan .pin_config_group_get = chv_config_group_get, 121977401d7fSDan O'Donovan .pin_config_group_set = chv_config_group_set, 12206e08d6bbSMika Westerberg }; 12216e08d6bbSMika Westerberg 12226e08d6bbSMika Westerberg static struct pinctrl_desc chv_pinctrl_desc = { 12236e08d6bbSMika Westerberg .pctlops = &chv_pinctrl_ops, 12246e08d6bbSMika Westerberg .pmxops = &chv_pinmux_ops, 12256e08d6bbSMika Westerberg .confops = &chv_pinconf_ops, 12266e08d6bbSMika Westerberg .owner = THIS_MODULE, 12276e08d6bbSMika Westerberg }; 12286e08d6bbSMika Westerberg 12296e08d6bbSMika Westerberg static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 12306e08d6bbSMika Westerberg { 12310587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12324585b000SMika Westerberg unsigned long flags; 12336e08d6bbSMika Westerberg u32 ctrl0, cfg; 12346e08d6bbSMika Westerberg 12350bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 123603c4749dSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 12370bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12386e08d6bbSMika Westerberg 12396e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 12406e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 12416e08d6bbSMika Westerberg 12426e08d6bbSMika Westerberg if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 12436e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 12446e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 12456e08d6bbSMika Westerberg } 12466e08d6bbSMika Westerberg 12476e08d6bbSMika Westerberg static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 12486e08d6bbSMika Westerberg { 12490587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12506e08d6bbSMika Westerberg unsigned long flags; 12516e08d6bbSMika Westerberg void __iomem *reg; 12526e08d6bbSMika Westerberg u32 ctrl0; 12536e08d6bbSMika Westerberg 12540bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12556e08d6bbSMika Westerberg 125603c4749dSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 12576e08d6bbSMika Westerberg ctrl0 = readl(reg); 12586e08d6bbSMika Westerberg 12596e08d6bbSMika Westerberg if (value) 12606e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 12616e08d6bbSMika Westerberg else 12626e08d6bbSMika Westerberg ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 12636e08d6bbSMika Westerberg 12646e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 12656e08d6bbSMika Westerberg 12660bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12676e08d6bbSMika Westerberg } 12686e08d6bbSMika Westerberg 12696e08d6bbSMika Westerberg static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 12706e08d6bbSMika Westerberg { 12710587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12726e08d6bbSMika Westerberg u32 ctrl0, direction; 12734585b000SMika Westerberg unsigned long flags; 12746e08d6bbSMika Westerberg 12750bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 127603c4749dSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 12770bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12786e08d6bbSMika Westerberg 12796e08d6bbSMika Westerberg direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 12806e08d6bbSMika Westerberg direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 12816e08d6bbSMika Westerberg 12826e08d6bbSMika Westerberg return direction != CHV_PADCTRL0_GPIOCFG_GPO; 12836e08d6bbSMika Westerberg } 12846e08d6bbSMika Westerberg 12856e08d6bbSMika Westerberg static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 12866e08d6bbSMika Westerberg { 12876e08d6bbSMika Westerberg return pinctrl_gpio_direction_input(chip->base + offset); 12886e08d6bbSMika Westerberg } 12896e08d6bbSMika Westerberg 12906e08d6bbSMika Westerberg static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 12916e08d6bbSMika Westerberg int value) 12926e08d6bbSMika Westerberg { 1293549e783fSqipeng.zha chv_gpio_set(chip, offset, value); 12946e08d6bbSMika Westerberg return pinctrl_gpio_direction_output(chip->base + offset); 12956e08d6bbSMika Westerberg } 12966e08d6bbSMika Westerberg 12976e08d6bbSMika Westerberg static const struct gpio_chip chv_gpio_chip = { 12986e08d6bbSMika Westerberg .owner = THIS_MODULE, 129998c85d58SJonas Gorski .request = gpiochip_generic_request, 130098c85d58SJonas Gorski .free = gpiochip_generic_free, 13016e08d6bbSMika Westerberg .get_direction = chv_gpio_get_direction, 13026e08d6bbSMika Westerberg .direction_input = chv_gpio_direction_input, 13036e08d6bbSMika Westerberg .direction_output = chv_gpio_direction_output, 13046e08d6bbSMika Westerberg .get = chv_gpio_get, 13056e08d6bbSMika Westerberg .set = chv_gpio_set, 13066e08d6bbSMika Westerberg }; 13076e08d6bbSMika Westerberg 13086e08d6bbSMika Westerberg static void chv_gpio_irq_ack(struct irq_data *d) 13096e08d6bbSMika Westerberg { 13106e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13110587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 131203c4749dSMika Westerberg int pin = irqd_to_hwirq(d); 13136e08d6bbSMika Westerberg u32 intr_line; 13146e08d6bbSMika Westerberg 13150bd50d71SDan O'Donovan raw_spin_lock(&chv_lock); 13166e08d6bbSMika Westerberg 13176e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13186e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13196e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13206e08d6bbSMika Westerberg chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 13216e08d6bbSMika Westerberg 13220bd50d71SDan O'Donovan raw_spin_unlock(&chv_lock); 13236e08d6bbSMika Westerberg } 13246e08d6bbSMika Westerberg 13256e08d6bbSMika Westerberg static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 13266e08d6bbSMika Westerberg { 13276e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13280587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 132903c4749dSMika Westerberg int pin = irqd_to_hwirq(d); 13306e08d6bbSMika Westerberg u32 value, intr_line; 13316e08d6bbSMika Westerberg unsigned long flags; 13326e08d6bbSMika Westerberg 13330bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 13346e08d6bbSMika Westerberg 13356e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13366e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13376e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13386e08d6bbSMika Westerberg 13396e08d6bbSMika Westerberg value = readl(pctrl->regs + CHV_INTMASK); 13406e08d6bbSMika Westerberg if (mask) 13416e08d6bbSMika Westerberg value &= ~BIT(intr_line); 13426e08d6bbSMika Westerberg else 13436e08d6bbSMika Westerberg value |= BIT(intr_line); 13446e08d6bbSMika Westerberg chv_writel(value, pctrl->regs + CHV_INTMASK); 13456e08d6bbSMika Westerberg 13460bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 13476e08d6bbSMika Westerberg } 13486e08d6bbSMika Westerberg 13496e08d6bbSMika Westerberg static void chv_gpio_irq_mask(struct irq_data *d) 13506e08d6bbSMika Westerberg { 13516e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, true); 13526e08d6bbSMika Westerberg } 13536e08d6bbSMika Westerberg 13546e08d6bbSMika Westerberg static void chv_gpio_irq_unmask(struct irq_data *d) 13556e08d6bbSMika Westerberg { 13566e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, false); 13576e08d6bbSMika Westerberg } 13586e08d6bbSMika Westerberg 1359e6c906deSMika Westerberg static unsigned chv_gpio_irq_startup(struct irq_data *d) 1360e6c906deSMika Westerberg { 1361e6c906deSMika Westerberg /* 1362e6c906deSMika Westerberg * Check if the interrupt has been requested with 0 as triggering 1363e6c906deSMika Westerberg * type. In that case it is assumed that the current values 1364e6c906deSMika Westerberg * programmed to the hardware are used (e.g BIOS configured 1365e6c906deSMika Westerberg * defaults). 1366e6c906deSMika Westerberg * 1367e6c906deSMika Westerberg * In that case ->irq_set_type() will never be called so we need to 1368e6c906deSMika Westerberg * read back the values from hardware now, set correct flow handler 1369e6c906deSMika Westerberg * and update mappings before the interrupt is being used. 1370e6c906deSMika Westerberg */ 1371e6c906deSMika Westerberg if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1372e6c906deSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13730587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 137403c4749dSMika Westerberg unsigned pin = irqd_to_hwirq(d); 1375e6c906deSMika Westerberg irq_flow_handler_t handler; 1376e6c906deSMika Westerberg unsigned long flags; 1377e6c906deSMika Westerberg u32 intsel, value; 1378e6c906deSMika Westerberg 13790bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1380e6c906deSMika Westerberg intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1381e6c906deSMika Westerberg intsel &= CHV_PADCTRL0_INTSEL_MASK; 1382e6c906deSMika Westerberg intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1383e6c906deSMika Westerberg 1384e6c906deSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1385e6c906deSMika Westerberg if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1386e6c906deSMika Westerberg handler = handle_level_irq; 1387e6c906deSMika Westerberg else 1388e6c906deSMika Westerberg handler = handle_edge_irq; 1389e6c906deSMika Westerberg 1390e6c906deSMika Westerberg if (!pctrl->intr_lines[intsel]) { 1391a4e3f783SThomas Gleixner irq_set_handler_locked(d, handler); 139203c4749dSMika Westerberg pctrl->intr_lines[intsel] = pin; 1393e6c906deSMika Westerberg } 13940bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1395e6c906deSMika Westerberg } 1396e6c906deSMika Westerberg 1397e6c906deSMika Westerberg chv_gpio_irq_unmask(d); 1398e6c906deSMika Westerberg return 0; 1399e6c906deSMika Westerberg } 1400e6c906deSMika Westerberg 14016e08d6bbSMika Westerberg static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 14026e08d6bbSMika Westerberg { 14036e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 14040587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 140503c4749dSMika Westerberg unsigned pin = irqd_to_hwirq(d); 14066e08d6bbSMika Westerberg unsigned long flags; 14076e08d6bbSMika Westerberg u32 value; 14086e08d6bbSMika Westerberg 14090bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 14106e08d6bbSMika Westerberg 14116e08d6bbSMika Westerberg /* 14126e08d6bbSMika Westerberg * Pins which can be used as shared interrupt are configured in 14136e08d6bbSMika Westerberg * BIOS. Driver trusts BIOS configurations and assigns different 14146e08d6bbSMika Westerberg * handler according to the irq type. 14156e08d6bbSMika Westerberg * 14166e08d6bbSMika Westerberg * Driver needs to save the mapping between each pin and 14176e08d6bbSMika Westerberg * its interrupt line. 14186e08d6bbSMika Westerberg * 1. If the pin cfg is locked in BIOS: 14196e08d6bbSMika Westerberg * Trust BIOS has programmed IntWakeCfg bits correctly, 14206e08d6bbSMika Westerberg * driver just needs to save the mapping. 14216e08d6bbSMika Westerberg * 2. If the pin cfg is not locked in BIOS: 14226e08d6bbSMika Westerberg * Driver programs the IntWakeCfg bits and save the mapping. 14236e08d6bbSMika Westerberg */ 14246e08d6bbSMika Westerberg if (!chv_pad_locked(pctrl, pin)) { 14256e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 14266e08d6bbSMika Westerberg 14276e08d6bbSMika Westerberg value = readl(reg); 14286e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 14296e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 14306e08d6bbSMika Westerberg 14316e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) { 14326e08d6bbSMika Westerberg if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 14336e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 14346e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_RISING) 14356e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_RISING; 14366e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_FALLING) 14376e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 14386e08d6bbSMika Westerberg } else if (type & IRQ_TYPE_LEVEL_MASK) { 14396e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 14406e08d6bbSMika Westerberg if (type & IRQ_TYPE_LEVEL_LOW) 14416e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_RXDATA; 14426e08d6bbSMika Westerberg } 14436e08d6bbSMika Westerberg 14446e08d6bbSMika Westerberg chv_writel(value, reg); 14456e08d6bbSMika Westerberg } 14466e08d6bbSMika Westerberg 14476e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 14486e08d6bbSMika Westerberg value &= CHV_PADCTRL0_INTSEL_MASK; 14496e08d6bbSMika Westerberg value >>= CHV_PADCTRL0_INTSEL_SHIFT; 14506e08d6bbSMika Westerberg 145103c4749dSMika Westerberg pctrl->intr_lines[value] = pin; 14526e08d6bbSMika Westerberg 14536e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) 1454a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 14556e08d6bbSMika Westerberg else if (type & IRQ_TYPE_LEVEL_MASK) 1456a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 14576e08d6bbSMika Westerberg 14580bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 14596e08d6bbSMika Westerberg 14606e08d6bbSMika Westerberg return 0; 14616e08d6bbSMika Westerberg } 14626e08d6bbSMika Westerberg 14636e08d6bbSMika Westerberg static struct irq_chip chv_gpio_irqchip = { 14646e08d6bbSMika Westerberg .name = "chv-gpio", 1465e6c906deSMika Westerberg .irq_startup = chv_gpio_irq_startup, 14666e08d6bbSMika Westerberg .irq_ack = chv_gpio_irq_ack, 14676e08d6bbSMika Westerberg .irq_mask = chv_gpio_irq_mask, 14686e08d6bbSMika Westerberg .irq_unmask = chv_gpio_irq_unmask, 14696e08d6bbSMika Westerberg .irq_set_type = chv_gpio_irq_type, 14706e08d6bbSMika Westerberg .flags = IRQCHIP_SKIP_SET_WAKE, 14716e08d6bbSMika Westerberg }; 14726e08d6bbSMika Westerberg 1473bd0b9ac4SThomas Gleixner static void chv_gpio_irq_handler(struct irq_desc *desc) 14746e08d6bbSMika Westerberg { 14756e08d6bbSMika Westerberg struct gpio_chip *gc = irq_desc_get_handler_data(desc); 14760587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 14775663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 14786e08d6bbSMika Westerberg unsigned long pending; 14796e08d6bbSMika Westerberg u32 intr_line; 14806e08d6bbSMika Westerberg 14816e08d6bbSMika Westerberg chained_irq_enter(chip, desc); 14826e08d6bbSMika Westerberg 14836e08d6bbSMika Westerberg pending = readl(pctrl->regs + CHV_INTSTAT); 148447c950d1SMika Westerberg for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { 14856e08d6bbSMika Westerberg unsigned irq, offset; 14866e08d6bbSMika Westerberg 14876e08d6bbSMika Westerberg offset = pctrl->intr_lines[intr_line]; 1488f0fbe7bcSThierry Reding irq = irq_find_mapping(gc->irq.domain, offset); 14896e08d6bbSMika Westerberg generic_handle_irq(irq); 14906e08d6bbSMika Westerberg } 14916e08d6bbSMika Westerberg 14926e08d6bbSMika Westerberg chained_irq_exit(chip, desc); 14936e08d6bbSMika Westerberg } 14946e08d6bbSMika Westerberg 149570365027SMika Westerberg /* 149670365027SMika Westerberg * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 149770365027SMika Westerberg * tables. Since we leave GPIOs that are not capable of generating 149870365027SMika Westerberg * interrupts out of the irqdomain the numbering will be different and 149970365027SMika Westerberg * cause devices using the hardcoded IRQ numbers fail. In order not to 150070365027SMika Westerberg * break such machines we will only mask pins from irqdomain if the machine 150170365027SMika Westerberg * is not listed below. 150270365027SMika Westerberg */ 150370365027SMika Westerberg static const struct dmi_system_id chv_no_valid_mask[] = { 150470365027SMika Westerberg /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 15052a8209faSMika Westerberg { 15062a8209faSMika Westerberg .ident = "Intel_Strago based Chromebooks (All models)", 150770365027SMika Westerberg .matches = { 150870365027SMika Westerberg DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 15092a8209faSMika Westerberg DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 151086c5dd68SDmitry Torokhov DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 15112a8209faSMika Westerberg }, 15122a8209faSMika Westerberg }, 15132a8209faSMika Westerberg { 15142d80bd3fSAndy Shevchenko .ident = "HP Chromebook 11 G5 (Setzer)", 15152d80bd3fSAndy Shevchenko .matches = { 15162d80bd3fSAndy Shevchenko DMI_MATCH(DMI_SYS_VENDOR, "HP"), 15172d80bd3fSAndy Shevchenko DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 151886c5dd68SDmitry Torokhov DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 15192d80bd3fSAndy Shevchenko }, 15202d80bd3fSAndy Shevchenko }, 15212d80bd3fSAndy Shevchenko { 15222a8209faSMika Westerberg .ident = "Acer Chromebook R11 (Cyan)", 15232a8209faSMika Westerberg .matches = { 15242a8209faSMika Westerberg DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 15252a8209faSMika Westerberg DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 152686c5dd68SDmitry Torokhov DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 15272a8209faSMika Westerberg }, 15282a8209faSMika Westerberg }, 15292a8209faSMika Westerberg { 15302a8209faSMika Westerberg .ident = "Samsung Chromebook 3 (Celes)", 15312a8209faSMika Westerberg .matches = { 15322a8209faSMika Westerberg DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 15332a8209faSMika Westerberg DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 153486c5dd68SDmitry Torokhov DMI_MATCH(DMI_BOARD_VERSION, "1.0"), 153570365027SMika Westerberg }, 1536a9de080bSWei Yongjun }, 1537a9de080bSWei Yongjun {} 153870365027SMika Westerberg }; 153970365027SMika Westerberg 15406e08d6bbSMika Westerberg static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 15416e08d6bbSMika Westerberg { 15426e08d6bbSMika Westerberg const struct chv_gpio_pinrange *range; 15436e08d6bbSMika Westerberg struct gpio_chip *chip = &pctrl->chip; 154470365027SMika Westerberg bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 154503c4749dSMika Westerberg const struct chv_community *community = pctrl->community; 154603c4749dSMika Westerberg int ret, i, irq_base; 15476e08d6bbSMika Westerberg 15486e08d6bbSMika Westerberg *chip = chv_gpio_chip; 15496e08d6bbSMika Westerberg 155003c4749dSMika Westerberg chip->ngpio = community->pins[community->npins - 1].number + 1; 15516e08d6bbSMika Westerberg chip->label = dev_name(pctrl->dev); 155258383c78SLinus Walleij chip->parent = pctrl->dev; 15536e08d6bbSMika Westerberg chip->base = -1; 1554dc7b0387SThierry Reding chip->irq.need_valid_mask = need_valid_mask; 15556e08d6bbSMika Westerberg 1556d1073418SMika Westerberg ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 15576e08d6bbSMika Westerberg if (ret) { 15586e08d6bbSMika Westerberg dev_err(pctrl->dev, "Failed to register gpiochip\n"); 15596e08d6bbSMika Westerberg return ret; 15606e08d6bbSMika Westerberg } 15616e08d6bbSMika Westerberg 156203c4749dSMika Westerberg for (i = 0; i < community->ngpio_ranges; i++) { 156303c4749dSMika Westerberg range = &community->gpio_ranges[i]; 156403c4749dSMika Westerberg ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), 156503c4749dSMika Westerberg range->base, range->base, 156603c4749dSMika Westerberg range->npins); 15676e08d6bbSMika Westerberg if (ret) { 15686e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1569d1073418SMika Westerberg return ret; 15706e08d6bbSMika Westerberg } 15716e08d6bbSMika Westerberg } 15726e08d6bbSMika Westerberg 157347c950d1SMika Westerberg /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 157403c4749dSMika Westerberg for (i = 0; i < community->npins; i++) { 157547c950d1SMika Westerberg const struct pinctrl_pin_desc *desc; 157647c950d1SMika Westerberg u32 intsel; 157747c950d1SMika Westerberg 157803c4749dSMika Westerberg desc = &community->pins[i]; 157947c950d1SMika Westerberg 158047c950d1SMika Westerberg intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); 158147c950d1SMika Westerberg intsel &= CHV_PADCTRL0_INTSEL_MASK; 158247c950d1SMika Westerberg intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 158347c950d1SMika Westerberg 158403c4749dSMika Westerberg if (need_valid_mask && intsel >= community->nirqs) 1585dc7b0387SThierry Reding clear_bit(i, chip->irq.valid_mask); 158647c950d1SMika Westerberg } 158747c950d1SMika Westerberg 1588d2b3c353SMika Westerberg /* 1589d2b3c353SMika Westerberg * The same set of machines in chv_no_valid_mask[] have incorrectly 1590d2b3c353SMika Westerberg * configured GPIOs that generate spurious interrupts so we use 1591d2b3c353SMika Westerberg * this same list to apply another quirk for them. 1592d2b3c353SMika Westerberg * 1593d2b3c353SMika Westerberg * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1594d2b3c353SMika Westerberg */ 1595d2b3c353SMika Westerberg if (!need_valid_mask) { 1596d2b3c353SMika Westerberg /* 1597d2b3c353SMika Westerberg * Mask all interrupts the community is able to generate 1598d2b3c353SMika Westerberg * but leave the ones that can only generate GPEs unmasked. 1599d2b3c353SMika Westerberg */ 1600d2b3c353SMika Westerberg chv_writel(GENMASK(31, pctrl->community->nirqs), 1601d2b3c353SMika Westerberg pctrl->regs + CHV_INTMASK); 1602d2b3c353SMika Westerberg } 1603d2b3c353SMika Westerberg 1604bcb48ccaSMika Westerberg /* Clear all interrupts */ 16056e08d6bbSMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 16066e08d6bbSMika Westerberg 1607845e405eSGrygorii Strashko if (!need_valid_mask) { 1608845e405eSGrygorii Strashko irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, 160983b9dc11SMika Westerberg community->npins, NUMA_NO_NODE); 1610845e405eSGrygorii Strashko if (irq_base < 0) { 1611845e405eSGrygorii Strashko dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); 1612845e405eSGrygorii Strashko return irq_base; 1613845e405eSGrygorii Strashko } 1614845e405eSGrygorii Strashko } 1615845e405eSGrygorii Strashko 161683b9dc11SMika Westerberg ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1617bcb48ccaSMika Westerberg handle_bad_irq, IRQ_TYPE_NONE); 16186e08d6bbSMika Westerberg if (ret) { 16196e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1620d1073418SMika Westerberg return ret; 16216e08d6bbSMika Westerberg } 16226e08d6bbSMika Westerberg 162383b9dc11SMika Westerberg if (!need_valid_mask) { 162483b9dc11SMika Westerberg for (i = 0; i < community->ngpio_ranges; i++) { 162583b9dc11SMika Westerberg range = &community->gpio_ranges[i]; 162683b9dc11SMika Westerberg 162783b9dc11SMika Westerberg irq_domain_associate_many(chip->irq.domain, irq_base, 162883b9dc11SMika Westerberg range->base, range->npins); 162983b9dc11SMika Westerberg irq_base += range->npins; 163083b9dc11SMika Westerberg } 163183b9dc11SMika Westerberg } 163283b9dc11SMika Westerberg 16336e08d6bbSMika Westerberg gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 16346e08d6bbSMika Westerberg chv_gpio_irq_handler); 16356e08d6bbSMika Westerberg return 0; 16366e08d6bbSMika Westerberg } 16376e08d6bbSMika Westerberg 1638a0b02859SHans de Goede static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1639a0b02859SHans de Goede acpi_physical_address address, u32 bits, u64 *value, 1640a0b02859SHans de Goede void *handler_context, void *region_context) 1641a0b02859SHans de Goede { 1642a0b02859SHans de Goede struct chv_pinctrl *pctrl = region_context; 1643a0b02859SHans de Goede unsigned long flags; 1644a0b02859SHans de Goede acpi_status ret = AE_OK; 1645a0b02859SHans de Goede 1646a0b02859SHans de Goede raw_spin_lock_irqsave(&chv_lock, flags); 1647a0b02859SHans de Goede 1648a0b02859SHans de Goede if (function == ACPI_WRITE) 1649a0b02859SHans de Goede chv_writel((u32)(*value), pctrl->regs + (u32)address); 1650a0b02859SHans de Goede else if (function == ACPI_READ) 1651a0b02859SHans de Goede *value = readl(pctrl->regs + (u32)address); 1652a0b02859SHans de Goede else 1653a0b02859SHans de Goede ret = AE_BAD_PARAMETER; 1654a0b02859SHans de Goede 1655a0b02859SHans de Goede raw_spin_unlock_irqrestore(&chv_lock, flags); 1656a0b02859SHans de Goede 1657a0b02859SHans de Goede return ret; 1658a0b02859SHans de Goede } 1659a0b02859SHans de Goede 16606e08d6bbSMika Westerberg static int chv_pinctrl_probe(struct platform_device *pdev) 16616e08d6bbSMika Westerberg { 16626e08d6bbSMika Westerberg struct chv_pinctrl *pctrl; 16636e08d6bbSMika Westerberg struct acpi_device *adev; 16646e08d6bbSMika Westerberg struct resource *res; 1665a0b02859SHans de Goede acpi_status status; 16666e08d6bbSMika Westerberg int ret, irq, i; 16676e08d6bbSMika Westerberg 16686e08d6bbSMika Westerberg adev = ACPI_COMPANION(&pdev->dev); 16696e08d6bbSMika Westerberg if (!adev) 16706e08d6bbSMika Westerberg return -ENODEV; 16716e08d6bbSMika Westerberg 16726e08d6bbSMika Westerberg pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 16736e08d6bbSMika Westerberg if (!pctrl) 16746e08d6bbSMika Westerberg return -ENOMEM; 16756e08d6bbSMika Westerberg 16766e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 16776e08d6bbSMika Westerberg if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 16786e08d6bbSMika Westerberg pctrl->community = chv_communities[i]; 16796e08d6bbSMika Westerberg break; 16806e08d6bbSMika Westerberg } 16816e08d6bbSMika Westerberg if (i == ARRAY_SIZE(chv_communities)) 16826e08d6bbSMika Westerberg return -ENODEV; 16836e08d6bbSMika Westerberg 16846e08d6bbSMika Westerberg pctrl->dev = &pdev->dev; 16856e08d6bbSMika Westerberg 16869eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 16879eb457b5SMika Westerberg pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 16889eb457b5SMika Westerberg pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 16899eb457b5SMika Westerberg GFP_KERNEL); 16909eb457b5SMika Westerberg if (!pctrl->saved_pin_context) 16919eb457b5SMika Westerberg return -ENOMEM; 16929eb457b5SMika Westerberg #endif 16939eb457b5SMika Westerberg 16946e08d6bbSMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 16956e08d6bbSMika Westerberg pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 16966e08d6bbSMika Westerberg if (IS_ERR(pctrl->regs)) 16976e08d6bbSMika Westerberg return PTR_ERR(pctrl->regs); 16986e08d6bbSMika Westerberg 16996e08d6bbSMika Westerberg irq = platform_get_irq(pdev, 0); 17006e08d6bbSMika Westerberg if (irq < 0) { 17016e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to get interrupt number\n"); 17026e08d6bbSMika Westerberg return irq; 17036e08d6bbSMika Westerberg } 17046e08d6bbSMika Westerberg 17056e08d6bbSMika Westerberg pctrl->pctldesc = chv_pinctrl_desc; 17066e08d6bbSMika Westerberg pctrl->pctldesc.name = dev_name(&pdev->dev); 17076e08d6bbSMika Westerberg pctrl->pctldesc.pins = pctrl->community->pins; 17086e08d6bbSMika Westerberg pctrl->pctldesc.npins = pctrl->community->npins; 17096e08d6bbSMika Westerberg 17107cf061faSLaxman Dewangan pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 17117cf061faSLaxman Dewangan pctrl); 1712323de9efSMasahiro Yamada if (IS_ERR(pctrl->pctldev)) { 17136e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1714323de9efSMasahiro Yamada return PTR_ERR(pctrl->pctldev); 17156e08d6bbSMika Westerberg } 17166e08d6bbSMika Westerberg 17176e08d6bbSMika Westerberg ret = chv_gpio_probe(pctrl, irq); 17187cf061faSLaxman Dewangan if (ret) 17196e08d6bbSMika Westerberg return ret; 17206e08d6bbSMika Westerberg 1721a0b02859SHans de Goede status = acpi_install_address_space_handler(adev->handle, 1722a0b02859SHans de Goede pctrl->community->acpi_space_id, 1723a0b02859SHans de Goede chv_pinctrl_mmio_access_handler, 1724a0b02859SHans de Goede NULL, pctrl); 1725a0b02859SHans de Goede if (ACPI_FAILURE(status)) 1726a0b02859SHans de Goede dev_err(&pdev->dev, "failed to install ACPI addr space handler\n"); 1727a0b02859SHans de Goede 17286e08d6bbSMika Westerberg platform_set_drvdata(pdev, pctrl); 17296e08d6bbSMika Westerberg 17306e08d6bbSMika Westerberg return 0; 17316e08d6bbSMika Westerberg } 17326e08d6bbSMika Westerberg 1733a0b02859SHans de Goede static int chv_pinctrl_remove(struct platform_device *pdev) 1734a0b02859SHans de Goede { 1735a0b02859SHans de Goede struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1736a0b02859SHans de Goede 1737a0b02859SHans de Goede acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), 1738a0b02859SHans de Goede pctrl->community->acpi_space_id, 1739a0b02859SHans de Goede chv_pinctrl_mmio_access_handler); 1740a0b02859SHans de Goede 1741a0b02859SHans de Goede return 0; 1742a0b02859SHans de Goede } 1743a0b02859SHans de Goede 17449eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 1745d2cdf5dcSMika Westerberg static int chv_pinctrl_suspend_noirq(struct device *dev) 17469eb457b5SMika Westerberg { 17479eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 17489eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 174956211121SMika Westerberg unsigned long flags; 17509eb457b5SMika Westerberg int i; 17519eb457b5SMika Westerberg 175256211121SMika Westerberg raw_spin_lock_irqsave(&chv_lock, flags); 175356211121SMika Westerberg 17549eb457b5SMika Westerberg pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 17559eb457b5SMika Westerberg 17569eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 17579eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 17589eb457b5SMika Westerberg struct chv_pin_context *ctx; 17599eb457b5SMika Westerberg void __iomem *reg; 17609eb457b5SMika Westerberg 17619eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 17629eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 17639eb457b5SMika Westerberg continue; 17649eb457b5SMika Westerberg 17659eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 17669eb457b5SMika Westerberg 17679eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 17689eb457b5SMika Westerberg ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 17699eb457b5SMika Westerberg 17709eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 17719eb457b5SMika Westerberg ctx->padctrl1 = readl(reg); 17729eb457b5SMika Westerberg } 17739eb457b5SMika Westerberg 177456211121SMika Westerberg raw_spin_unlock_irqrestore(&chv_lock, flags); 177556211121SMika Westerberg 17769eb457b5SMika Westerberg return 0; 17779eb457b5SMika Westerberg } 17789eb457b5SMika Westerberg 1779d2cdf5dcSMika Westerberg static int chv_pinctrl_resume_noirq(struct device *dev) 17809eb457b5SMika Westerberg { 17819eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 17829eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 178356211121SMika Westerberg unsigned long flags; 17849eb457b5SMika Westerberg int i; 17859eb457b5SMika Westerberg 178656211121SMika Westerberg raw_spin_lock_irqsave(&chv_lock, flags); 178756211121SMika Westerberg 17889eb457b5SMika Westerberg /* 17899eb457b5SMika Westerberg * Mask all interrupts before restoring per-pin configuration 17909eb457b5SMika Westerberg * registers because we don't know in which state BIOS left them 17919eb457b5SMika Westerberg * upon exiting suspend. 17929eb457b5SMika Westerberg */ 17939eb457b5SMika Westerberg chv_writel(0, pctrl->regs + CHV_INTMASK); 17949eb457b5SMika Westerberg 17959eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 17969eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 17979eb457b5SMika Westerberg const struct chv_pin_context *ctx; 17989eb457b5SMika Westerberg void __iomem *reg; 17999eb457b5SMika Westerberg u32 val; 18009eb457b5SMika Westerberg 18019eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 18029eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 18039eb457b5SMika Westerberg continue; 18049eb457b5SMika Westerberg 18059eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 18069eb457b5SMika Westerberg 18079eb457b5SMika Westerberg /* Only restore if our saved state differs from the current */ 18089eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 18099eb457b5SMika Westerberg val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 18109eb457b5SMika Westerberg if (ctx->padctrl0 != val) { 18119eb457b5SMika Westerberg chv_writel(ctx->padctrl0, reg); 18129eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 18139eb457b5SMika Westerberg desc->number, readl(reg)); 18149eb457b5SMika Westerberg } 18159eb457b5SMika Westerberg 18169eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 18179eb457b5SMika Westerberg val = readl(reg); 18189eb457b5SMika Westerberg if (ctx->padctrl1 != val) { 18199eb457b5SMika Westerberg chv_writel(ctx->padctrl1, reg); 18209eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 18219eb457b5SMika Westerberg desc->number, readl(reg)); 18229eb457b5SMika Westerberg } 18239eb457b5SMika Westerberg } 18249eb457b5SMika Westerberg 18259eb457b5SMika Westerberg /* 18269eb457b5SMika Westerberg * Now that all pins are restored to known state, we can restore 18279eb457b5SMika Westerberg * the interrupt mask register as well. 18289eb457b5SMika Westerberg */ 18299eb457b5SMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 18309eb457b5SMika Westerberg chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 18319eb457b5SMika Westerberg 183256211121SMika Westerberg raw_spin_unlock_irqrestore(&chv_lock, flags); 183356211121SMika Westerberg 18349eb457b5SMika Westerberg return 0; 18359eb457b5SMika Westerberg } 18369eb457b5SMika Westerberg #endif 18379eb457b5SMika Westerberg 18389eb457b5SMika Westerberg static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1839d2cdf5dcSMika Westerberg SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1840d2cdf5dcSMika Westerberg chv_pinctrl_resume_noirq) 18419eb457b5SMika Westerberg }; 18429eb457b5SMika Westerberg 18436e08d6bbSMika Westerberg static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 18446e08d6bbSMika Westerberg { "INT33FF" }, 18456e08d6bbSMika Westerberg { } 18466e08d6bbSMika Westerberg }; 18476e08d6bbSMika Westerberg MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 18486e08d6bbSMika Westerberg 18496e08d6bbSMika Westerberg static struct platform_driver chv_pinctrl_driver = { 18506e08d6bbSMika Westerberg .probe = chv_pinctrl_probe, 1851a0b02859SHans de Goede .remove = chv_pinctrl_remove, 18526e08d6bbSMika Westerberg .driver = { 18536e08d6bbSMika Westerberg .name = "cherryview-pinctrl", 18549eb457b5SMika Westerberg .pm = &chv_pinctrl_pm_ops, 18556e08d6bbSMika Westerberg .acpi_match_table = chv_pinctrl_acpi_match, 18566e08d6bbSMika Westerberg }, 18576e08d6bbSMika Westerberg }; 18586e08d6bbSMika Westerberg 18596e08d6bbSMika Westerberg static int __init chv_pinctrl_init(void) 18606e08d6bbSMika Westerberg { 18616e08d6bbSMika Westerberg return platform_driver_register(&chv_pinctrl_driver); 18626e08d6bbSMika Westerberg } 18636e08d6bbSMika Westerberg subsys_initcall(chv_pinctrl_init); 18646e08d6bbSMika Westerberg 18656e08d6bbSMika Westerberg static void __exit chv_pinctrl_exit(void) 18666e08d6bbSMika Westerberg { 18676e08d6bbSMika Westerberg platform_driver_unregister(&chv_pinctrl_driver); 18686e08d6bbSMika Westerberg } 18696e08d6bbSMika Westerberg module_exit(chv_pinctrl_exit); 18706e08d6bbSMika Westerberg 18716e08d6bbSMika Westerberg MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 18726e08d6bbSMika Westerberg MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 18736e08d6bbSMika Westerberg MODULE_LICENSE("GPL v2"); 1874