16e08d6bbSMika Westerberg /* 26e08d6bbSMika Westerberg * Cherryview/Braswell pinctrl driver 36e08d6bbSMika Westerberg * 46e08d6bbSMika Westerberg * Copyright (C) 2014, Intel Corporation 56e08d6bbSMika Westerberg * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 66e08d6bbSMika Westerberg * 76e08d6bbSMika Westerberg * This driver is based on the original Cherryview GPIO driver by 86e08d6bbSMika Westerberg * Ning Li <ning.li@intel.com> 96e08d6bbSMika Westerberg * Alan Cox <alan@linux.intel.com> 106e08d6bbSMika Westerberg * 116e08d6bbSMika Westerberg * This program is free software; you can redistribute it and/or modify 126e08d6bbSMika Westerberg * it under the terms of the GNU General Public License version 2 as 136e08d6bbSMika Westerberg * published by the Free Software Foundation. 146e08d6bbSMika Westerberg */ 156e08d6bbSMika Westerberg 1670365027SMika Westerberg #include <linux/dmi.h> 176e08d6bbSMika Westerberg #include <linux/kernel.h> 186e08d6bbSMika Westerberg #include <linux/module.h> 196e08d6bbSMika Westerberg #include <linux/init.h> 206e08d6bbSMika Westerberg #include <linux/types.h> 216e08d6bbSMika Westerberg #include <linux/gpio.h> 226e08d6bbSMika Westerberg #include <linux/gpio/driver.h> 236e08d6bbSMika Westerberg #include <linux/acpi.h> 246e08d6bbSMika Westerberg #include <linux/pinctrl/pinctrl.h> 256e08d6bbSMika Westerberg #include <linux/pinctrl/pinmux.h> 266e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf.h> 276e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf-generic.h> 286e08d6bbSMika Westerberg #include <linux/platform_device.h> 296e08d6bbSMika Westerberg 306e08d6bbSMika Westerberg #define CHV_INTSTAT 0x300 316e08d6bbSMika Westerberg #define CHV_INTMASK 0x380 326e08d6bbSMika Westerberg 336e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_OFF 0x4400 346e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_SIZE 0x400 356e08d6bbSMika Westerberg #define MAX_FAMILY_PAD_GPIO_NO 15 366e08d6bbSMika Westerberg #define GPIO_REGS_SIZE 8 376e08d6bbSMika Westerberg 386e08d6bbSMika Westerberg #define CHV_PADCTRL0 0x000 396e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_SHIFT 28 406e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 416e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_UP BIT(23) 426e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_SHIFT 20 436e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 446e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_20K 1 456e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_5K 2 466e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_1K 4 476e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_SHIFT 16 486e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 496e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOEN BIT(15) 506e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 516e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 526e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPIO 0 536e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPO 1 546e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPI 2 556e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_HIZ 3 566e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 576e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 586e08d6bbSMika Westerberg 596e08d6bbSMika Westerberg #define CHV_PADCTRL1 0x004 606e08d6bbSMika Westerberg #define CHV_PADCTRL1_CFGLOCK BIT(31) 616e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_SHIFT 4 626e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 636e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 646e08d6bbSMika Westerberg #define CHV_PADCTRL1_ODEN BIT(3) 656e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 666e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_MASK 7 676e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 686e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_RISING 2 696e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 706e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 716e08d6bbSMika Westerberg 726e08d6bbSMika Westerberg /** 736e08d6bbSMika Westerberg * struct chv_alternate_function - A per group or per pin alternate function 746e08d6bbSMika Westerberg * @pin: Pin number (only used in per pin configs) 756e08d6bbSMika Westerberg * @mode: Mode the pin should be set in 766e08d6bbSMika Westerberg * @invert_oe: Invert OE for this pin 776e08d6bbSMika Westerberg */ 786e08d6bbSMika Westerberg struct chv_alternate_function { 796e08d6bbSMika Westerberg unsigned pin; 806e08d6bbSMika Westerberg u8 mode; 816e08d6bbSMika Westerberg bool invert_oe; 826e08d6bbSMika Westerberg }; 836e08d6bbSMika Westerberg 846e08d6bbSMika Westerberg /** 856e08d6bbSMika Westerberg * struct chv_pincgroup - describes a CHV pin group 866e08d6bbSMika Westerberg * @name: Name of the group 876e08d6bbSMika Westerberg * @pins: An array of pins in this group 886e08d6bbSMika Westerberg * @npins: Number of pins in this group 896e08d6bbSMika Westerberg * @altfunc: Alternate function applied to all pins in this group 906e08d6bbSMika Westerberg * @overrides: Alternate function override per pin or %NULL if not used 916e08d6bbSMika Westerberg * @noverrides: Number of per pin alternate function overrides if 926e08d6bbSMika Westerberg * @overrides != NULL. 936e08d6bbSMika Westerberg */ 946e08d6bbSMika Westerberg struct chv_pingroup { 956e08d6bbSMika Westerberg const char *name; 966e08d6bbSMika Westerberg const unsigned *pins; 976e08d6bbSMika Westerberg size_t npins; 986e08d6bbSMika Westerberg struct chv_alternate_function altfunc; 996e08d6bbSMika Westerberg const struct chv_alternate_function *overrides; 1006e08d6bbSMika Westerberg size_t noverrides; 1016e08d6bbSMika Westerberg }; 1026e08d6bbSMika Westerberg 1036e08d6bbSMika Westerberg /** 1046e08d6bbSMika Westerberg * struct chv_function - A CHV pinmux function 1056e08d6bbSMika Westerberg * @name: Name of the function 1066e08d6bbSMika Westerberg * @groups: An array of groups for this function 1076e08d6bbSMika Westerberg * @ngroups: Number of groups in @groups 1086e08d6bbSMika Westerberg */ 1096e08d6bbSMika Westerberg struct chv_function { 1106e08d6bbSMika Westerberg const char *name; 1116e08d6bbSMika Westerberg const char * const *groups; 1126e08d6bbSMika Westerberg size_t ngroups; 1136e08d6bbSMika Westerberg }; 1146e08d6bbSMika Westerberg 1156e08d6bbSMika Westerberg /** 1166e08d6bbSMika Westerberg * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 1176e08d6bbSMika Westerberg * @base: Start pin number 1186e08d6bbSMika Westerberg * @npins: Number of pins in this range 1196e08d6bbSMika Westerberg */ 1206e08d6bbSMika Westerberg struct chv_gpio_pinrange { 1216e08d6bbSMika Westerberg unsigned base; 1226e08d6bbSMika Westerberg unsigned npins; 1236e08d6bbSMika Westerberg }; 1246e08d6bbSMika Westerberg 1256e08d6bbSMika Westerberg /** 1266e08d6bbSMika Westerberg * struct chv_community - A community specific configuration 1276e08d6bbSMika Westerberg * @uid: ACPI _UID used to match the community 1286e08d6bbSMika Westerberg * @pins: All pins in this community 1296e08d6bbSMika Westerberg * @npins: Number of pins 1306e08d6bbSMika Westerberg * @groups: All groups in this community 1316e08d6bbSMika Westerberg * @ngroups: Number of groups 1326e08d6bbSMika Westerberg * @functions: All functions in this community 1336e08d6bbSMika Westerberg * @nfunctions: Number of functions 1346e08d6bbSMika Westerberg * @ngpios: Number of GPIOs in this community 1356e08d6bbSMika Westerberg * @gpio_ranges: An array of GPIO ranges in this community 1366e08d6bbSMika Westerberg * @ngpio_ranges: Number of GPIO ranges 1376e08d6bbSMika Westerberg * @ngpios: Total number of GPIOs in this community 13847c950d1SMika Westerberg * @nirqs: Total number of IRQs this community can generate 1396e08d6bbSMika Westerberg */ 1406e08d6bbSMika Westerberg struct chv_community { 1416e08d6bbSMika Westerberg const char *uid; 1426e08d6bbSMika Westerberg const struct pinctrl_pin_desc *pins; 1436e08d6bbSMika Westerberg size_t npins; 1446e08d6bbSMika Westerberg const struct chv_pingroup *groups; 1456e08d6bbSMika Westerberg size_t ngroups; 1466e08d6bbSMika Westerberg const struct chv_function *functions; 1476e08d6bbSMika Westerberg size_t nfunctions; 1486e08d6bbSMika Westerberg const struct chv_gpio_pinrange *gpio_ranges; 1496e08d6bbSMika Westerberg size_t ngpio_ranges; 1506e08d6bbSMika Westerberg size_t ngpios; 15147c950d1SMika Westerberg size_t nirqs; 152a0b02859SHans de Goede acpi_adr_space_type acpi_space_id; 1536e08d6bbSMika Westerberg }; 1546e08d6bbSMika Westerberg 1559eb457b5SMika Westerberg struct chv_pin_context { 1569eb457b5SMika Westerberg u32 padctrl0; 1579eb457b5SMika Westerberg u32 padctrl1; 1589eb457b5SMika Westerberg }; 1599eb457b5SMika Westerberg 1606e08d6bbSMika Westerberg /** 1616e08d6bbSMika Westerberg * struct chv_pinctrl - CHV pinctrl private structure 1626e08d6bbSMika Westerberg * @dev: Pointer to the parent device 1636e08d6bbSMika Westerberg * @pctldesc: Pin controller description 1646e08d6bbSMika Westerberg * @pctldev: Pointer to the pin controller device 1656e08d6bbSMika Westerberg * @chip: GPIO chip in this pin controller 1666e08d6bbSMika Westerberg * @regs: MMIO registers 1676e08d6bbSMika Westerberg * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 1686e08d6bbSMika Westerberg * offset (in GPIO number space) 1696e08d6bbSMika Westerberg * @community: Community this pinctrl instance represents 1706e08d6bbSMika Westerberg * 1716e08d6bbSMika Westerberg * The first group in @groups is expected to contain all pins that can be 1726e08d6bbSMika Westerberg * used as GPIOs. 1736e08d6bbSMika Westerberg */ 1746e08d6bbSMika Westerberg struct chv_pinctrl { 1756e08d6bbSMika Westerberg struct device *dev; 1766e08d6bbSMika Westerberg struct pinctrl_desc pctldesc; 1776e08d6bbSMika Westerberg struct pinctrl_dev *pctldev; 1786e08d6bbSMika Westerberg struct gpio_chip chip; 1796e08d6bbSMika Westerberg void __iomem *regs; 1806e08d6bbSMika Westerberg unsigned intr_lines[16]; 1816e08d6bbSMika Westerberg const struct chv_community *community; 1829eb457b5SMika Westerberg u32 saved_intmask; 1839eb457b5SMika Westerberg struct chv_pin_context *saved_pin_context; 1846e08d6bbSMika Westerberg }; 1856e08d6bbSMika Westerberg 1866e08d6bbSMika Westerberg #define ALTERNATE_FUNCTION(p, m, i) \ 1876e08d6bbSMika Westerberg { \ 1886e08d6bbSMika Westerberg .pin = (p), \ 1896e08d6bbSMika Westerberg .mode = (m), \ 1906e08d6bbSMika Westerberg .invert_oe = (i), \ 1916e08d6bbSMika Westerberg } 1926e08d6bbSMika Westerberg 1936e08d6bbSMika Westerberg #define PIN_GROUP(n, p, m, i) \ 1946e08d6bbSMika Westerberg { \ 1956e08d6bbSMika Westerberg .name = (n), \ 1966e08d6bbSMika Westerberg .pins = (p), \ 1976e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 1986e08d6bbSMika Westerberg .altfunc.mode = (m), \ 1996e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 2006e08d6bbSMika Westerberg } 2016e08d6bbSMika Westerberg 2026e08d6bbSMika Westerberg #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 2036e08d6bbSMika Westerberg { \ 2046e08d6bbSMika Westerberg .name = (n), \ 2056e08d6bbSMika Westerberg .pins = (p), \ 2066e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 2076e08d6bbSMika Westerberg .altfunc.mode = (m), \ 2086e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 2096e08d6bbSMika Westerberg .overrides = (o), \ 2106e08d6bbSMika Westerberg .noverrides = ARRAY_SIZE((o)), \ 2116e08d6bbSMika Westerberg } 2126e08d6bbSMika Westerberg 2136e08d6bbSMika Westerberg #define FUNCTION(n, g) \ 2146e08d6bbSMika Westerberg { \ 2156e08d6bbSMika Westerberg .name = (n), \ 2166e08d6bbSMika Westerberg .groups = (g), \ 2176e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE((g)), \ 2186e08d6bbSMika Westerberg } 2196e08d6bbSMika Westerberg 2206e08d6bbSMika Westerberg #define GPIO_PINRANGE(start, end) \ 2216e08d6bbSMika Westerberg { \ 2226e08d6bbSMika Westerberg .base = (start), \ 2236e08d6bbSMika Westerberg .npins = (end) - (start) + 1, \ 2246e08d6bbSMika Westerberg } 2256e08d6bbSMika Westerberg 2266e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southwest_pins[] = { 2276e08d6bbSMika Westerberg PINCTRL_PIN(0, "FST_SPI_D2"), 2286e08d6bbSMika Westerberg PINCTRL_PIN(1, "FST_SPI_D0"), 2296e08d6bbSMika Westerberg PINCTRL_PIN(2, "FST_SPI_CLK"), 2306e08d6bbSMika Westerberg PINCTRL_PIN(3, "FST_SPI_D3"), 2316e08d6bbSMika Westerberg PINCTRL_PIN(4, "FST_SPI_CS1_B"), 2326e08d6bbSMika Westerberg PINCTRL_PIN(5, "FST_SPI_D1"), 2336e08d6bbSMika Westerberg PINCTRL_PIN(6, "FST_SPI_CS0_B"), 2346e08d6bbSMika Westerberg PINCTRL_PIN(7, "FST_SPI_CS2_B"), 2356e08d6bbSMika Westerberg 2366e08d6bbSMika Westerberg PINCTRL_PIN(15, "UART1_RTS_B"), 2376e08d6bbSMika Westerberg PINCTRL_PIN(16, "UART1_RXD"), 2386e08d6bbSMika Westerberg PINCTRL_PIN(17, "UART2_RXD"), 2396e08d6bbSMika Westerberg PINCTRL_PIN(18, "UART1_CTS_B"), 2406e08d6bbSMika Westerberg PINCTRL_PIN(19, "UART2_RTS_B"), 2416e08d6bbSMika Westerberg PINCTRL_PIN(20, "UART1_TXD"), 2426e08d6bbSMika Westerberg PINCTRL_PIN(21, "UART2_TXD"), 2436e08d6bbSMika Westerberg PINCTRL_PIN(22, "UART2_CTS_B"), 2446e08d6bbSMika Westerberg 2456e08d6bbSMika Westerberg PINCTRL_PIN(30, "MF_HDA_CLK"), 2466e08d6bbSMika Westerberg PINCTRL_PIN(31, "MF_HDA_RSTB"), 2476e08d6bbSMika Westerberg PINCTRL_PIN(32, "MF_HDA_SDIO"), 2486e08d6bbSMika Westerberg PINCTRL_PIN(33, "MF_HDA_SDO"), 2496e08d6bbSMika Westerberg PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 2506e08d6bbSMika Westerberg PINCTRL_PIN(35, "MF_HDA_SYNC"), 2516e08d6bbSMika Westerberg PINCTRL_PIN(36, "MF_HDA_SDI1"), 2526e08d6bbSMika Westerberg PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 2536e08d6bbSMika Westerberg 2546e08d6bbSMika Westerberg PINCTRL_PIN(45, "I2C5_SDA"), 2556e08d6bbSMika Westerberg PINCTRL_PIN(46, "I2C4_SDA"), 2566e08d6bbSMika Westerberg PINCTRL_PIN(47, "I2C6_SDA"), 2576e08d6bbSMika Westerberg PINCTRL_PIN(48, "I2C5_SCL"), 2586e08d6bbSMika Westerberg PINCTRL_PIN(49, "I2C_NFC_SDA"), 2596e08d6bbSMika Westerberg PINCTRL_PIN(50, "I2C4_SCL"), 2606e08d6bbSMika Westerberg PINCTRL_PIN(51, "I2C6_SCL"), 2616e08d6bbSMika Westerberg PINCTRL_PIN(52, "I2C_NFC_SCL"), 2626e08d6bbSMika Westerberg 2636e08d6bbSMika Westerberg PINCTRL_PIN(60, "I2C1_SDA"), 2646e08d6bbSMika Westerberg PINCTRL_PIN(61, "I2C0_SDA"), 2656e08d6bbSMika Westerberg PINCTRL_PIN(62, "I2C2_SDA"), 2666e08d6bbSMika Westerberg PINCTRL_PIN(63, "I2C1_SCL"), 2676e08d6bbSMika Westerberg PINCTRL_PIN(64, "I2C3_SDA"), 2686e08d6bbSMika Westerberg PINCTRL_PIN(65, "I2C0_SCL"), 2696e08d6bbSMika Westerberg PINCTRL_PIN(66, "I2C2_SCL"), 2706e08d6bbSMika Westerberg PINCTRL_PIN(67, "I2C3_SCL"), 2716e08d6bbSMika Westerberg 2726e08d6bbSMika Westerberg PINCTRL_PIN(75, "SATA_GP0"), 2736e08d6bbSMika Westerberg PINCTRL_PIN(76, "SATA_GP1"), 2746e08d6bbSMika Westerberg PINCTRL_PIN(77, "SATA_LEDN"), 2756e08d6bbSMika Westerberg PINCTRL_PIN(78, "SATA_GP2"), 2766e08d6bbSMika Westerberg PINCTRL_PIN(79, "MF_SMB_ALERTB"), 2776e08d6bbSMika Westerberg PINCTRL_PIN(80, "SATA_GP3"), 2786e08d6bbSMika Westerberg PINCTRL_PIN(81, "MF_SMB_CLK"), 2796e08d6bbSMika Westerberg PINCTRL_PIN(82, "MF_SMB_DATA"), 2806e08d6bbSMika Westerberg 2816e08d6bbSMika Westerberg PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 2826e08d6bbSMika Westerberg PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 2836e08d6bbSMika Westerberg PINCTRL_PIN(92, "GP_SSP_2_CLK"), 2846e08d6bbSMika Westerberg PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 2856e08d6bbSMika Westerberg PINCTRL_PIN(94, "GP_SSP_2_RXD"), 2866e08d6bbSMika Westerberg PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 2876e08d6bbSMika Westerberg PINCTRL_PIN(96, "GP_SSP_2_FS"), 2886e08d6bbSMika Westerberg PINCTRL_PIN(97, "GP_SSP_2_TXD"), 2896e08d6bbSMika Westerberg }; 2906e08d6bbSMika Westerberg 2916e08d6bbSMika Westerberg static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 2926e08d6bbSMika Westerberg static const unsigned southwest_uart0_pins[] = { 16, 20 }; 2936e08d6bbSMika Westerberg static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 2946e08d6bbSMika Westerberg static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 2956e08d6bbSMika Westerberg static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 2966e08d6bbSMika Westerberg static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 2976e08d6bbSMika Westerberg static const unsigned southwest_lpe_pins[] = { 2986e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 2996e08d6bbSMika Westerberg }; 3006e08d6bbSMika Westerberg static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 3016e08d6bbSMika Westerberg static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 3026e08d6bbSMika Westerberg static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 3036e08d6bbSMika Westerberg static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 3046e08d6bbSMika Westerberg static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 3056e08d6bbSMika Westerberg static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 3066e08d6bbSMika Westerberg static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 3076e08d6bbSMika Westerberg static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 3086e08d6bbSMika Westerberg static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 3096e08d6bbSMika Westerberg 3106e08d6bbSMika Westerberg /* LPE I2S TXD pins need to have invert_oe set */ 3116e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 3126e08d6bbSMika Westerberg ALTERNATE_FUNCTION(30, 1, true), 3136e08d6bbSMika Westerberg ALTERNATE_FUNCTION(34, 1, true), 3146e08d6bbSMika Westerberg ALTERNATE_FUNCTION(97, 1, true), 3156e08d6bbSMika Westerberg }; 3166e08d6bbSMika Westerberg 3176e08d6bbSMika Westerberg /* 3186e08d6bbSMika Westerberg * Two spi3 chipselects are available in different mode than the main spi3 3196e08d6bbSMika Westerberg * functionality, which is using mode 1. 3206e08d6bbSMika Westerberg */ 3216e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 3226e08d6bbSMika Westerberg ALTERNATE_FUNCTION(76, 3, false), 3236e08d6bbSMika Westerberg ALTERNATE_FUNCTION(80, 3, false), 3246e08d6bbSMika Westerberg }; 3256e08d6bbSMika Westerberg 3266e08d6bbSMika Westerberg static const struct chv_pingroup southwest_groups[] = { 3276e08d6bbSMika Westerberg PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 3286e08d6bbSMika Westerberg PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 3296e08d6bbSMika Westerberg PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 3306e08d6bbSMika Westerberg PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 3316e08d6bbSMika Westerberg PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 3326e08d6bbSMika Westerberg PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 3336e08d6bbSMika Westerberg PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 3346e08d6bbSMika Westerberg PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 3356e08d6bbSMika Westerberg PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 3366e08d6bbSMika Westerberg PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 3376e08d6bbSMika Westerberg PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 3386e08d6bbSMika Westerberg PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 3396e08d6bbSMika Westerberg 3406e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 3416e08d6bbSMika Westerberg southwest_lpe_altfuncs), 3426e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 3436e08d6bbSMika Westerberg southwest_spi3_altfuncs), 3446e08d6bbSMika Westerberg }; 3456e08d6bbSMika Westerberg 3466e08d6bbSMika Westerberg static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 3476e08d6bbSMika Westerberg static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 3486e08d6bbSMika Westerberg static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 3496e08d6bbSMika Westerberg static const char * const southwest_hda_groups[] = { "hda_grp" }; 3506e08d6bbSMika Westerberg static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 3516e08d6bbSMika Westerberg static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 3526e08d6bbSMika Westerberg static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 3536e08d6bbSMika Westerberg static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 3546e08d6bbSMika Westerberg static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 3556e08d6bbSMika Westerberg static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 3566e08d6bbSMika Westerberg static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 3576e08d6bbSMika Westerberg static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 3586e08d6bbSMika Westerberg static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 3596e08d6bbSMika Westerberg static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 3606e08d6bbSMika Westerberg 3616e08d6bbSMika Westerberg /* 3626e08d6bbSMika Westerberg * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 3636e08d6bbSMika Westerberg * enabled only as GPIOs. 3646e08d6bbSMika Westerberg */ 3656e08d6bbSMika Westerberg static const struct chv_function southwest_functions[] = { 3666e08d6bbSMika Westerberg FUNCTION("uart0", southwest_uart0_groups), 3676e08d6bbSMika Westerberg FUNCTION("uart1", southwest_uart1_groups), 3686e08d6bbSMika Westerberg FUNCTION("uart2", southwest_uart2_groups), 3696e08d6bbSMika Westerberg FUNCTION("hda", southwest_hda_groups), 3706e08d6bbSMika Westerberg FUNCTION("lpe", southwest_lpe_groups), 3716e08d6bbSMika Westerberg FUNCTION("i2c0", southwest_i2c0_groups), 3726e08d6bbSMika Westerberg FUNCTION("i2c1", southwest_i2c1_groups), 3736e08d6bbSMika Westerberg FUNCTION("i2c2", southwest_i2c2_groups), 3746e08d6bbSMika Westerberg FUNCTION("i2c3", southwest_i2c3_groups), 3756e08d6bbSMika Westerberg FUNCTION("i2c4", southwest_i2c4_groups), 3766e08d6bbSMika Westerberg FUNCTION("i2c5", southwest_i2c5_groups), 3776e08d6bbSMika Westerberg FUNCTION("i2c6", southwest_i2c6_groups), 3786e08d6bbSMika Westerberg FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 3796e08d6bbSMika Westerberg FUNCTION("spi3", southwest_spi3_groups), 3806e08d6bbSMika Westerberg }; 3816e08d6bbSMika Westerberg 3826e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 3836e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 3846e08d6bbSMika Westerberg GPIO_PINRANGE(15, 22), 3856e08d6bbSMika Westerberg GPIO_PINRANGE(30, 37), 3866e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 3876e08d6bbSMika Westerberg GPIO_PINRANGE(60, 67), 3886e08d6bbSMika Westerberg GPIO_PINRANGE(75, 82), 3896e08d6bbSMika Westerberg GPIO_PINRANGE(90, 97), 3906e08d6bbSMika Westerberg }; 3916e08d6bbSMika Westerberg 3926e08d6bbSMika Westerberg static const struct chv_community southwest_community = { 3936e08d6bbSMika Westerberg .uid = "1", 3946e08d6bbSMika Westerberg .pins = southwest_pins, 3956e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southwest_pins), 3966e08d6bbSMika Westerberg .groups = southwest_groups, 3976e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southwest_groups), 3986e08d6bbSMika Westerberg .functions = southwest_functions, 3996e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southwest_functions), 4006e08d6bbSMika Westerberg .gpio_ranges = southwest_gpio_ranges, 4016e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 4026e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(southwest_pins), 40347c950d1SMika Westerberg /* 40447c950d1SMika Westerberg * Southwest community can benerate GPIO interrupts only for the 40547c950d1SMika Westerberg * first 8 interrupts. The upper half (8-15) can only be used to 40647c950d1SMika Westerberg * trigger GPEs. 40747c950d1SMika Westerberg */ 40847c950d1SMika Westerberg .nirqs = 8, 409a0b02859SHans de Goede .acpi_space_id = 0x91, 4106e08d6bbSMika Westerberg }; 4116e08d6bbSMika Westerberg 4126e08d6bbSMika Westerberg static const struct pinctrl_pin_desc north_pins[] = { 4136e08d6bbSMika Westerberg PINCTRL_PIN(0, "GPIO_DFX_0"), 4146e08d6bbSMika Westerberg PINCTRL_PIN(1, "GPIO_DFX_3"), 4156e08d6bbSMika Westerberg PINCTRL_PIN(2, "GPIO_DFX_7"), 4166e08d6bbSMika Westerberg PINCTRL_PIN(3, "GPIO_DFX_1"), 4176e08d6bbSMika Westerberg PINCTRL_PIN(4, "GPIO_DFX_5"), 4186e08d6bbSMika Westerberg PINCTRL_PIN(5, "GPIO_DFX_4"), 4196e08d6bbSMika Westerberg PINCTRL_PIN(6, "GPIO_DFX_8"), 4206e08d6bbSMika Westerberg PINCTRL_PIN(7, "GPIO_DFX_2"), 4216e08d6bbSMika Westerberg PINCTRL_PIN(8, "GPIO_DFX_6"), 4226e08d6bbSMika Westerberg 4236e08d6bbSMika Westerberg PINCTRL_PIN(15, "GPIO_SUS0"), 4246e08d6bbSMika Westerberg PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 4256e08d6bbSMika Westerberg PINCTRL_PIN(17, "GPIO_SUS3"), 4266e08d6bbSMika Westerberg PINCTRL_PIN(18, "GPIO_SUS7"), 4276e08d6bbSMika Westerberg PINCTRL_PIN(19, "GPIO_SUS1"), 4286e08d6bbSMika Westerberg PINCTRL_PIN(20, "GPIO_SUS5"), 4296e08d6bbSMika Westerberg PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 4306e08d6bbSMika Westerberg PINCTRL_PIN(22, "GPIO_SUS4"), 4316e08d6bbSMika Westerberg PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 4326e08d6bbSMika Westerberg PINCTRL_PIN(24, "GPIO_SUS2"), 4336e08d6bbSMika Westerberg PINCTRL_PIN(25, "GPIO_SUS6"), 4346e08d6bbSMika Westerberg PINCTRL_PIN(26, "CX_PREQ_B"), 4356e08d6bbSMika Westerberg PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 4366e08d6bbSMika Westerberg 4376e08d6bbSMika Westerberg PINCTRL_PIN(30, "TRST_B"), 4386e08d6bbSMika Westerberg PINCTRL_PIN(31, "TCK"), 4396e08d6bbSMika Westerberg PINCTRL_PIN(32, "PROCHOT_B"), 4406e08d6bbSMika Westerberg PINCTRL_PIN(33, "SVIDO_DATA"), 4416e08d6bbSMika Westerberg PINCTRL_PIN(34, "TMS"), 4426e08d6bbSMika Westerberg PINCTRL_PIN(35, "CX_PRDY_B_2"), 4436e08d6bbSMika Westerberg PINCTRL_PIN(36, "TDO_2"), 4446e08d6bbSMika Westerberg PINCTRL_PIN(37, "CX_PRDY_B"), 4456e08d6bbSMika Westerberg PINCTRL_PIN(38, "SVIDO_ALERT_B"), 4466e08d6bbSMika Westerberg PINCTRL_PIN(39, "TDO"), 4476e08d6bbSMika Westerberg PINCTRL_PIN(40, "SVIDO_CLK"), 4486e08d6bbSMika Westerberg PINCTRL_PIN(41, "TDI"), 4496e08d6bbSMika Westerberg 4506e08d6bbSMika Westerberg PINCTRL_PIN(45, "GP_CAMERASB_05"), 4516e08d6bbSMika Westerberg PINCTRL_PIN(46, "GP_CAMERASB_02"), 4526e08d6bbSMika Westerberg PINCTRL_PIN(47, "GP_CAMERASB_08"), 4536e08d6bbSMika Westerberg PINCTRL_PIN(48, "GP_CAMERASB_00"), 4546e08d6bbSMika Westerberg PINCTRL_PIN(49, "GP_CAMERASB_06"), 4556e08d6bbSMika Westerberg PINCTRL_PIN(50, "GP_CAMERASB_10"), 4566e08d6bbSMika Westerberg PINCTRL_PIN(51, "GP_CAMERASB_03"), 4576e08d6bbSMika Westerberg PINCTRL_PIN(52, "GP_CAMERASB_09"), 4586e08d6bbSMika Westerberg PINCTRL_PIN(53, "GP_CAMERASB_01"), 4596e08d6bbSMika Westerberg PINCTRL_PIN(54, "GP_CAMERASB_07"), 4606e08d6bbSMika Westerberg PINCTRL_PIN(55, "GP_CAMERASB_11"), 4616e08d6bbSMika Westerberg PINCTRL_PIN(56, "GP_CAMERASB_04"), 4626e08d6bbSMika Westerberg 4636e08d6bbSMika Westerberg PINCTRL_PIN(60, "PANEL0_BKLTEN"), 4646e08d6bbSMika Westerberg PINCTRL_PIN(61, "HV_DDI0_HPD"), 4656e08d6bbSMika Westerberg PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 4666e08d6bbSMika Westerberg PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 4676e08d6bbSMika Westerberg PINCTRL_PIN(64, "HV_DDI1_HPD"), 4686e08d6bbSMika Westerberg PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 4696e08d6bbSMika Westerberg PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 4706e08d6bbSMika Westerberg PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 4716e08d6bbSMika Westerberg PINCTRL_PIN(68, "HV_DDI2_HPD"), 4726e08d6bbSMika Westerberg PINCTRL_PIN(69, "PANEL1_VDDEN"), 4736e08d6bbSMika Westerberg PINCTRL_PIN(70, "PANEL1_BKLTEN"), 4746e08d6bbSMika Westerberg PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 4756e08d6bbSMika Westerberg PINCTRL_PIN(72, "PANEL0_VDDEN"), 4766e08d6bbSMika Westerberg }; 4776e08d6bbSMika Westerberg 4786e08d6bbSMika Westerberg static const struct chv_gpio_pinrange north_gpio_ranges[] = { 4796e08d6bbSMika Westerberg GPIO_PINRANGE(0, 8), 4806e08d6bbSMika Westerberg GPIO_PINRANGE(15, 27), 4816e08d6bbSMika Westerberg GPIO_PINRANGE(30, 41), 4826e08d6bbSMika Westerberg GPIO_PINRANGE(45, 56), 4836e08d6bbSMika Westerberg GPIO_PINRANGE(60, 72), 4846e08d6bbSMika Westerberg }; 4856e08d6bbSMika Westerberg 4866e08d6bbSMika Westerberg static const struct chv_community north_community = { 4876e08d6bbSMika Westerberg .uid = "2", 4886e08d6bbSMika Westerberg .pins = north_pins, 4896e08d6bbSMika Westerberg .npins = ARRAY_SIZE(north_pins), 4906e08d6bbSMika Westerberg .gpio_ranges = north_gpio_ranges, 4916e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 4926e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(north_pins), 49347c950d1SMika Westerberg /* 49447c950d1SMika Westerberg * North community can benerate GPIO interrupts only for the first 49547c950d1SMika Westerberg * 8 interrupts. The upper half (8-15) can only be used to trigger 49647c950d1SMika Westerberg * GPEs. 49747c950d1SMika Westerberg */ 49847c950d1SMika Westerberg .nirqs = 8, 499a0b02859SHans de Goede .acpi_space_id = 0x92, 5006e08d6bbSMika Westerberg }; 5016e08d6bbSMika Westerberg 5026e08d6bbSMika Westerberg static const struct pinctrl_pin_desc east_pins[] = { 5036e08d6bbSMika Westerberg PINCTRL_PIN(0, "PMU_SLP_S3_B"), 5046e08d6bbSMika Westerberg PINCTRL_PIN(1, "PMU_BATLOW_B"), 5056e08d6bbSMika Westerberg PINCTRL_PIN(2, "SUS_STAT_B"), 5066e08d6bbSMika Westerberg PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 5076e08d6bbSMika Westerberg PINCTRL_PIN(4, "PMU_AC_PRESENT"), 5086e08d6bbSMika Westerberg PINCTRL_PIN(5, "PMU_PLTRST_B"), 5096e08d6bbSMika Westerberg PINCTRL_PIN(6, "PMU_SUSCLK"), 5106e08d6bbSMika Westerberg PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 5116e08d6bbSMika Westerberg PINCTRL_PIN(8, "PMU_PWRBTN_B"), 5126e08d6bbSMika Westerberg PINCTRL_PIN(9, "PMU_SLP_S4_B"), 5136e08d6bbSMika Westerberg PINCTRL_PIN(10, "PMU_WAKE_B"), 5146e08d6bbSMika Westerberg PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 5156e08d6bbSMika Westerberg 5166e08d6bbSMika Westerberg PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 5176e08d6bbSMika Westerberg PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 5186e08d6bbSMika Westerberg PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 5196e08d6bbSMika Westerberg PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 5206e08d6bbSMika Westerberg PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 5216e08d6bbSMika Westerberg PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 5226e08d6bbSMika Westerberg PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 5236e08d6bbSMika Westerberg PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 5246e08d6bbSMika Westerberg PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 5256e08d6bbSMika Westerberg PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 5266e08d6bbSMika Westerberg PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 5276e08d6bbSMika Westerberg PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 5286e08d6bbSMika Westerberg }; 5296e08d6bbSMika Westerberg 5306e08d6bbSMika Westerberg static const struct chv_gpio_pinrange east_gpio_ranges[] = { 5316e08d6bbSMika Westerberg GPIO_PINRANGE(0, 11), 5326e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 5336e08d6bbSMika Westerberg }; 5346e08d6bbSMika Westerberg 5356e08d6bbSMika Westerberg static const struct chv_community east_community = { 5366e08d6bbSMika Westerberg .uid = "3", 5376e08d6bbSMika Westerberg .pins = east_pins, 5386e08d6bbSMika Westerberg .npins = ARRAY_SIZE(east_pins), 5396e08d6bbSMika Westerberg .gpio_ranges = east_gpio_ranges, 5406e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 5416e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(east_pins), 54247c950d1SMika Westerberg .nirqs = 16, 543a0b02859SHans de Goede .acpi_space_id = 0x93, 5446e08d6bbSMika Westerberg }; 5456e08d6bbSMika Westerberg 5466e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southeast_pins[] = { 5476e08d6bbSMika Westerberg PINCTRL_PIN(0, "MF_PLT_CLK0"), 5486e08d6bbSMika Westerberg PINCTRL_PIN(1, "PWM1"), 5496e08d6bbSMika Westerberg PINCTRL_PIN(2, "MF_PLT_CLK1"), 5506e08d6bbSMika Westerberg PINCTRL_PIN(3, "MF_PLT_CLK4"), 5516e08d6bbSMika Westerberg PINCTRL_PIN(4, "MF_PLT_CLK3"), 5526e08d6bbSMika Westerberg PINCTRL_PIN(5, "PWM0"), 5536e08d6bbSMika Westerberg PINCTRL_PIN(6, "MF_PLT_CLK5"), 5546e08d6bbSMika Westerberg PINCTRL_PIN(7, "MF_PLT_CLK2"), 5556e08d6bbSMika Westerberg 5566e08d6bbSMika Westerberg PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 5576e08d6bbSMika Westerberg PINCTRL_PIN(16, "SDMMC1_CLK"), 5586e08d6bbSMika Westerberg PINCTRL_PIN(17, "SDMMC1_D0"), 5596e08d6bbSMika Westerberg PINCTRL_PIN(18, "SDMMC2_D1"), 5606e08d6bbSMika Westerberg PINCTRL_PIN(19, "SDMMC2_CLK"), 5616e08d6bbSMika Westerberg PINCTRL_PIN(20, "SDMMC1_D2"), 5626e08d6bbSMika Westerberg PINCTRL_PIN(21, "SDMMC2_D2"), 5636e08d6bbSMika Westerberg PINCTRL_PIN(22, "SDMMC2_CMD"), 5646e08d6bbSMika Westerberg PINCTRL_PIN(23, "SDMMC1_CMD"), 5656e08d6bbSMika Westerberg PINCTRL_PIN(24, "SDMMC1_D1"), 5666e08d6bbSMika Westerberg PINCTRL_PIN(25, "SDMMC2_D0"), 5676e08d6bbSMika Westerberg PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 5686e08d6bbSMika Westerberg 5696e08d6bbSMika Westerberg PINCTRL_PIN(30, "SDMMC3_D1"), 5706e08d6bbSMika Westerberg PINCTRL_PIN(31, "SDMMC3_CLK"), 5716e08d6bbSMika Westerberg PINCTRL_PIN(32, "SDMMC3_D3"), 5726e08d6bbSMika Westerberg PINCTRL_PIN(33, "SDMMC3_D2"), 5736e08d6bbSMika Westerberg PINCTRL_PIN(34, "SDMMC3_CMD"), 5746e08d6bbSMika Westerberg PINCTRL_PIN(35, "SDMMC3_D0"), 5756e08d6bbSMika Westerberg 5766e08d6bbSMika Westerberg PINCTRL_PIN(45, "MF_LPC_AD2"), 5776e08d6bbSMika Westerberg PINCTRL_PIN(46, "LPC_CLKRUNB"), 5786e08d6bbSMika Westerberg PINCTRL_PIN(47, "MF_LPC_AD0"), 5796e08d6bbSMika Westerberg PINCTRL_PIN(48, "LPC_FRAMEB"), 5806e08d6bbSMika Westerberg PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 5816e08d6bbSMika Westerberg PINCTRL_PIN(50, "MF_LPC_AD3"), 5826e08d6bbSMika Westerberg PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 5836e08d6bbSMika Westerberg PINCTRL_PIN(52, "MF_LPC_AD1"), 5846e08d6bbSMika Westerberg 5856e08d6bbSMika Westerberg PINCTRL_PIN(60, "SPI1_MISO"), 5866e08d6bbSMika Westerberg PINCTRL_PIN(61, "SPI1_CSO_B"), 5876e08d6bbSMika Westerberg PINCTRL_PIN(62, "SPI1_CLK"), 5886e08d6bbSMika Westerberg PINCTRL_PIN(63, "MMC1_D6"), 5896e08d6bbSMika Westerberg PINCTRL_PIN(64, "SPI1_MOSI"), 5906e08d6bbSMika Westerberg PINCTRL_PIN(65, "MMC1_D5"), 5916e08d6bbSMika Westerberg PINCTRL_PIN(66, "SPI1_CS1_B"), 5926e08d6bbSMika Westerberg PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 5936e08d6bbSMika Westerberg PINCTRL_PIN(68, "MMC1_D7"), 5946e08d6bbSMika Westerberg PINCTRL_PIN(69, "MMC1_RCLK"), 5956e08d6bbSMika Westerberg 5966e08d6bbSMika Westerberg PINCTRL_PIN(75, "USB_OC1_B"), 5976e08d6bbSMika Westerberg PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 5986e08d6bbSMika Westerberg PINCTRL_PIN(77, "GPIO_ALERT"), 5996e08d6bbSMika Westerberg PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 6006e08d6bbSMika Westerberg PINCTRL_PIN(79, "ILB_SERIRQ"), 6016e08d6bbSMika Westerberg PINCTRL_PIN(80, "USB_OC0_B"), 6026e08d6bbSMika Westerberg PINCTRL_PIN(81, "SDMMC3_CD_B"), 6036e08d6bbSMika Westerberg PINCTRL_PIN(82, "SPKR"), 6046e08d6bbSMika Westerberg PINCTRL_PIN(83, "SUSPWRDNACK"), 6056e08d6bbSMika Westerberg PINCTRL_PIN(84, "SPARE_PIN"), 6066e08d6bbSMika Westerberg PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 6076e08d6bbSMika Westerberg }; 6086e08d6bbSMika Westerberg 6096e08d6bbSMika Westerberg static const unsigned southeast_pwm0_pins[] = { 5 }; 6106e08d6bbSMika Westerberg static const unsigned southeast_pwm1_pins[] = { 1 }; 6116e08d6bbSMika Westerberg static const unsigned southeast_sdmmc1_pins[] = { 6126e08d6bbSMika Westerberg 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 6136e08d6bbSMika Westerberg }; 6146e08d6bbSMika Westerberg static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 6156e08d6bbSMika Westerberg static const unsigned southeast_sdmmc3_pins[] = { 6166e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 78, 81, 85, 6176e08d6bbSMika Westerberg }; 6186e08d6bbSMika Westerberg static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 6196e08d6bbSMika Westerberg static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 6206e08d6bbSMika Westerberg 6216e08d6bbSMika Westerberg static const struct chv_pingroup southeast_groups[] = { 6226e08d6bbSMika Westerberg PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 6236e08d6bbSMika Westerberg PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 6246e08d6bbSMika Westerberg PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 6256e08d6bbSMika Westerberg PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 6266e08d6bbSMika Westerberg PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 6276e08d6bbSMika Westerberg PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 6286e08d6bbSMika Westerberg PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 6296e08d6bbSMika Westerberg }; 6306e08d6bbSMika Westerberg 6316e08d6bbSMika Westerberg static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 6326e08d6bbSMika Westerberg static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 6336e08d6bbSMika Westerberg static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 6346e08d6bbSMika Westerberg static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 6356e08d6bbSMika Westerberg static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 6366e08d6bbSMika Westerberg static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 6376e08d6bbSMika Westerberg static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 6386e08d6bbSMika Westerberg 6396e08d6bbSMika Westerberg static const struct chv_function southeast_functions[] = { 6406e08d6bbSMika Westerberg FUNCTION("pwm0", southeast_pwm0_groups), 6416e08d6bbSMika Westerberg FUNCTION("pwm1", southeast_pwm1_groups), 6426e08d6bbSMika Westerberg FUNCTION("sdmmc1", southeast_sdmmc1_groups), 6436e08d6bbSMika Westerberg FUNCTION("sdmmc2", southeast_sdmmc2_groups), 6446e08d6bbSMika Westerberg FUNCTION("sdmmc3", southeast_sdmmc3_groups), 6456e08d6bbSMika Westerberg FUNCTION("spi1", southeast_spi1_groups), 6466e08d6bbSMika Westerberg FUNCTION("spi2", southeast_spi2_groups), 6476e08d6bbSMika Westerberg }; 6486e08d6bbSMika Westerberg 6496e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 6506e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 6516e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 6526e08d6bbSMika Westerberg GPIO_PINRANGE(30, 35), 6536e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 6546e08d6bbSMika Westerberg GPIO_PINRANGE(60, 69), 6556e08d6bbSMika Westerberg GPIO_PINRANGE(75, 85), 6566e08d6bbSMika Westerberg }; 6576e08d6bbSMika Westerberg 6586e08d6bbSMika Westerberg static const struct chv_community southeast_community = { 6596e08d6bbSMika Westerberg .uid = "4", 6606e08d6bbSMika Westerberg .pins = southeast_pins, 6616e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southeast_pins), 6626e08d6bbSMika Westerberg .groups = southeast_groups, 6636e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southeast_groups), 6646e08d6bbSMika Westerberg .functions = southeast_functions, 6656e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southeast_functions), 6666e08d6bbSMika Westerberg .gpio_ranges = southeast_gpio_ranges, 6676e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 6686e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(southeast_pins), 66947c950d1SMika Westerberg .nirqs = 16, 670a0b02859SHans de Goede .acpi_space_id = 0x94, 6716e08d6bbSMika Westerberg }; 6726e08d6bbSMika Westerberg 6736e08d6bbSMika Westerberg static const struct chv_community *chv_communities[] = { 6746e08d6bbSMika Westerberg &southwest_community, 6756e08d6bbSMika Westerberg &north_community, 6766e08d6bbSMika Westerberg &east_community, 6776e08d6bbSMika Westerberg &southeast_community, 6786e08d6bbSMika Westerberg }; 6796e08d6bbSMika Westerberg 6800bd50d71SDan O'Donovan /* 6810bd50d71SDan O'Donovan * Lock to serialize register accesses 6820bd50d71SDan O'Donovan * 6830bd50d71SDan O'Donovan * Due to a silicon issue, a shared lock must be used to prevent 6840bd50d71SDan O'Donovan * concurrent accesses across the 4 GPIO controllers. 6850bd50d71SDan O'Donovan * 6860bd50d71SDan O'Donovan * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 6870bd50d71SDan O'Donovan * errata #CHT34, for further information. 6880bd50d71SDan O'Donovan */ 6890bd50d71SDan O'Donovan static DEFINE_RAW_SPINLOCK(chv_lock); 6900bd50d71SDan O'Donovan 6916e08d6bbSMika Westerberg static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 6926e08d6bbSMika Westerberg unsigned reg) 6936e08d6bbSMika Westerberg { 6946e08d6bbSMika Westerberg unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 6956e08d6bbSMika Westerberg unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 6966e08d6bbSMika Westerberg 6976e08d6bbSMika Westerberg offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 6986e08d6bbSMika Westerberg GPIO_REGS_SIZE * pad_no; 6996e08d6bbSMika Westerberg 7006e08d6bbSMika Westerberg return pctrl->regs + offset + reg; 7016e08d6bbSMika Westerberg } 7026e08d6bbSMika Westerberg 7036e08d6bbSMika Westerberg static void chv_writel(u32 value, void __iomem *reg) 7046e08d6bbSMika Westerberg { 7056e08d6bbSMika Westerberg writel(value, reg); 7066e08d6bbSMika Westerberg /* simple readback to confirm the bus transferring done */ 7076e08d6bbSMika Westerberg readl(reg); 7086e08d6bbSMika Westerberg } 7096e08d6bbSMika Westerberg 7106e08d6bbSMika Westerberg /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 7116e08d6bbSMika Westerberg static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 7126e08d6bbSMika Westerberg { 7136e08d6bbSMika Westerberg void __iomem *reg; 7146e08d6bbSMika Westerberg 7156e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 7166e08d6bbSMika Westerberg return readl(reg) & CHV_PADCTRL1_CFGLOCK; 7176e08d6bbSMika Westerberg } 7186e08d6bbSMika Westerberg 7196e08d6bbSMika Westerberg static int chv_get_groups_count(struct pinctrl_dev *pctldev) 7206e08d6bbSMika Westerberg { 7216e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7226e08d6bbSMika Westerberg 7236e08d6bbSMika Westerberg return pctrl->community->ngroups; 7246e08d6bbSMika Westerberg } 7256e08d6bbSMika Westerberg 7266e08d6bbSMika Westerberg static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 7276e08d6bbSMika Westerberg unsigned group) 7286e08d6bbSMika Westerberg { 7296e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7306e08d6bbSMika Westerberg 7316e08d6bbSMika Westerberg return pctrl->community->groups[group].name; 7326e08d6bbSMika Westerberg } 7336e08d6bbSMika Westerberg 7346e08d6bbSMika Westerberg static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 7356e08d6bbSMika Westerberg const unsigned **pins, unsigned *npins) 7366e08d6bbSMika Westerberg { 7376e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7386e08d6bbSMika Westerberg 7396e08d6bbSMika Westerberg *pins = pctrl->community->groups[group].pins; 7406e08d6bbSMika Westerberg *npins = pctrl->community->groups[group].npins; 7416e08d6bbSMika Westerberg return 0; 7426e08d6bbSMika Westerberg } 7436e08d6bbSMika Westerberg 7446e08d6bbSMika Westerberg static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 7456e08d6bbSMika Westerberg unsigned offset) 7466e08d6bbSMika Westerberg { 7476e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7486e08d6bbSMika Westerberg unsigned long flags; 7496e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 7506e08d6bbSMika Westerberg bool locked; 7516e08d6bbSMika Westerberg 7520bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 7536e08d6bbSMika Westerberg 7546e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 7556e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 7566e08d6bbSMika Westerberg locked = chv_pad_locked(pctrl, offset); 7576e08d6bbSMika Westerberg 7580bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 7596e08d6bbSMika Westerberg 7606e08d6bbSMika Westerberg if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 7616e08d6bbSMika Westerberg seq_puts(s, "GPIO "); 7626e08d6bbSMika Westerberg } else { 7636e08d6bbSMika Westerberg u32 mode; 7646e08d6bbSMika Westerberg 7656e08d6bbSMika Westerberg mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 7666e08d6bbSMika Westerberg mode >>= CHV_PADCTRL0_PMODE_SHIFT; 7676e08d6bbSMika Westerberg 7686e08d6bbSMika Westerberg seq_printf(s, "mode %d ", mode); 7696e08d6bbSMika Westerberg } 7706e08d6bbSMika Westerberg 771684373eaSMika Westerberg seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 7726e08d6bbSMika Westerberg 7736e08d6bbSMika Westerberg if (locked) 7746e08d6bbSMika Westerberg seq_puts(s, " [LOCKED]"); 7756e08d6bbSMika Westerberg } 7766e08d6bbSMika Westerberg 7776e08d6bbSMika Westerberg static const struct pinctrl_ops chv_pinctrl_ops = { 7786e08d6bbSMika Westerberg .get_groups_count = chv_get_groups_count, 7796e08d6bbSMika Westerberg .get_group_name = chv_get_group_name, 7806e08d6bbSMika Westerberg .get_group_pins = chv_get_group_pins, 7816e08d6bbSMika Westerberg .pin_dbg_show = chv_pin_dbg_show, 7826e08d6bbSMika Westerberg }; 7836e08d6bbSMika Westerberg 7846e08d6bbSMika Westerberg static int chv_get_functions_count(struct pinctrl_dev *pctldev) 7856e08d6bbSMika Westerberg { 7866e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7876e08d6bbSMika Westerberg 7886e08d6bbSMika Westerberg return pctrl->community->nfunctions; 7896e08d6bbSMika Westerberg } 7906e08d6bbSMika Westerberg 7916e08d6bbSMika Westerberg static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 7926e08d6bbSMika Westerberg unsigned function) 7936e08d6bbSMika Westerberg { 7946e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7956e08d6bbSMika Westerberg 7966e08d6bbSMika Westerberg return pctrl->community->functions[function].name; 7976e08d6bbSMika Westerberg } 7986e08d6bbSMika Westerberg 7996e08d6bbSMika Westerberg static int chv_get_function_groups(struct pinctrl_dev *pctldev, 8006e08d6bbSMika Westerberg unsigned function, 8016e08d6bbSMika Westerberg const char * const **groups, 8026e08d6bbSMika Westerberg unsigned * const ngroups) 8036e08d6bbSMika Westerberg { 8046e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 8056e08d6bbSMika Westerberg 8066e08d6bbSMika Westerberg *groups = pctrl->community->functions[function].groups; 8076e08d6bbSMika Westerberg *ngroups = pctrl->community->functions[function].ngroups; 8086e08d6bbSMika Westerberg return 0; 8096e08d6bbSMika Westerberg } 8106e08d6bbSMika Westerberg 8116e08d6bbSMika Westerberg static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 8126e08d6bbSMika Westerberg unsigned group) 8136e08d6bbSMika Westerberg { 8146e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 8156e08d6bbSMika Westerberg const struct chv_pingroup *grp; 8166e08d6bbSMika Westerberg unsigned long flags; 8176e08d6bbSMika Westerberg int i; 8186e08d6bbSMika Westerberg 8196e08d6bbSMika Westerberg grp = &pctrl->community->groups[group]; 8206e08d6bbSMika Westerberg 8210bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 8226e08d6bbSMika Westerberg 8236e08d6bbSMika Westerberg /* Check first that the pad is not locked */ 8246e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 8256e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, grp->pins[i])) { 8266e08d6bbSMika Westerberg dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 8276e08d6bbSMika Westerberg grp->pins[i]); 8280bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8296e08d6bbSMika Westerberg return -EBUSY; 8306e08d6bbSMika Westerberg } 8316e08d6bbSMika Westerberg } 8326e08d6bbSMika Westerberg 8336e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 8346e08d6bbSMika Westerberg const struct chv_alternate_function *altfunc = &grp->altfunc; 8356e08d6bbSMika Westerberg int pin = grp->pins[i]; 8366e08d6bbSMika Westerberg void __iomem *reg; 8376e08d6bbSMika Westerberg u32 value; 8386e08d6bbSMika Westerberg 8396e08d6bbSMika Westerberg /* Check if there is pin-specific config */ 8406e08d6bbSMika Westerberg if (grp->overrides) { 8416e08d6bbSMika Westerberg int j; 8426e08d6bbSMika Westerberg 8436e08d6bbSMika Westerberg for (j = 0; j < grp->noverrides; j++) { 8446e08d6bbSMika Westerberg if (grp->overrides[j].pin == pin) { 8456e08d6bbSMika Westerberg altfunc = &grp->overrides[j]; 8466e08d6bbSMika Westerberg break; 8476e08d6bbSMika Westerberg } 8486e08d6bbSMika Westerberg } 8496e08d6bbSMika Westerberg } 8506e08d6bbSMika Westerberg 8516e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 8526e08d6bbSMika Westerberg value = readl(reg); 8536e08d6bbSMika Westerberg /* Disable GPIO mode */ 8546e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_GPIOEN; 8556e08d6bbSMika Westerberg /* Set to desired mode */ 8566e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_PMODE_MASK; 8576e08d6bbSMika Westerberg value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 8586e08d6bbSMika Westerberg chv_writel(value, reg); 8596e08d6bbSMika Westerberg 8606e08d6bbSMika Westerberg /* Update for invert_oe */ 8616e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 8626e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 8636e08d6bbSMika Westerberg if (altfunc->invert_oe) 8646e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 8656e08d6bbSMika Westerberg chv_writel(value, reg); 8666e08d6bbSMika Westerberg 8676e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 8686e08d6bbSMika Westerberg pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 8696e08d6bbSMika Westerberg } 8706e08d6bbSMika Westerberg 8710bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8726e08d6bbSMika Westerberg 8736e08d6bbSMika Westerberg return 0; 8746e08d6bbSMika Westerberg } 8756e08d6bbSMika Westerberg 8766e08d6bbSMika Westerberg static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 8776e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 8786e08d6bbSMika Westerberg unsigned offset) 8796e08d6bbSMika Westerberg { 8806e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 8816e08d6bbSMika Westerberg unsigned long flags; 8826e08d6bbSMika Westerberg void __iomem *reg; 8836e08d6bbSMika Westerberg u32 value; 8846e08d6bbSMika Westerberg 8850bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 8866e08d6bbSMika Westerberg 8876e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, offset)) { 8886e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 8896e08d6bbSMika Westerberg if (!(value & CHV_PADCTRL0_GPIOEN)) { 8906e08d6bbSMika Westerberg /* Locked so cannot enable */ 8910bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8926e08d6bbSMika Westerberg return -EBUSY; 8936e08d6bbSMika Westerberg } 8946e08d6bbSMika Westerberg } else { 8956e08d6bbSMika Westerberg int i; 8966e08d6bbSMika Westerberg 8976e08d6bbSMika Westerberg /* Reset the interrupt mapping */ 8986e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 8996e08d6bbSMika Westerberg if (pctrl->intr_lines[i] == offset) { 9006e08d6bbSMika Westerberg pctrl->intr_lines[i] = 0; 9016e08d6bbSMika Westerberg break; 9026e08d6bbSMika Westerberg } 9036e08d6bbSMika Westerberg } 9046e08d6bbSMika Westerberg 9056e08d6bbSMika Westerberg /* Disable interrupt generation */ 9066e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 9076e08d6bbSMika Westerberg value = readl(reg); 9086e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 9096e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 9106e08d6bbSMika Westerberg chv_writel(value, reg); 9116e08d6bbSMika Westerberg 9126e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9132479c730SMika Westerberg value = readl(reg); 9142479c730SMika Westerberg 9152479c730SMika Westerberg /* 9162479c730SMika Westerberg * If the pin is in HiZ mode (both TX and RX buffers are 9172479c730SMika Westerberg * disabled) we turn it to be input now. 9182479c730SMika Westerberg */ 9192479c730SMika Westerberg if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 9202479c730SMika Westerberg (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 9212479c730SMika Westerberg value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 9222479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOCFG_GPI << 9232479c730SMika Westerberg CHV_PADCTRL0_GPIOCFG_SHIFT; 9242479c730SMika Westerberg } 9252479c730SMika Westerberg 9262479c730SMika Westerberg /* Switch to a GPIO mode */ 9272479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOEN; 9286e08d6bbSMika Westerberg chv_writel(value, reg); 9296e08d6bbSMika Westerberg } 9306e08d6bbSMika Westerberg 9310bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9326e08d6bbSMika Westerberg 9336e08d6bbSMika Westerberg return 0; 9346e08d6bbSMika Westerberg } 9356e08d6bbSMika Westerberg 9366e08d6bbSMika Westerberg static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 9376e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9386e08d6bbSMika Westerberg unsigned offset) 9396e08d6bbSMika Westerberg { 9406e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9416e08d6bbSMika Westerberg unsigned long flags; 9426e08d6bbSMika Westerberg void __iomem *reg; 9436e08d6bbSMika Westerberg u32 value; 9446e08d6bbSMika Westerberg 9450bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9466e08d6bbSMika Westerberg 9476e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9486e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 9496e08d6bbSMika Westerberg chv_writel(value, reg); 9506e08d6bbSMika Westerberg 9510bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9526e08d6bbSMika Westerberg } 9536e08d6bbSMika Westerberg 9546e08d6bbSMika Westerberg static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 9556e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9566e08d6bbSMika Westerberg unsigned offset, bool input) 9576e08d6bbSMika Westerberg { 9586e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9596e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9606e08d6bbSMika Westerberg unsigned long flags; 9616e08d6bbSMika Westerberg u32 ctrl0; 9626e08d6bbSMika Westerberg 9630bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9646e08d6bbSMika Westerberg 9656e08d6bbSMika Westerberg ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 9666e08d6bbSMika Westerberg if (input) 9676e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 9686e08d6bbSMika Westerberg else 9696e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 9706e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 9716e08d6bbSMika Westerberg 9720bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9736e08d6bbSMika Westerberg 9746e08d6bbSMika Westerberg return 0; 9756e08d6bbSMika Westerberg } 9766e08d6bbSMika Westerberg 9776e08d6bbSMika Westerberg static const struct pinmux_ops chv_pinmux_ops = { 9786e08d6bbSMika Westerberg .get_functions_count = chv_get_functions_count, 9796e08d6bbSMika Westerberg .get_function_name = chv_get_function_name, 9806e08d6bbSMika Westerberg .get_function_groups = chv_get_function_groups, 9816e08d6bbSMika Westerberg .set_mux = chv_pinmux_set_mux, 9826e08d6bbSMika Westerberg .gpio_request_enable = chv_gpio_request_enable, 9836e08d6bbSMika Westerberg .gpio_disable_free = chv_gpio_disable_free, 9846e08d6bbSMika Westerberg .gpio_set_direction = chv_gpio_set_direction, 9856e08d6bbSMika Westerberg }; 9866e08d6bbSMika Westerberg 9876e08d6bbSMika Westerberg static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 9886e08d6bbSMika Westerberg unsigned long *config) 9896e08d6bbSMika Westerberg { 9906e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9916e08d6bbSMika Westerberg enum pin_config_param param = pinconf_to_config_param(*config); 9926e08d6bbSMika Westerberg unsigned long flags; 9936e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 9946e08d6bbSMika Westerberg u16 arg = 0; 9956e08d6bbSMika Westerberg u32 term; 9966e08d6bbSMika Westerberg 9970bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9986e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 9996e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 10000bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10016e08d6bbSMika Westerberg 10026e08d6bbSMika Westerberg term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 10036e08d6bbSMika Westerberg 10046e08d6bbSMika Westerberg switch (param) { 10056e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 10066e08d6bbSMika Westerberg if (term) 10076e08d6bbSMika Westerberg return -EINVAL; 10086e08d6bbSMika Westerberg break; 10096e08d6bbSMika Westerberg 10106e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 10116e08d6bbSMika Westerberg if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 10126e08d6bbSMika Westerberg return -EINVAL; 10136e08d6bbSMika Westerberg 10146e08d6bbSMika Westerberg switch (term) { 10156e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 10166e08d6bbSMika Westerberg arg = 20000; 10176e08d6bbSMika Westerberg break; 10186e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 10196e08d6bbSMika Westerberg arg = 5000; 10206e08d6bbSMika Westerberg break; 10216e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_1K: 10226e08d6bbSMika Westerberg arg = 1000; 10236e08d6bbSMika Westerberg break; 10246e08d6bbSMika Westerberg } 10256e08d6bbSMika Westerberg 10266e08d6bbSMika Westerberg break; 10276e08d6bbSMika Westerberg 10286e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 10296e08d6bbSMika Westerberg if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 10306e08d6bbSMika Westerberg return -EINVAL; 10316e08d6bbSMika Westerberg 10326e08d6bbSMika Westerberg switch (term) { 10336e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 10346e08d6bbSMika Westerberg arg = 20000; 10356e08d6bbSMika Westerberg break; 10366e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 10376e08d6bbSMika Westerberg arg = 5000; 10386e08d6bbSMika Westerberg break; 10396e08d6bbSMika Westerberg } 10406e08d6bbSMika Westerberg 10416e08d6bbSMika Westerberg break; 10426e08d6bbSMika Westerberg 10436e08d6bbSMika Westerberg case PIN_CONFIG_DRIVE_OPEN_DRAIN: 10446e08d6bbSMika Westerberg if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 10456e08d6bbSMika Westerberg return -EINVAL; 10466e08d6bbSMika Westerberg break; 10476e08d6bbSMika Westerberg 10486e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 10496e08d6bbSMika Westerberg u32 cfg; 10506e08d6bbSMika Westerberg 10516e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 10526e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 10536e08d6bbSMika Westerberg if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 10546e08d6bbSMika Westerberg return -EINVAL; 10556e08d6bbSMika Westerberg 10566e08d6bbSMika Westerberg break; 10576e08d6bbSMika Westerberg } 10586e08d6bbSMika Westerberg 10596e08d6bbSMika Westerberg default: 10606e08d6bbSMika Westerberg return -ENOTSUPP; 10616e08d6bbSMika Westerberg } 10626e08d6bbSMika Westerberg 10636e08d6bbSMika Westerberg *config = pinconf_to_config_packed(param, arg); 10646e08d6bbSMika Westerberg return 0; 10656e08d6bbSMika Westerberg } 10666e08d6bbSMika Westerberg 10676e08d6bbSMika Westerberg static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 106858957d2eSMika Westerberg enum pin_config_param param, u32 arg) 10696e08d6bbSMika Westerberg { 10706e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 10716e08d6bbSMika Westerberg unsigned long flags; 10726e08d6bbSMika Westerberg u32 ctrl0, pull; 10736e08d6bbSMika Westerberg 10740bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 10756e08d6bbSMika Westerberg ctrl0 = readl(reg); 10766e08d6bbSMika Westerberg 10776e08d6bbSMika Westerberg switch (param) { 10786e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 10796e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10806e08d6bbSMika Westerberg break; 10816e08d6bbSMika Westerberg 10826e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 10836e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10846e08d6bbSMika Westerberg 10856e08d6bbSMika Westerberg switch (arg) { 10866e08d6bbSMika Westerberg case 1000: 10876e08d6bbSMika Westerberg /* For 1k there is only pull up */ 10886e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 10896e08d6bbSMika Westerberg break; 10906e08d6bbSMika Westerberg case 5000: 10916e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 10926e08d6bbSMika Westerberg break; 10936e08d6bbSMika Westerberg case 20000: 10946e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 10956e08d6bbSMika Westerberg break; 10966e08d6bbSMika Westerberg default: 10970bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10986e08d6bbSMika Westerberg return -EINVAL; 10996e08d6bbSMika Westerberg } 11006e08d6bbSMika Westerberg 11016e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 11026e08d6bbSMika Westerberg break; 11036e08d6bbSMika Westerberg 11046e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 11056e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 11066e08d6bbSMika Westerberg 11076e08d6bbSMika Westerberg switch (arg) { 11086e08d6bbSMika Westerberg case 5000: 11096e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 11106e08d6bbSMika Westerberg break; 11116e08d6bbSMika Westerberg case 20000: 11126e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 11136e08d6bbSMika Westerberg break; 11146e08d6bbSMika Westerberg default: 11150bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11166e08d6bbSMika Westerberg return -EINVAL; 11176e08d6bbSMika Westerberg } 11186e08d6bbSMika Westerberg 11196e08d6bbSMika Westerberg ctrl0 |= pull; 11206e08d6bbSMika Westerberg break; 11216e08d6bbSMika Westerberg 11226e08d6bbSMika Westerberg default: 11230bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11246e08d6bbSMika Westerberg return -EINVAL; 11256e08d6bbSMika Westerberg } 11266e08d6bbSMika Westerberg 11276e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 11280bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11296e08d6bbSMika Westerberg 11306e08d6bbSMika Westerberg return 0; 11316e08d6bbSMika Westerberg } 11326e08d6bbSMika Westerberg 1133ccdf81d0SDan O'Donovan static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1134ccdf81d0SDan O'Donovan bool enable) 1135ccdf81d0SDan O'Donovan { 1136ccdf81d0SDan O'Donovan void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1137ccdf81d0SDan O'Donovan unsigned long flags; 1138ccdf81d0SDan O'Donovan u32 ctrl1; 1139ccdf81d0SDan O'Donovan 1140ccdf81d0SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1141ccdf81d0SDan O'Donovan ctrl1 = readl(reg); 1142ccdf81d0SDan O'Donovan 1143ccdf81d0SDan O'Donovan if (enable) 1144ccdf81d0SDan O'Donovan ctrl1 |= CHV_PADCTRL1_ODEN; 1145ccdf81d0SDan O'Donovan else 1146ccdf81d0SDan O'Donovan ctrl1 &= ~CHV_PADCTRL1_ODEN; 1147ccdf81d0SDan O'Donovan 1148ccdf81d0SDan O'Donovan chv_writel(ctrl1, reg); 1149ccdf81d0SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1150ccdf81d0SDan O'Donovan 1151ccdf81d0SDan O'Donovan return 0; 1152ccdf81d0SDan O'Donovan } 1153ccdf81d0SDan O'Donovan 11546e08d6bbSMika Westerberg static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 11556e08d6bbSMika Westerberg unsigned long *configs, unsigned nconfigs) 11566e08d6bbSMika Westerberg { 11576e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 11586e08d6bbSMika Westerberg enum pin_config_param param; 11596e08d6bbSMika Westerberg int i, ret; 116058957d2eSMika Westerberg u32 arg; 11616e08d6bbSMika Westerberg 11626e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, pin)) 11636e08d6bbSMika Westerberg return -EBUSY; 11646e08d6bbSMika Westerberg 11656e08d6bbSMika Westerberg for (i = 0; i < nconfigs; i++) { 11666e08d6bbSMika Westerberg param = pinconf_to_config_param(configs[i]); 11676e08d6bbSMika Westerberg arg = pinconf_to_config_argument(configs[i]); 11686e08d6bbSMika Westerberg 11696e08d6bbSMika Westerberg switch (param) { 11706e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 11716e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 11726e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 11736e08d6bbSMika Westerberg ret = chv_config_set_pull(pctrl, pin, param, arg); 11746e08d6bbSMika Westerberg if (ret) 11756e08d6bbSMika Westerberg return ret; 11766e08d6bbSMika Westerberg break; 11776e08d6bbSMika Westerberg 1178ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_PUSH_PULL: 1179ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, false); 1180ccdf81d0SDan O'Donovan if (ret) 1181ccdf81d0SDan O'Donovan return ret; 1182ccdf81d0SDan O'Donovan break; 1183ccdf81d0SDan O'Donovan 1184ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1185ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, true); 1186ccdf81d0SDan O'Donovan if (ret) 1187ccdf81d0SDan O'Donovan return ret; 1188ccdf81d0SDan O'Donovan break; 1189ccdf81d0SDan O'Donovan 11906e08d6bbSMika Westerberg default: 11916e08d6bbSMika Westerberg return -ENOTSUPP; 11926e08d6bbSMika Westerberg } 11936e08d6bbSMika Westerberg 11946e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 11956e08d6bbSMika Westerberg param, arg); 11966e08d6bbSMika Westerberg } 11976e08d6bbSMika Westerberg 11986e08d6bbSMika Westerberg return 0; 11996e08d6bbSMika Westerberg } 12006e08d6bbSMika Westerberg 120177401d7fSDan O'Donovan static int chv_config_group_get(struct pinctrl_dev *pctldev, 120277401d7fSDan O'Donovan unsigned int group, 120377401d7fSDan O'Donovan unsigned long *config) 120477401d7fSDan O'Donovan { 120577401d7fSDan O'Donovan const unsigned int *pins; 120677401d7fSDan O'Donovan unsigned int npins; 120777401d7fSDan O'Donovan int ret; 120877401d7fSDan O'Donovan 120977401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 121077401d7fSDan O'Donovan if (ret) 121177401d7fSDan O'Donovan return ret; 121277401d7fSDan O'Donovan 121377401d7fSDan O'Donovan ret = chv_config_get(pctldev, pins[0], config); 121477401d7fSDan O'Donovan if (ret) 121577401d7fSDan O'Donovan return ret; 121677401d7fSDan O'Donovan 121777401d7fSDan O'Donovan return 0; 121877401d7fSDan O'Donovan } 121977401d7fSDan O'Donovan 122077401d7fSDan O'Donovan static int chv_config_group_set(struct pinctrl_dev *pctldev, 122177401d7fSDan O'Donovan unsigned int group, unsigned long *configs, 122277401d7fSDan O'Donovan unsigned int num_configs) 122377401d7fSDan O'Donovan { 122477401d7fSDan O'Donovan const unsigned int *pins; 122577401d7fSDan O'Donovan unsigned int npins; 122677401d7fSDan O'Donovan int i, ret; 122777401d7fSDan O'Donovan 122877401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 122977401d7fSDan O'Donovan if (ret) 123077401d7fSDan O'Donovan return ret; 123177401d7fSDan O'Donovan 123277401d7fSDan O'Donovan for (i = 0; i < npins; i++) { 123377401d7fSDan O'Donovan ret = chv_config_set(pctldev, pins[i], configs, num_configs); 123477401d7fSDan O'Donovan if (ret) 123577401d7fSDan O'Donovan return ret; 123677401d7fSDan O'Donovan } 123777401d7fSDan O'Donovan 123877401d7fSDan O'Donovan return 0; 123977401d7fSDan O'Donovan } 124077401d7fSDan O'Donovan 12416e08d6bbSMika Westerberg static const struct pinconf_ops chv_pinconf_ops = { 12426e08d6bbSMika Westerberg .is_generic = true, 12436e08d6bbSMika Westerberg .pin_config_set = chv_config_set, 12446e08d6bbSMika Westerberg .pin_config_get = chv_config_get, 124577401d7fSDan O'Donovan .pin_config_group_get = chv_config_group_get, 124677401d7fSDan O'Donovan .pin_config_group_set = chv_config_group_set, 12476e08d6bbSMika Westerberg }; 12486e08d6bbSMika Westerberg 12496e08d6bbSMika Westerberg static struct pinctrl_desc chv_pinctrl_desc = { 12506e08d6bbSMika Westerberg .pctlops = &chv_pinctrl_ops, 12516e08d6bbSMika Westerberg .pmxops = &chv_pinmux_ops, 12526e08d6bbSMika Westerberg .confops = &chv_pinconf_ops, 12536e08d6bbSMika Westerberg .owner = THIS_MODULE, 12546e08d6bbSMika Westerberg }; 12556e08d6bbSMika Westerberg 12566e08d6bbSMika Westerberg static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, 12576e08d6bbSMika Westerberg unsigned offset) 12586e08d6bbSMika Westerberg { 12596e08d6bbSMika Westerberg return pctrl->community->pins[offset].number; 12606e08d6bbSMika Westerberg } 12616e08d6bbSMika Westerberg 12626e08d6bbSMika Westerberg static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 12636e08d6bbSMika Westerberg { 12640587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12656e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 12664585b000SMika Westerberg unsigned long flags; 12676e08d6bbSMika Westerberg u32 ctrl0, cfg; 12686e08d6bbSMika Westerberg 12690bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12706e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 12710bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12726e08d6bbSMika Westerberg 12736e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 12746e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 12756e08d6bbSMika Westerberg 12766e08d6bbSMika Westerberg if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 12776e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 12786e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 12796e08d6bbSMika Westerberg } 12806e08d6bbSMika Westerberg 12816e08d6bbSMika Westerberg static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 12826e08d6bbSMika Westerberg { 12830587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12846e08d6bbSMika Westerberg unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 12856e08d6bbSMika Westerberg unsigned long flags; 12866e08d6bbSMika Westerberg void __iomem *reg; 12876e08d6bbSMika Westerberg u32 ctrl0; 12886e08d6bbSMika Westerberg 12890bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12906e08d6bbSMika Westerberg 12916e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 12926e08d6bbSMika Westerberg ctrl0 = readl(reg); 12936e08d6bbSMika Westerberg 12946e08d6bbSMika Westerberg if (value) 12956e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 12966e08d6bbSMika Westerberg else 12976e08d6bbSMika Westerberg ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 12986e08d6bbSMika Westerberg 12996e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 13006e08d6bbSMika Westerberg 13010bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 13026e08d6bbSMika Westerberg } 13036e08d6bbSMika Westerberg 13046e08d6bbSMika Westerberg static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 13056e08d6bbSMika Westerberg { 13060587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 13076e08d6bbSMika Westerberg unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 13086e08d6bbSMika Westerberg u32 ctrl0, direction; 13094585b000SMika Westerberg unsigned long flags; 13106e08d6bbSMika Westerberg 13110bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 13126e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13130bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 13146e08d6bbSMika Westerberg 13156e08d6bbSMika Westerberg direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 13166e08d6bbSMika Westerberg direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 13176e08d6bbSMika Westerberg 13186e08d6bbSMika Westerberg return direction != CHV_PADCTRL0_GPIOCFG_GPO; 13196e08d6bbSMika Westerberg } 13206e08d6bbSMika Westerberg 13216e08d6bbSMika Westerberg static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 13226e08d6bbSMika Westerberg { 13236e08d6bbSMika Westerberg return pinctrl_gpio_direction_input(chip->base + offset); 13246e08d6bbSMika Westerberg } 13256e08d6bbSMika Westerberg 13266e08d6bbSMika Westerberg static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 13276e08d6bbSMika Westerberg int value) 13286e08d6bbSMika Westerberg { 1329549e783fSqipeng.zha chv_gpio_set(chip, offset, value); 13306e08d6bbSMika Westerberg return pinctrl_gpio_direction_output(chip->base + offset); 13316e08d6bbSMika Westerberg } 13326e08d6bbSMika Westerberg 13336e08d6bbSMika Westerberg static const struct gpio_chip chv_gpio_chip = { 13346e08d6bbSMika Westerberg .owner = THIS_MODULE, 133598c85d58SJonas Gorski .request = gpiochip_generic_request, 133698c85d58SJonas Gorski .free = gpiochip_generic_free, 13376e08d6bbSMika Westerberg .get_direction = chv_gpio_get_direction, 13386e08d6bbSMika Westerberg .direction_input = chv_gpio_direction_input, 13396e08d6bbSMika Westerberg .direction_output = chv_gpio_direction_output, 13406e08d6bbSMika Westerberg .get = chv_gpio_get, 13416e08d6bbSMika Westerberg .set = chv_gpio_set, 13426e08d6bbSMika Westerberg }; 13436e08d6bbSMika Westerberg 13446e08d6bbSMika Westerberg static void chv_gpio_irq_ack(struct irq_data *d) 13456e08d6bbSMika Westerberg { 13466e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13470587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 13486e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 13496e08d6bbSMika Westerberg u32 intr_line; 13506e08d6bbSMika Westerberg 13510bd50d71SDan O'Donovan raw_spin_lock(&chv_lock); 13526e08d6bbSMika Westerberg 13536e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13546e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13556e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13566e08d6bbSMika Westerberg chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 13576e08d6bbSMika Westerberg 13580bd50d71SDan O'Donovan raw_spin_unlock(&chv_lock); 13596e08d6bbSMika Westerberg } 13606e08d6bbSMika Westerberg 13616e08d6bbSMika Westerberg static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 13626e08d6bbSMika Westerberg { 13636e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13640587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 13656e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 13666e08d6bbSMika Westerberg u32 value, intr_line; 13676e08d6bbSMika Westerberg unsigned long flags; 13686e08d6bbSMika Westerberg 13690bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 13706e08d6bbSMika Westerberg 13716e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13726e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13736e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13746e08d6bbSMika Westerberg 13756e08d6bbSMika Westerberg value = readl(pctrl->regs + CHV_INTMASK); 13766e08d6bbSMika Westerberg if (mask) 13776e08d6bbSMika Westerberg value &= ~BIT(intr_line); 13786e08d6bbSMika Westerberg else 13796e08d6bbSMika Westerberg value |= BIT(intr_line); 13806e08d6bbSMika Westerberg chv_writel(value, pctrl->regs + CHV_INTMASK); 13816e08d6bbSMika Westerberg 13820bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 13836e08d6bbSMika Westerberg } 13846e08d6bbSMika Westerberg 13856e08d6bbSMika Westerberg static void chv_gpio_irq_mask(struct irq_data *d) 13866e08d6bbSMika Westerberg { 13876e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, true); 13886e08d6bbSMika Westerberg } 13896e08d6bbSMika Westerberg 13906e08d6bbSMika Westerberg static void chv_gpio_irq_unmask(struct irq_data *d) 13916e08d6bbSMika Westerberg { 13926e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, false); 13936e08d6bbSMika Westerberg } 13946e08d6bbSMika Westerberg 1395e6c906deSMika Westerberg static unsigned chv_gpio_irq_startup(struct irq_data *d) 1396e6c906deSMika Westerberg { 1397e6c906deSMika Westerberg /* 1398e6c906deSMika Westerberg * Check if the interrupt has been requested with 0 as triggering 1399e6c906deSMika Westerberg * type. In that case it is assumed that the current values 1400e6c906deSMika Westerberg * programmed to the hardware are used (e.g BIOS configured 1401e6c906deSMika Westerberg * defaults). 1402e6c906deSMika Westerberg * 1403e6c906deSMika Westerberg * In that case ->irq_set_type() will never be called so we need to 1404e6c906deSMika Westerberg * read back the values from hardware now, set correct flow handler 1405e6c906deSMika Westerberg * and update mappings before the interrupt is being used. 1406e6c906deSMika Westerberg */ 1407e6c906deSMika Westerberg if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1408e6c906deSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 14090587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1410e6c906deSMika Westerberg unsigned offset = irqd_to_hwirq(d); 1411e6c906deSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 1412e6c906deSMika Westerberg irq_flow_handler_t handler; 1413e6c906deSMika Westerberg unsigned long flags; 1414e6c906deSMika Westerberg u32 intsel, value; 1415e6c906deSMika Westerberg 14160bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1417e6c906deSMika Westerberg intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1418e6c906deSMika Westerberg intsel &= CHV_PADCTRL0_INTSEL_MASK; 1419e6c906deSMika Westerberg intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1420e6c906deSMika Westerberg 1421e6c906deSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1422e6c906deSMika Westerberg if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1423e6c906deSMika Westerberg handler = handle_level_irq; 1424e6c906deSMika Westerberg else 1425e6c906deSMika Westerberg handler = handle_edge_irq; 1426e6c906deSMika Westerberg 1427e6c906deSMika Westerberg if (!pctrl->intr_lines[intsel]) { 1428a4e3f783SThomas Gleixner irq_set_handler_locked(d, handler); 1429e6c906deSMika Westerberg pctrl->intr_lines[intsel] = offset; 1430e6c906deSMika Westerberg } 14310bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1432e6c906deSMika Westerberg } 1433e6c906deSMika Westerberg 1434e6c906deSMika Westerberg chv_gpio_irq_unmask(d); 1435e6c906deSMika Westerberg return 0; 1436e6c906deSMika Westerberg } 1437e6c906deSMika Westerberg 14386e08d6bbSMika Westerberg static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 14396e08d6bbSMika Westerberg { 14406e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 14410587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 14426e08d6bbSMika Westerberg unsigned offset = irqd_to_hwirq(d); 14436e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 14446e08d6bbSMika Westerberg unsigned long flags; 14456e08d6bbSMika Westerberg u32 value; 14466e08d6bbSMika Westerberg 14470bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 14486e08d6bbSMika Westerberg 14496e08d6bbSMika Westerberg /* 14506e08d6bbSMika Westerberg * Pins which can be used as shared interrupt are configured in 14516e08d6bbSMika Westerberg * BIOS. Driver trusts BIOS configurations and assigns different 14526e08d6bbSMika Westerberg * handler according to the irq type. 14536e08d6bbSMika Westerberg * 14546e08d6bbSMika Westerberg * Driver needs to save the mapping between each pin and 14556e08d6bbSMika Westerberg * its interrupt line. 14566e08d6bbSMika Westerberg * 1. If the pin cfg is locked in BIOS: 14576e08d6bbSMika Westerberg * Trust BIOS has programmed IntWakeCfg bits correctly, 14586e08d6bbSMika Westerberg * driver just needs to save the mapping. 14596e08d6bbSMika Westerberg * 2. If the pin cfg is not locked in BIOS: 14606e08d6bbSMika Westerberg * Driver programs the IntWakeCfg bits and save the mapping. 14616e08d6bbSMika Westerberg */ 14626e08d6bbSMika Westerberg if (!chv_pad_locked(pctrl, pin)) { 14636e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 14646e08d6bbSMika Westerberg 14656e08d6bbSMika Westerberg value = readl(reg); 14666e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 14676e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 14686e08d6bbSMika Westerberg 14696e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) { 14706e08d6bbSMika Westerberg if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 14716e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 14726e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_RISING) 14736e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_RISING; 14746e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_FALLING) 14756e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 14766e08d6bbSMika Westerberg } else if (type & IRQ_TYPE_LEVEL_MASK) { 14776e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 14786e08d6bbSMika Westerberg if (type & IRQ_TYPE_LEVEL_LOW) 14796e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_RXDATA; 14806e08d6bbSMika Westerberg } 14816e08d6bbSMika Westerberg 14826e08d6bbSMika Westerberg chv_writel(value, reg); 14836e08d6bbSMika Westerberg } 14846e08d6bbSMika Westerberg 14856e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 14866e08d6bbSMika Westerberg value &= CHV_PADCTRL0_INTSEL_MASK; 14876e08d6bbSMika Westerberg value >>= CHV_PADCTRL0_INTSEL_SHIFT; 14886e08d6bbSMika Westerberg 14896e08d6bbSMika Westerberg pctrl->intr_lines[value] = offset; 14906e08d6bbSMika Westerberg 14916e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) 1492a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 14936e08d6bbSMika Westerberg else if (type & IRQ_TYPE_LEVEL_MASK) 1494a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 14956e08d6bbSMika Westerberg 14960bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 14976e08d6bbSMika Westerberg 14986e08d6bbSMika Westerberg return 0; 14996e08d6bbSMika Westerberg } 15006e08d6bbSMika Westerberg 15016e08d6bbSMika Westerberg static struct irq_chip chv_gpio_irqchip = { 15026e08d6bbSMika Westerberg .name = "chv-gpio", 1503e6c906deSMika Westerberg .irq_startup = chv_gpio_irq_startup, 15046e08d6bbSMika Westerberg .irq_ack = chv_gpio_irq_ack, 15056e08d6bbSMika Westerberg .irq_mask = chv_gpio_irq_mask, 15066e08d6bbSMika Westerberg .irq_unmask = chv_gpio_irq_unmask, 15076e08d6bbSMika Westerberg .irq_set_type = chv_gpio_irq_type, 15086e08d6bbSMika Westerberg .flags = IRQCHIP_SKIP_SET_WAKE, 15096e08d6bbSMika Westerberg }; 15106e08d6bbSMika Westerberg 1511bd0b9ac4SThomas Gleixner static void chv_gpio_irq_handler(struct irq_desc *desc) 15126e08d6bbSMika Westerberg { 15136e08d6bbSMika Westerberg struct gpio_chip *gc = irq_desc_get_handler_data(desc); 15140587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 15155663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 15166e08d6bbSMika Westerberg unsigned long pending; 15176e08d6bbSMika Westerberg u32 intr_line; 15186e08d6bbSMika Westerberg 15196e08d6bbSMika Westerberg chained_irq_enter(chip, desc); 15206e08d6bbSMika Westerberg 15216e08d6bbSMika Westerberg pending = readl(pctrl->regs + CHV_INTSTAT); 152247c950d1SMika Westerberg for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { 15236e08d6bbSMika Westerberg unsigned irq, offset; 15246e08d6bbSMika Westerberg 15256e08d6bbSMika Westerberg offset = pctrl->intr_lines[intr_line]; 15266e08d6bbSMika Westerberg irq = irq_find_mapping(gc->irqdomain, offset); 15276e08d6bbSMika Westerberg generic_handle_irq(irq); 15286e08d6bbSMika Westerberg } 15296e08d6bbSMika Westerberg 15306e08d6bbSMika Westerberg chained_irq_exit(chip, desc); 15316e08d6bbSMika Westerberg } 15326e08d6bbSMika Westerberg 153370365027SMika Westerberg /* 153470365027SMika Westerberg * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 153570365027SMika Westerberg * tables. Since we leave GPIOs that are not capable of generating 153670365027SMika Westerberg * interrupts out of the irqdomain the numbering will be different and 153770365027SMika Westerberg * cause devices using the hardcoded IRQ numbers fail. In order not to 153870365027SMika Westerberg * break such machines we will only mask pins from irqdomain if the machine 153970365027SMika Westerberg * is not listed below. 154070365027SMika Westerberg */ 154170365027SMika Westerberg static const struct dmi_system_id chv_no_valid_mask[] = { 154270365027SMika Westerberg /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 15432a8209faSMika Westerberg { 15442a8209faSMika Westerberg .ident = "Intel_Strago based Chromebooks (All models)", 154570365027SMika Westerberg .matches = { 154670365027SMika Westerberg DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 15472a8209faSMika Westerberg DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 15482a8209faSMika Westerberg }, 15492a8209faSMika Westerberg }, 15502a8209faSMika Westerberg { 15512d80bd3fSAndy Shevchenko .ident = "HP Chromebook 11 G5 (Setzer)", 15522d80bd3fSAndy Shevchenko .matches = { 15532d80bd3fSAndy Shevchenko DMI_MATCH(DMI_SYS_VENDOR, "HP"), 15542d80bd3fSAndy Shevchenko DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 15552d80bd3fSAndy Shevchenko }, 15562d80bd3fSAndy Shevchenko }, 15572d80bd3fSAndy Shevchenko { 15582a8209faSMika Westerberg .ident = "Acer Chromebook R11 (Cyan)", 15592a8209faSMika Westerberg .matches = { 15602a8209faSMika Westerberg DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 15612a8209faSMika Westerberg DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 15622a8209faSMika Westerberg }, 15632a8209faSMika Westerberg }, 15642a8209faSMika Westerberg { 15652a8209faSMika Westerberg .ident = "Samsung Chromebook 3 (Celes)", 15662a8209faSMika Westerberg .matches = { 15672a8209faSMika Westerberg DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 15682a8209faSMika Westerberg DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 156970365027SMika Westerberg }, 1570a9de080bSWei Yongjun }, 1571a9de080bSWei Yongjun {} 157270365027SMika Westerberg }; 157370365027SMika Westerberg 15746e08d6bbSMika Westerberg static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 15756e08d6bbSMika Westerberg { 15766e08d6bbSMika Westerberg const struct chv_gpio_pinrange *range; 15776e08d6bbSMika Westerberg struct gpio_chip *chip = &pctrl->chip; 157870365027SMika Westerberg bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 15796e08d6bbSMika Westerberg int ret, i, offset; 1580845e405eSGrygorii Strashko int irq_base; 15816e08d6bbSMika Westerberg 15826e08d6bbSMika Westerberg *chip = chv_gpio_chip; 15836e08d6bbSMika Westerberg 15846e08d6bbSMika Westerberg chip->ngpio = pctrl->community->ngpios; 15856e08d6bbSMika Westerberg chip->label = dev_name(pctrl->dev); 158658383c78SLinus Walleij chip->parent = pctrl->dev; 15876e08d6bbSMika Westerberg chip->base = -1; 158870365027SMika Westerberg chip->irq_need_valid_mask = need_valid_mask; 15896e08d6bbSMika Westerberg 1590d1073418SMika Westerberg ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 15916e08d6bbSMika Westerberg if (ret) { 15926e08d6bbSMika Westerberg dev_err(pctrl->dev, "Failed to register gpiochip\n"); 15936e08d6bbSMika Westerberg return ret; 15946e08d6bbSMika Westerberg } 15956e08d6bbSMika Westerberg 15966e08d6bbSMika Westerberg for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { 15976e08d6bbSMika Westerberg range = &pctrl->community->gpio_ranges[i]; 15986e08d6bbSMika Westerberg ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, 15996e08d6bbSMika Westerberg range->base, range->npins); 16006e08d6bbSMika Westerberg if (ret) { 16016e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1602d1073418SMika Westerberg return ret; 16036e08d6bbSMika Westerberg } 16046e08d6bbSMika Westerberg 16056e08d6bbSMika Westerberg offset += range->npins; 16066e08d6bbSMika Westerberg } 16076e08d6bbSMika Westerberg 160847c950d1SMika Westerberg /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 160947c950d1SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 161047c950d1SMika Westerberg const struct pinctrl_pin_desc *desc; 161147c950d1SMika Westerberg u32 intsel; 161247c950d1SMika Westerberg 161347c950d1SMika Westerberg desc = &pctrl->community->pins[i]; 161447c950d1SMika Westerberg 161547c950d1SMika Westerberg intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); 161647c950d1SMika Westerberg intsel &= CHV_PADCTRL0_INTSEL_MASK; 161747c950d1SMika Westerberg intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 161847c950d1SMika Westerberg 161970365027SMika Westerberg if (need_valid_mask && intsel >= pctrl->community->nirqs) 162047c950d1SMika Westerberg clear_bit(i, chip->irq_valid_mask); 162147c950d1SMika Westerberg } 162247c950d1SMika Westerberg 1623bcb48ccaSMika Westerberg /* Clear all interrupts */ 16246e08d6bbSMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 16256e08d6bbSMika Westerberg 1626845e405eSGrygorii Strashko if (!need_valid_mask) { 1627845e405eSGrygorii Strashko irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, 1628845e405eSGrygorii Strashko chip->ngpio, NUMA_NO_NODE); 1629845e405eSGrygorii Strashko if (irq_base < 0) { 1630845e405eSGrygorii Strashko dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); 1631845e405eSGrygorii Strashko return irq_base; 1632845e405eSGrygorii Strashko } 1633845e405eSGrygorii Strashko } else { 1634845e405eSGrygorii Strashko irq_base = 0; 1635845e405eSGrygorii Strashko } 1636845e405eSGrygorii Strashko 1637845e405eSGrygorii Strashko ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, irq_base, 1638bcb48ccaSMika Westerberg handle_bad_irq, IRQ_TYPE_NONE); 16396e08d6bbSMika Westerberg if (ret) { 16406e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add IRQ chip\n"); 1641d1073418SMika Westerberg return ret; 16426e08d6bbSMika Westerberg } 16436e08d6bbSMika Westerberg 16446e08d6bbSMika Westerberg gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 16456e08d6bbSMika Westerberg chv_gpio_irq_handler); 16466e08d6bbSMika Westerberg return 0; 16476e08d6bbSMika Westerberg } 16486e08d6bbSMika Westerberg 1649a0b02859SHans de Goede static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1650a0b02859SHans de Goede acpi_physical_address address, u32 bits, u64 *value, 1651a0b02859SHans de Goede void *handler_context, void *region_context) 1652a0b02859SHans de Goede { 1653a0b02859SHans de Goede struct chv_pinctrl *pctrl = region_context; 1654a0b02859SHans de Goede unsigned long flags; 1655a0b02859SHans de Goede acpi_status ret = AE_OK; 1656a0b02859SHans de Goede 1657a0b02859SHans de Goede raw_spin_lock_irqsave(&chv_lock, flags); 1658a0b02859SHans de Goede 1659a0b02859SHans de Goede if (function == ACPI_WRITE) 1660a0b02859SHans de Goede chv_writel((u32)(*value), pctrl->regs + (u32)address); 1661a0b02859SHans de Goede else if (function == ACPI_READ) 1662a0b02859SHans de Goede *value = readl(pctrl->regs + (u32)address); 1663a0b02859SHans de Goede else 1664a0b02859SHans de Goede ret = AE_BAD_PARAMETER; 1665a0b02859SHans de Goede 1666a0b02859SHans de Goede raw_spin_unlock_irqrestore(&chv_lock, flags); 1667a0b02859SHans de Goede 1668a0b02859SHans de Goede return ret; 1669a0b02859SHans de Goede } 1670a0b02859SHans de Goede 16716e08d6bbSMika Westerberg static int chv_pinctrl_probe(struct platform_device *pdev) 16726e08d6bbSMika Westerberg { 16736e08d6bbSMika Westerberg struct chv_pinctrl *pctrl; 16746e08d6bbSMika Westerberg struct acpi_device *adev; 16756e08d6bbSMika Westerberg struct resource *res; 1676a0b02859SHans de Goede acpi_status status; 16776e08d6bbSMika Westerberg int ret, irq, i; 16786e08d6bbSMika Westerberg 16796e08d6bbSMika Westerberg adev = ACPI_COMPANION(&pdev->dev); 16806e08d6bbSMika Westerberg if (!adev) 16816e08d6bbSMika Westerberg return -ENODEV; 16826e08d6bbSMika Westerberg 16836e08d6bbSMika Westerberg pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 16846e08d6bbSMika Westerberg if (!pctrl) 16856e08d6bbSMika Westerberg return -ENOMEM; 16866e08d6bbSMika Westerberg 16876e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 16886e08d6bbSMika Westerberg if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 16896e08d6bbSMika Westerberg pctrl->community = chv_communities[i]; 16906e08d6bbSMika Westerberg break; 16916e08d6bbSMika Westerberg } 16926e08d6bbSMika Westerberg if (i == ARRAY_SIZE(chv_communities)) 16936e08d6bbSMika Westerberg return -ENODEV; 16946e08d6bbSMika Westerberg 16956e08d6bbSMika Westerberg pctrl->dev = &pdev->dev; 16966e08d6bbSMika Westerberg 16979eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 16989eb457b5SMika Westerberg pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 16999eb457b5SMika Westerberg pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 17009eb457b5SMika Westerberg GFP_KERNEL); 17019eb457b5SMika Westerberg if (!pctrl->saved_pin_context) 17029eb457b5SMika Westerberg return -ENOMEM; 17039eb457b5SMika Westerberg #endif 17049eb457b5SMika Westerberg 17056e08d6bbSMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 17066e08d6bbSMika Westerberg pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 17076e08d6bbSMika Westerberg if (IS_ERR(pctrl->regs)) 17086e08d6bbSMika Westerberg return PTR_ERR(pctrl->regs); 17096e08d6bbSMika Westerberg 17106e08d6bbSMika Westerberg irq = platform_get_irq(pdev, 0); 17116e08d6bbSMika Westerberg if (irq < 0) { 17126e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to get interrupt number\n"); 17136e08d6bbSMika Westerberg return irq; 17146e08d6bbSMika Westerberg } 17156e08d6bbSMika Westerberg 17166e08d6bbSMika Westerberg pctrl->pctldesc = chv_pinctrl_desc; 17176e08d6bbSMika Westerberg pctrl->pctldesc.name = dev_name(&pdev->dev); 17186e08d6bbSMika Westerberg pctrl->pctldesc.pins = pctrl->community->pins; 17196e08d6bbSMika Westerberg pctrl->pctldesc.npins = pctrl->community->npins; 17206e08d6bbSMika Westerberg 17217cf061faSLaxman Dewangan pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 17227cf061faSLaxman Dewangan pctrl); 1723323de9efSMasahiro Yamada if (IS_ERR(pctrl->pctldev)) { 17246e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1725323de9efSMasahiro Yamada return PTR_ERR(pctrl->pctldev); 17266e08d6bbSMika Westerberg } 17276e08d6bbSMika Westerberg 17286e08d6bbSMika Westerberg ret = chv_gpio_probe(pctrl, irq); 17297cf061faSLaxman Dewangan if (ret) 17306e08d6bbSMika Westerberg return ret; 17316e08d6bbSMika Westerberg 1732a0b02859SHans de Goede status = acpi_install_address_space_handler(adev->handle, 1733a0b02859SHans de Goede pctrl->community->acpi_space_id, 1734a0b02859SHans de Goede chv_pinctrl_mmio_access_handler, 1735a0b02859SHans de Goede NULL, pctrl); 1736a0b02859SHans de Goede if (ACPI_FAILURE(status)) 1737a0b02859SHans de Goede dev_err(&pdev->dev, "failed to install ACPI addr space handler\n"); 1738a0b02859SHans de Goede 17396e08d6bbSMika Westerberg platform_set_drvdata(pdev, pctrl); 17406e08d6bbSMika Westerberg 17416e08d6bbSMika Westerberg return 0; 17426e08d6bbSMika Westerberg } 17436e08d6bbSMika Westerberg 1744a0b02859SHans de Goede static int chv_pinctrl_remove(struct platform_device *pdev) 1745a0b02859SHans de Goede { 1746a0b02859SHans de Goede struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 1747a0b02859SHans de Goede 1748a0b02859SHans de Goede acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), 1749a0b02859SHans de Goede pctrl->community->acpi_space_id, 1750a0b02859SHans de Goede chv_pinctrl_mmio_access_handler); 1751a0b02859SHans de Goede 1752a0b02859SHans de Goede return 0; 1753a0b02859SHans de Goede } 1754a0b02859SHans de Goede 17559eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 1756d2cdf5dcSMika Westerberg static int chv_pinctrl_suspend_noirq(struct device *dev) 17579eb457b5SMika Westerberg { 17589eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 17599eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 176056211121SMika Westerberg unsigned long flags; 17619eb457b5SMika Westerberg int i; 17629eb457b5SMika Westerberg 176356211121SMika Westerberg raw_spin_lock_irqsave(&chv_lock, flags); 176456211121SMika Westerberg 17659eb457b5SMika Westerberg pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 17669eb457b5SMika Westerberg 17679eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 17689eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 17699eb457b5SMika Westerberg struct chv_pin_context *ctx; 17709eb457b5SMika Westerberg void __iomem *reg; 17719eb457b5SMika Westerberg 17729eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 17739eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 17749eb457b5SMika Westerberg continue; 17759eb457b5SMika Westerberg 17769eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 17779eb457b5SMika Westerberg 17789eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 17799eb457b5SMika Westerberg ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 17809eb457b5SMika Westerberg 17819eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 17829eb457b5SMika Westerberg ctx->padctrl1 = readl(reg); 17839eb457b5SMika Westerberg } 17849eb457b5SMika Westerberg 178556211121SMika Westerberg raw_spin_unlock_irqrestore(&chv_lock, flags); 178656211121SMika Westerberg 17879eb457b5SMika Westerberg return 0; 17889eb457b5SMika Westerberg } 17899eb457b5SMika Westerberg 1790d2cdf5dcSMika Westerberg static int chv_pinctrl_resume_noirq(struct device *dev) 17919eb457b5SMika Westerberg { 17929eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 17939eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 179456211121SMika Westerberg unsigned long flags; 17959eb457b5SMika Westerberg int i; 17969eb457b5SMika Westerberg 179756211121SMika Westerberg raw_spin_lock_irqsave(&chv_lock, flags); 179856211121SMika Westerberg 17999eb457b5SMika Westerberg /* 18009eb457b5SMika Westerberg * Mask all interrupts before restoring per-pin configuration 18019eb457b5SMika Westerberg * registers because we don't know in which state BIOS left them 18029eb457b5SMika Westerberg * upon exiting suspend. 18039eb457b5SMika Westerberg */ 18049eb457b5SMika Westerberg chv_writel(0, pctrl->regs + CHV_INTMASK); 18059eb457b5SMika Westerberg 18069eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 18079eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 18089eb457b5SMika Westerberg const struct chv_pin_context *ctx; 18099eb457b5SMika Westerberg void __iomem *reg; 18109eb457b5SMika Westerberg u32 val; 18119eb457b5SMika Westerberg 18129eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 18139eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 18149eb457b5SMika Westerberg continue; 18159eb457b5SMika Westerberg 18169eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 18179eb457b5SMika Westerberg 18189eb457b5SMika Westerberg /* Only restore if our saved state differs from the current */ 18199eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 18209eb457b5SMika Westerberg val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 18219eb457b5SMika Westerberg if (ctx->padctrl0 != val) { 18229eb457b5SMika Westerberg chv_writel(ctx->padctrl0, reg); 18239eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 18249eb457b5SMika Westerberg desc->number, readl(reg)); 18259eb457b5SMika Westerberg } 18269eb457b5SMika Westerberg 18279eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 18289eb457b5SMika Westerberg val = readl(reg); 18299eb457b5SMika Westerberg if (ctx->padctrl1 != val) { 18309eb457b5SMika Westerberg chv_writel(ctx->padctrl1, reg); 18319eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 18329eb457b5SMika Westerberg desc->number, readl(reg)); 18339eb457b5SMika Westerberg } 18349eb457b5SMika Westerberg } 18359eb457b5SMika Westerberg 18369eb457b5SMika Westerberg /* 18379eb457b5SMika Westerberg * Now that all pins are restored to known state, we can restore 18389eb457b5SMika Westerberg * the interrupt mask register as well. 18399eb457b5SMika Westerberg */ 18409eb457b5SMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 18419eb457b5SMika Westerberg chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 18429eb457b5SMika Westerberg 184356211121SMika Westerberg raw_spin_unlock_irqrestore(&chv_lock, flags); 184456211121SMika Westerberg 18459eb457b5SMika Westerberg return 0; 18469eb457b5SMika Westerberg } 18479eb457b5SMika Westerberg #endif 18489eb457b5SMika Westerberg 18499eb457b5SMika Westerberg static const struct dev_pm_ops chv_pinctrl_pm_ops = { 1850d2cdf5dcSMika Westerberg SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq, 1851d2cdf5dcSMika Westerberg chv_pinctrl_resume_noirq) 18529eb457b5SMika Westerberg }; 18539eb457b5SMika Westerberg 18546e08d6bbSMika Westerberg static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 18556e08d6bbSMika Westerberg { "INT33FF" }, 18566e08d6bbSMika Westerberg { } 18576e08d6bbSMika Westerberg }; 18586e08d6bbSMika Westerberg MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 18596e08d6bbSMika Westerberg 18606e08d6bbSMika Westerberg static struct platform_driver chv_pinctrl_driver = { 18616e08d6bbSMika Westerberg .probe = chv_pinctrl_probe, 1862a0b02859SHans de Goede .remove = chv_pinctrl_remove, 18636e08d6bbSMika Westerberg .driver = { 18646e08d6bbSMika Westerberg .name = "cherryview-pinctrl", 18659eb457b5SMika Westerberg .pm = &chv_pinctrl_pm_ops, 18666e08d6bbSMika Westerberg .acpi_match_table = chv_pinctrl_acpi_match, 18676e08d6bbSMika Westerberg }, 18686e08d6bbSMika Westerberg }; 18696e08d6bbSMika Westerberg 18706e08d6bbSMika Westerberg static int __init chv_pinctrl_init(void) 18716e08d6bbSMika Westerberg { 18726e08d6bbSMika Westerberg return platform_driver_register(&chv_pinctrl_driver); 18736e08d6bbSMika Westerberg } 18746e08d6bbSMika Westerberg subsys_initcall(chv_pinctrl_init); 18756e08d6bbSMika Westerberg 18766e08d6bbSMika Westerberg static void __exit chv_pinctrl_exit(void) 18776e08d6bbSMika Westerberg { 18786e08d6bbSMika Westerberg platform_driver_unregister(&chv_pinctrl_driver); 18796e08d6bbSMika Westerberg } 18806e08d6bbSMika Westerberg module_exit(chv_pinctrl_exit); 18816e08d6bbSMika Westerberg 18826e08d6bbSMika Westerberg MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 18836e08d6bbSMika Westerberg MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 18846e08d6bbSMika Westerberg MODULE_LICENSE("GPL v2"); 1885