16e08d6bbSMika Westerberg /* 26e08d6bbSMika Westerberg * Cherryview/Braswell pinctrl driver 36e08d6bbSMika Westerberg * 46e08d6bbSMika Westerberg * Copyright (C) 2014, Intel Corporation 56e08d6bbSMika Westerberg * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 66e08d6bbSMika Westerberg * 76e08d6bbSMika Westerberg * This driver is based on the original Cherryview GPIO driver by 86e08d6bbSMika Westerberg * Ning Li <ning.li@intel.com> 96e08d6bbSMika Westerberg * Alan Cox <alan@linux.intel.com> 106e08d6bbSMika Westerberg * 116e08d6bbSMika Westerberg * This program is free software; you can redistribute it and/or modify 126e08d6bbSMika Westerberg * it under the terms of the GNU General Public License version 2 as 136e08d6bbSMika Westerberg * published by the Free Software Foundation. 146e08d6bbSMika Westerberg */ 156e08d6bbSMika Westerberg 166e08d6bbSMika Westerberg #include <linux/kernel.h> 176e08d6bbSMika Westerberg #include <linux/module.h> 186e08d6bbSMika Westerberg #include <linux/init.h> 196e08d6bbSMika Westerberg #include <linux/types.h> 206e08d6bbSMika Westerberg #include <linux/gpio.h> 216e08d6bbSMika Westerberg #include <linux/gpio/driver.h> 226e08d6bbSMika Westerberg #include <linux/acpi.h> 236e08d6bbSMika Westerberg #include <linux/pinctrl/pinctrl.h> 246e08d6bbSMika Westerberg #include <linux/pinctrl/pinmux.h> 256e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf.h> 266e08d6bbSMika Westerberg #include <linux/pinctrl/pinconf-generic.h> 276e08d6bbSMika Westerberg #include <linux/platform_device.h> 286e08d6bbSMika Westerberg 296e08d6bbSMika Westerberg #define CHV_INTSTAT 0x300 306e08d6bbSMika Westerberg #define CHV_INTMASK 0x380 316e08d6bbSMika Westerberg 326e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_OFF 0x4400 336e08d6bbSMika Westerberg #define FAMILY_PAD_REGS_SIZE 0x400 346e08d6bbSMika Westerberg #define MAX_FAMILY_PAD_GPIO_NO 15 356e08d6bbSMika Westerberg #define GPIO_REGS_SIZE 8 366e08d6bbSMika Westerberg 376e08d6bbSMika Westerberg #define CHV_PADCTRL0 0x000 386e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_SHIFT 28 396e08d6bbSMika Westerberg #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) 406e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_UP BIT(23) 416e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_SHIFT 20 426e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) 436e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_20K 1 446e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_5K 2 456e08d6bbSMika Westerberg #define CHV_PADCTRL0_TERM_1K 4 466e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_SHIFT 16 476e08d6bbSMika Westerberg #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) 486e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOEN BIT(15) 496e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 506e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) 516e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPIO 0 526e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPO 1 536e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_GPI 2 546e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOCFG_HIZ 3 556e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 566e08d6bbSMika Westerberg #define CHV_PADCTRL0_GPIORXSTATE BIT(0) 576e08d6bbSMika Westerberg 586e08d6bbSMika Westerberg #define CHV_PADCTRL1 0x004 596e08d6bbSMika Westerberg #define CHV_PADCTRL1_CFGLOCK BIT(31) 606e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_SHIFT 4 616e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) 626e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) 636e08d6bbSMika Westerberg #define CHV_PADCTRL1_ODEN BIT(3) 646e08d6bbSMika Westerberg #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) 656e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_MASK 7 666e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 676e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_RISING 2 686e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 696e08d6bbSMika Westerberg #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 706e08d6bbSMika Westerberg 716e08d6bbSMika Westerberg /** 726e08d6bbSMika Westerberg * struct chv_alternate_function - A per group or per pin alternate function 736e08d6bbSMika Westerberg * @pin: Pin number (only used in per pin configs) 746e08d6bbSMika Westerberg * @mode: Mode the pin should be set in 756e08d6bbSMika Westerberg * @invert_oe: Invert OE for this pin 766e08d6bbSMika Westerberg */ 776e08d6bbSMika Westerberg struct chv_alternate_function { 786e08d6bbSMika Westerberg unsigned pin; 796e08d6bbSMika Westerberg u8 mode; 806e08d6bbSMika Westerberg bool invert_oe; 816e08d6bbSMika Westerberg }; 826e08d6bbSMika Westerberg 836e08d6bbSMika Westerberg /** 846e08d6bbSMika Westerberg * struct chv_pincgroup - describes a CHV pin group 856e08d6bbSMika Westerberg * @name: Name of the group 866e08d6bbSMika Westerberg * @pins: An array of pins in this group 876e08d6bbSMika Westerberg * @npins: Number of pins in this group 886e08d6bbSMika Westerberg * @altfunc: Alternate function applied to all pins in this group 896e08d6bbSMika Westerberg * @overrides: Alternate function override per pin or %NULL if not used 906e08d6bbSMika Westerberg * @noverrides: Number of per pin alternate function overrides if 916e08d6bbSMika Westerberg * @overrides != NULL. 926e08d6bbSMika Westerberg */ 936e08d6bbSMika Westerberg struct chv_pingroup { 946e08d6bbSMika Westerberg const char *name; 956e08d6bbSMika Westerberg const unsigned *pins; 966e08d6bbSMika Westerberg size_t npins; 976e08d6bbSMika Westerberg struct chv_alternate_function altfunc; 986e08d6bbSMika Westerberg const struct chv_alternate_function *overrides; 996e08d6bbSMika Westerberg size_t noverrides; 1006e08d6bbSMika Westerberg }; 1016e08d6bbSMika Westerberg 1026e08d6bbSMika Westerberg /** 1036e08d6bbSMika Westerberg * struct chv_function - A CHV pinmux function 1046e08d6bbSMika Westerberg * @name: Name of the function 1056e08d6bbSMika Westerberg * @groups: An array of groups for this function 1066e08d6bbSMika Westerberg * @ngroups: Number of groups in @groups 1076e08d6bbSMika Westerberg */ 1086e08d6bbSMika Westerberg struct chv_function { 1096e08d6bbSMika Westerberg const char *name; 1106e08d6bbSMika Westerberg const char * const *groups; 1116e08d6bbSMika Westerberg size_t ngroups; 1126e08d6bbSMika Westerberg }; 1136e08d6bbSMika Westerberg 1146e08d6bbSMika Westerberg /** 1156e08d6bbSMika Westerberg * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs 1166e08d6bbSMika Westerberg * @base: Start pin number 1176e08d6bbSMika Westerberg * @npins: Number of pins in this range 1186e08d6bbSMika Westerberg */ 1196e08d6bbSMika Westerberg struct chv_gpio_pinrange { 1206e08d6bbSMika Westerberg unsigned base; 1216e08d6bbSMika Westerberg unsigned npins; 1226e08d6bbSMika Westerberg }; 1236e08d6bbSMika Westerberg 1246e08d6bbSMika Westerberg /** 1256e08d6bbSMika Westerberg * struct chv_community - A community specific configuration 1266e08d6bbSMika Westerberg * @uid: ACPI _UID used to match the community 1276e08d6bbSMika Westerberg * @pins: All pins in this community 1286e08d6bbSMika Westerberg * @npins: Number of pins 1296e08d6bbSMika Westerberg * @groups: All groups in this community 1306e08d6bbSMika Westerberg * @ngroups: Number of groups 1316e08d6bbSMika Westerberg * @functions: All functions in this community 1326e08d6bbSMika Westerberg * @nfunctions: Number of functions 1336e08d6bbSMika Westerberg * @ngpios: Number of GPIOs in this community 1346e08d6bbSMika Westerberg * @gpio_ranges: An array of GPIO ranges in this community 1356e08d6bbSMika Westerberg * @ngpio_ranges: Number of GPIO ranges 1366e08d6bbSMika Westerberg * @ngpios: Total number of GPIOs in this community 13747c950d1SMika Westerberg * @nirqs: Total number of IRQs this community can generate 1386e08d6bbSMika Westerberg */ 1396e08d6bbSMika Westerberg struct chv_community { 1406e08d6bbSMika Westerberg const char *uid; 1416e08d6bbSMika Westerberg const struct pinctrl_pin_desc *pins; 1426e08d6bbSMika Westerberg size_t npins; 1436e08d6bbSMika Westerberg const struct chv_pingroup *groups; 1446e08d6bbSMika Westerberg size_t ngroups; 1456e08d6bbSMika Westerberg const struct chv_function *functions; 1466e08d6bbSMika Westerberg size_t nfunctions; 1476e08d6bbSMika Westerberg const struct chv_gpio_pinrange *gpio_ranges; 1486e08d6bbSMika Westerberg size_t ngpio_ranges; 1496e08d6bbSMika Westerberg size_t ngpios; 15047c950d1SMika Westerberg size_t nirqs; 1516e08d6bbSMika Westerberg }; 1526e08d6bbSMika Westerberg 1539eb457b5SMika Westerberg struct chv_pin_context { 1549eb457b5SMika Westerberg u32 padctrl0; 1559eb457b5SMika Westerberg u32 padctrl1; 1569eb457b5SMika Westerberg }; 1579eb457b5SMika Westerberg 1586e08d6bbSMika Westerberg /** 1596e08d6bbSMika Westerberg * struct chv_pinctrl - CHV pinctrl private structure 1606e08d6bbSMika Westerberg * @dev: Pointer to the parent device 1616e08d6bbSMika Westerberg * @pctldesc: Pin controller description 1626e08d6bbSMika Westerberg * @pctldev: Pointer to the pin controller device 1636e08d6bbSMika Westerberg * @chip: GPIO chip in this pin controller 1646e08d6bbSMika Westerberg * @regs: MMIO registers 1656e08d6bbSMika Westerberg * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO 1666e08d6bbSMika Westerberg * offset (in GPIO number space) 1676e08d6bbSMika Westerberg * @community: Community this pinctrl instance represents 1686e08d6bbSMika Westerberg * 1696e08d6bbSMika Westerberg * The first group in @groups is expected to contain all pins that can be 1706e08d6bbSMika Westerberg * used as GPIOs. 1716e08d6bbSMika Westerberg */ 1726e08d6bbSMika Westerberg struct chv_pinctrl { 1736e08d6bbSMika Westerberg struct device *dev; 1746e08d6bbSMika Westerberg struct pinctrl_desc pctldesc; 1756e08d6bbSMika Westerberg struct pinctrl_dev *pctldev; 1766e08d6bbSMika Westerberg struct gpio_chip chip; 1776e08d6bbSMika Westerberg void __iomem *regs; 1786e08d6bbSMika Westerberg unsigned intr_lines[16]; 1796e08d6bbSMika Westerberg const struct chv_community *community; 1809eb457b5SMika Westerberg u32 saved_intmask; 1819eb457b5SMika Westerberg struct chv_pin_context *saved_pin_context; 1826e08d6bbSMika Westerberg }; 1836e08d6bbSMika Westerberg 1846e08d6bbSMika Westerberg #define ALTERNATE_FUNCTION(p, m, i) \ 1856e08d6bbSMika Westerberg { \ 1866e08d6bbSMika Westerberg .pin = (p), \ 1876e08d6bbSMika Westerberg .mode = (m), \ 1886e08d6bbSMika Westerberg .invert_oe = (i), \ 1896e08d6bbSMika Westerberg } 1906e08d6bbSMika Westerberg 1916e08d6bbSMika Westerberg #define PIN_GROUP(n, p, m, i) \ 1926e08d6bbSMika Westerberg { \ 1936e08d6bbSMika Westerberg .name = (n), \ 1946e08d6bbSMika Westerberg .pins = (p), \ 1956e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 1966e08d6bbSMika Westerberg .altfunc.mode = (m), \ 1976e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 1986e08d6bbSMika Westerberg } 1996e08d6bbSMika Westerberg 2006e08d6bbSMika Westerberg #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ 2016e08d6bbSMika Westerberg { \ 2026e08d6bbSMika Westerberg .name = (n), \ 2036e08d6bbSMika Westerberg .pins = (p), \ 2046e08d6bbSMika Westerberg .npins = ARRAY_SIZE((p)), \ 2056e08d6bbSMika Westerberg .altfunc.mode = (m), \ 2066e08d6bbSMika Westerberg .altfunc.invert_oe = (i), \ 2076e08d6bbSMika Westerberg .overrides = (o), \ 2086e08d6bbSMika Westerberg .noverrides = ARRAY_SIZE((o)), \ 2096e08d6bbSMika Westerberg } 2106e08d6bbSMika Westerberg 2116e08d6bbSMika Westerberg #define FUNCTION(n, g) \ 2126e08d6bbSMika Westerberg { \ 2136e08d6bbSMika Westerberg .name = (n), \ 2146e08d6bbSMika Westerberg .groups = (g), \ 2156e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE((g)), \ 2166e08d6bbSMika Westerberg } 2176e08d6bbSMika Westerberg 2186e08d6bbSMika Westerberg #define GPIO_PINRANGE(start, end) \ 2196e08d6bbSMika Westerberg { \ 2206e08d6bbSMika Westerberg .base = (start), \ 2216e08d6bbSMika Westerberg .npins = (end) - (start) + 1, \ 2226e08d6bbSMika Westerberg } 2236e08d6bbSMika Westerberg 2246e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southwest_pins[] = { 2256e08d6bbSMika Westerberg PINCTRL_PIN(0, "FST_SPI_D2"), 2266e08d6bbSMika Westerberg PINCTRL_PIN(1, "FST_SPI_D0"), 2276e08d6bbSMika Westerberg PINCTRL_PIN(2, "FST_SPI_CLK"), 2286e08d6bbSMika Westerberg PINCTRL_PIN(3, "FST_SPI_D3"), 2296e08d6bbSMika Westerberg PINCTRL_PIN(4, "FST_SPI_CS1_B"), 2306e08d6bbSMika Westerberg PINCTRL_PIN(5, "FST_SPI_D1"), 2316e08d6bbSMika Westerberg PINCTRL_PIN(6, "FST_SPI_CS0_B"), 2326e08d6bbSMika Westerberg PINCTRL_PIN(7, "FST_SPI_CS2_B"), 2336e08d6bbSMika Westerberg 2346e08d6bbSMika Westerberg PINCTRL_PIN(15, "UART1_RTS_B"), 2356e08d6bbSMika Westerberg PINCTRL_PIN(16, "UART1_RXD"), 2366e08d6bbSMika Westerberg PINCTRL_PIN(17, "UART2_RXD"), 2376e08d6bbSMika Westerberg PINCTRL_PIN(18, "UART1_CTS_B"), 2386e08d6bbSMika Westerberg PINCTRL_PIN(19, "UART2_RTS_B"), 2396e08d6bbSMika Westerberg PINCTRL_PIN(20, "UART1_TXD"), 2406e08d6bbSMika Westerberg PINCTRL_PIN(21, "UART2_TXD"), 2416e08d6bbSMika Westerberg PINCTRL_PIN(22, "UART2_CTS_B"), 2426e08d6bbSMika Westerberg 2436e08d6bbSMika Westerberg PINCTRL_PIN(30, "MF_HDA_CLK"), 2446e08d6bbSMika Westerberg PINCTRL_PIN(31, "MF_HDA_RSTB"), 2456e08d6bbSMika Westerberg PINCTRL_PIN(32, "MF_HDA_SDIO"), 2466e08d6bbSMika Westerberg PINCTRL_PIN(33, "MF_HDA_SDO"), 2476e08d6bbSMika Westerberg PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 2486e08d6bbSMika Westerberg PINCTRL_PIN(35, "MF_HDA_SYNC"), 2496e08d6bbSMika Westerberg PINCTRL_PIN(36, "MF_HDA_SDI1"), 2506e08d6bbSMika Westerberg PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 2516e08d6bbSMika Westerberg 2526e08d6bbSMika Westerberg PINCTRL_PIN(45, "I2C5_SDA"), 2536e08d6bbSMika Westerberg PINCTRL_PIN(46, "I2C4_SDA"), 2546e08d6bbSMika Westerberg PINCTRL_PIN(47, "I2C6_SDA"), 2556e08d6bbSMika Westerberg PINCTRL_PIN(48, "I2C5_SCL"), 2566e08d6bbSMika Westerberg PINCTRL_PIN(49, "I2C_NFC_SDA"), 2576e08d6bbSMika Westerberg PINCTRL_PIN(50, "I2C4_SCL"), 2586e08d6bbSMika Westerberg PINCTRL_PIN(51, "I2C6_SCL"), 2596e08d6bbSMika Westerberg PINCTRL_PIN(52, "I2C_NFC_SCL"), 2606e08d6bbSMika Westerberg 2616e08d6bbSMika Westerberg PINCTRL_PIN(60, "I2C1_SDA"), 2626e08d6bbSMika Westerberg PINCTRL_PIN(61, "I2C0_SDA"), 2636e08d6bbSMika Westerberg PINCTRL_PIN(62, "I2C2_SDA"), 2646e08d6bbSMika Westerberg PINCTRL_PIN(63, "I2C1_SCL"), 2656e08d6bbSMika Westerberg PINCTRL_PIN(64, "I2C3_SDA"), 2666e08d6bbSMika Westerberg PINCTRL_PIN(65, "I2C0_SCL"), 2676e08d6bbSMika Westerberg PINCTRL_PIN(66, "I2C2_SCL"), 2686e08d6bbSMika Westerberg PINCTRL_PIN(67, "I2C3_SCL"), 2696e08d6bbSMika Westerberg 2706e08d6bbSMika Westerberg PINCTRL_PIN(75, "SATA_GP0"), 2716e08d6bbSMika Westerberg PINCTRL_PIN(76, "SATA_GP1"), 2726e08d6bbSMika Westerberg PINCTRL_PIN(77, "SATA_LEDN"), 2736e08d6bbSMika Westerberg PINCTRL_PIN(78, "SATA_GP2"), 2746e08d6bbSMika Westerberg PINCTRL_PIN(79, "MF_SMB_ALERTB"), 2756e08d6bbSMika Westerberg PINCTRL_PIN(80, "SATA_GP3"), 2766e08d6bbSMika Westerberg PINCTRL_PIN(81, "MF_SMB_CLK"), 2776e08d6bbSMika Westerberg PINCTRL_PIN(82, "MF_SMB_DATA"), 2786e08d6bbSMika Westerberg 2796e08d6bbSMika Westerberg PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 2806e08d6bbSMika Westerberg PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 2816e08d6bbSMika Westerberg PINCTRL_PIN(92, "GP_SSP_2_CLK"), 2826e08d6bbSMika Westerberg PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 2836e08d6bbSMika Westerberg PINCTRL_PIN(94, "GP_SSP_2_RXD"), 2846e08d6bbSMika Westerberg PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 2856e08d6bbSMika Westerberg PINCTRL_PIN(96, "GP_SSP_2_FS"), 2866e08d6bbSMika Westerberg PINCTRL_PIN(97, "GP_SSP_2_TXD"), 2876e08d6bbSMika Westerberg }; 2886e08d6bbSMika Westerberg 2896e08d6bbSMika Westerberg static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; 2906e08d6bbSMika Westerberg static const unsigned southwest_uart0_pins[] = { 16, 20 }; 2916e08d6bbSMika Westerberg static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 2926e08d6bbSMika Westerberg static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 2936e08d6bbSMika Westerberg static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 2946e08d6bbSMika Westerberg static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 2956e08d6bbSMika Westerberg static const unsigned southwest_lpe_pins[] = { 2966e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 2976e08d6bbSMika Westerberg }; 2986e08d6bbSMika Westerberg static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 2996e08d6bbSMika Westerberg static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 3006e08d6bbSMika Westerberg static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 3016e08d6bbSMika Westerberg static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 3026e08d6bbSMika Westerberg static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 3036e08d6bbSMika Westerberg static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 3046e08d6bbSMika Westerberg static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 3056e08d6bbSMika Westerberg static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; 3066e08d6bbSMika Westerberg static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 3076e08d6bbSMika Westerberg 3086e08d6bbSMika Westerberg /* LPE I2S TXD pins need to have invert_oe set */ 3096e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_lpe_altfuncs[] = { 3106e08d6bbSMika Westerberg ALTERNATE_FUNCTION(30, 1, true), 3116e08d6bbSMika Westerberg ALTERNATE_FUNCTION(34, 1, true), 3126e08d6bbSMika Westerberg ALTERNATE_FUNCTION(97, 1, true), 3136e08d6bbSMika Westerberg }; 3146e08d6bbSMika Westerberg 3156e08d6bbSMika Westerberg /* 3166e08d6bbSMika Westerberg * Two spi3 chipselects are available in different mode than the main spi3 3176e08d6bbSMika Westerberg * functionality, which is using mode 1. 3186e08d6bbSMika Westerberg */ 3196e08d6bbSMika Westerberg static const struct chv_alternate_function southwest_spi3_altfuncs[] = { 3206e08d6bbSMika Westerberg ALTERNATE_FUNCTION(76, 3, false), 3216e08d6bbSMika Westerberg ALTERNATE_FUNCTION(80, 3, false), 3226e08d6bbSMika Westerberg }; 3236e08d6bbSMika Westerberg 3246e08d6bbSMika Westerberg static const struct chv_pingroup southwest_groups[] = { 3256e08d6bbSMika Westerberg PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), 3266e08d6bbSMika Westerberg PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), 3276e08d6bbSMika Westerberg PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), 3286e08d6bbSMika Westerberg PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), 3296e08d6bbSMika Westerberg PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), 3306e08d6bbSMika Westerberg PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), 3316e08d6bbSMika Westerberg PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), 3326e08d6bbSMika Westerberg PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), 3336e08d6bbSMika Westerberg PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), 3346e08d6bbSMika Westerberg PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), 3356e08d6bbSMika Westerberg PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), 3366e08d6bbSMika Westerberg PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), 3376e08d6bbSMika Westerberg 3386e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, 3396e08d6bbSMika Westerberg southwest_lpe_altfuncs), 3406e08d6bbSMika Westerberg PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, 3416e08d6bbSMika Westerberg southwest_spi3_altfuncs), 3426e08d6bbSMika Westerberg }; 3436e08d6bbSMika Westerberg 3446e08d6bbSMika Westerberg static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 3456e08d6bbSMika Westerberg static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 3466e08d6bbSMika Westerberg static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 3476e08d6bbSMika Westerberg static const char * const southwest_hda_groups[] = { "hda_grp" }; 3486e08d6bbSMika Westerberg static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 3496e08d6bbSMika Westerberg static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 3506e08d6bbSMika Westerberg static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 3516e08d6bbSMika Westerberg static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 3526e08d6bbSMika Westerberg static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 3536e08d6bbSMika Westerberg static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 3546e08d6bbSMika Westerberg static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 3556e08d6bbSMika Westerberg static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 3566e08d6bbSMika Westerberg static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 3576e08d6bbSMika Westerberg static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 3586e08d6bbSMika Westerberg 3596e08d6bbSMika Westerberg /* 3606e08d6bbSMika Westerberg * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 3616e08d6bbSMika Westerberg * enabled only as GPIOs. 3626e08d6bbSMika Westerberg */ 3636e08d6bbSMika Westerberg static const struct chv_function southwest_functions[] = { 3646e08d6bbSMika Westerberg FUNCTION("uart0", southwest_uart0_groups), 3656e08d6bbSMika Westerberg FUNCTION("uart1", southwest_uart1_groups), 3666e08d6bbSMika Westerberg FUNCTION("uart2", southwest_uart2_groups), 3676e08d6bbSMika Westerberg FUNCTION("hda", southwest_hda_groups), 3686e08d6bbSMika Westerberg FUNCTION("lpe", southwest_lpe_groups), 3696e08d6bbSMika Westerberg FUNCTION("i2c0", southwest_i2c0_groups), 3706e08d6bbSMika Westerberg FUNCTION("i2c1", southwest_i2c1_groups), 3716e08d6bbSMika Westerberg FUNCTION("i2c2", southwest_i2c2_groups), 3726e08d6bbSMika Westerberg FUNCTION("i2c3", southwest_i2c3_groups), 3736e08d6bbSMika Westerberg FUNCTION("i2c4", southwest_i2c4_groups), 3746e08d6bbSMika Westerberg FUNCTION("i2c5", southwest_i2c5_groups), 3756e08d6bbSMika Westerberg FUNCTION("i2c6", southwest_i2c6_groups), 3766e08d6bbSMika Westerberg FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 3776e08d6bbSMika Westerberg FUNCTION("spi3", southwest_spi3_groups), 3786e08d6bbSMika Westerberg }; 3796e08d6bbSMika Westerberg 3806e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { 3816e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 3826e08d6bbSMika Westerberg GPIO_PINRANGE(15, 22), 3836e08d6bbSMika Westerberg GPIO_PINRANGE(30, 37), 3846e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 3856e08d6bbSMika Westerberg GPIO_PINRANGE(60, 67), 3866e08d6bbSMika Westerberg GPIO_PINRANGE(75, 82), 3876e08d6bbSMika Westerberg GPIO_PINRANGE(90, 97), 3886e08d6bbSMika Westerberg }; 3896e08d6bbSMika Westerberg 3906e08d6bbSMika Westerberg static const struct chv_community southwest_community = { 3916e08d6bbSMika Westerberg .uid = "1", 3926e08d6bbSMika Westerberg .pins = southwest_pins, 3936e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southwest_pins), 3946e08d6bbSMika Westerberg .groups = southwest_groups, 3956e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southwest_groups), 3966e08d6bbSMika Westerberg .functions = southwest_functions, 3976e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southwest_functions), 3986e08d6bbSMika Westerberg .gpio_ranges = southwest_gpio_ranges, 3996e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), 4006e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(southwest_pins), 40147c950d1SMika Westerberg /* 40247c950d1SMika Westerberg * Southwest community can benerate GPIO interrupts only for the 40347c950d1SMika Westerberg * first 8 interrupts. The upper half (8-15) can only be used to 40447c950d1SMika Westerberg * trigger GPEs. 40547c950d1SMika Westerberg */ 40647c950d1SMika Westerberg .nirqs = 8, 4076e08d6bbSMika Westerberg }; 4086e08d6bbSMika Westerberg 4096e08d6bbSMika Westerberg static const struct pinctrl_pin_desc north_pins[] = { 4106e08d6bbSMika Westerberg PINCTRL_PIN(0, "GPIO_DFX_0"), 4116e08d6bbSMika Westerberg PINCTRL_PIN(1, "GPIO_DFX_3"), 4126e08d6bbSMika Westerberg PINCTRL_PIN(2, "GPIO_DFX_7"), 4136e08d6bbSMika Westerberg PINCTRL_PIN(3, "GPIO_DFX_1"), 4146e08d6bbSMika Westerberg PINCTRL_PIN(4, "GPIO_DFX_5"), 4156e08d6bbSMika Westerberg PINCTRL_PIN(5, "GPIO_DFX_4"), 4166e08d6bbSMika Westerberg PINCTRL_PIN(6, "GPIO_DFX_8"), 4176e08d6bbSMika Westerberg PINCTRL_PIN(7, "GPIO_DFX_2"), 4186e08d6bbSMika Westerberg PINCTRL_PIN(8, "GPIO_DFX_6"), 4196e08d6bbSMika Westerberg 4206e08d6bbSMika Westerberg PINCTRL_PIN(15, "GPIO_SUS0"), 4216e08d6bbSMika Westerberg PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 4226e08d6bbSMika Westerberg PINCTRL_PIN(17, "GPIO_SUS3"), 4236e08d6bbSMika Westerberg PINCTRL_PIN(18, "GPIO_SUS7"), 4246e08d6bbSMika Westerberg PINCTRL_PIN(19, "GPIO_SUS1"), 4256e08d6bbSMika Westerberg PINCTRL_PIN(20, "GPIO_SUS5"), 4266e08d6bbSMika Westerberg PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 4276e08d6bbSMika Westerberg PINCTRL_PIN(22, "GPIO_SUS4"), 4286e08d6bbSMika Westerberg PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 4296e08d6bbSMika Westerberg PINCTRL_PIN(24, "GPIO_SUS2"), 4306e08d6bbSMika Westerberg PINCTRL_PIN(25, "GPIO_SUS6"), 4316e08d6bbSMika Westerberg PINCTRL_PIN(26, "CX_PREQ_B"), 4326e08d6bbSMika Westerberg PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 4336e08d6bbSMika Westerberg 4346e08d6bbSMika Westerberg PINCTRL_PIN(30, "TRST_B"), 4356e08d6bbSMika Westerberg PINCTRL_PIN(31, "TCK"), 4366e08d6bbSMika Westerberg PINCTRL_PIN(32, "PROCHOT_B"), 4376e08d6bbSMika Westerberg PINCTRL_PIN(33, "SVIDO_DATA"), 4386e08d6bbSMika Westerberg PINCTRL_PIN(34, "TMS"), 4396e08d6bbSMika Westerberg PINCTRL_PIN(35, "CX_PRDY_B_2"), 4406e08d6bbSMika Westerberg PINCTRL_PIN(36, "TDO_2"), 4416e08d6bbSMika Westerberg PINCTRL_PIN(37, "CX_PRDY_B"), 4426e08d6bbSMika Westerberg PINCTRL_PIN(38, "SVIDO_ALERT_B"), 4436e08d6bbSMika Westerberg PINCTRL_PIN(39, "TDO"), 4446e08d6bbSMika Westerberg PINCTRL_PIN(40, "SVIDO_CLK"), 4456e08d6bbSMika Westerberg PINCTRL_PIN(41, "TDI"), 4466e08d6bbSMika Westerberg 4476e08d6bbSMika Westerberg PINCTRL_PIN(45, "GP_CAMERASB_05"), 4486e08d6bbSMika Westerberg PINCTRL_PIN(46, "GP_CAMERASB_02"), 4496e08d6bbSMika Westerberg PINCTRL_PIN(47, "GP_CAMERASB_08"), 4506e08d6bbSMika Westerberg PINCTRL_PIN(48, "GP_CAMERASB_00"), 4516e08d6bbSMika Westerberg PINCTRL_PIN(49, "GP_CAMERASB_06"), 4526e08d6bbSMika Westerberg PINCTRL_PIN(50, "GP_CAMERASB_10"), 4536e08d6bbSMika Westerberg PINCTRL_PIN(51, "GP_CAMERASB_03"), 4546e08d6bbSMika Westerberg PINCTRL_PIN(52, "GP_CAMERASB_09"), 4556e08d6bbSMika Westerberg PINCTRL_PIN(53, "GP_CAMERASB_01"), 4566e08d6bbSMika Westerberg PINCTRL_PIN(54, "GP_CAMERASB_07"), 4576e08d6bbSMika Westerberg PINCTRL_PIN(55, "GP_CAMERASB_11"), 4586e08d6bbSMika Westerberg PINCTRL_PIN(56, "GP_CAMERASB_04"), 4596e08d6bbSMika Westerberg 4606e08d6bbSMika Westerberg PINCTRL_PIN(60, "PANEL0_BKLTEN"), 4616e08d6bbSMika Westerberg PINCTRL_PIN(61, "HV_DDI0_HPD"), 4626e08d6bbSMika Westerberg PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 4636e08d6bbSMika Westerberg PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 4646e08d6bbSMika Westerberg PINCTRL_PIN(64, "HV_DDI1_HPD"), 4656e08d6bbSMika Westerberg PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 4666e08d6bbSMika Westerberg PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 4676e08d6bbSMika Westerberg PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 4686e08d6bbSMika Westerberg PINCTRL_PIN(68, "HV_DDI2_HPD"), 4696e08d6bbSMika Westerberg PINCTRL_PIN(69, "PANEL1_VDDEN"), 4706e08d6bbSMika Westerberg PINCTRL_PIN(70, "PANEL1_BKLTEN"), 4716e08d6bbSMika Westerberg PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 4726e08d6bbSMika Westerberg PINCTRL_PIN(72, "PANEL0_VDDEN"), 4736e08d6bbSMika Westerberg }; 4746e08d6bbSMika Westerberg 4756e08d6bbSMika Westerberg static const struct chv_gpio_pinrange north_gpio_ranges[] = { 4766e08d6bbSMika Westerberg GPIO_PINRANGE(0, 8), 4776e08d6bbSMika Westerberg GPIO_PINRANGE(15, 27), 4786e08d6bbSMika Westerberg GPIO_PINRANGE(30, 41), 4796e08d6bbSMika Westerberg GPIO_PINRANGE(45, 56), 4806e08d6bbSMika Westerberg GPIO_PINRANGE(60, 72), 4816e08d6bbSMika Westerberg }; 4826e08d6bbSMika Westerberg 4836e08d6bbSMika Westerberg static const struct chv_community north_community = { 4846e08d6bbSMika Westerberg .uid = "2", 4856e08d6bbSMika Westerberg .pins = north_pins, 4866e08d6bbSMika Westerberg .npins = ARRAY_SIZE(north_pins), 4876e08d6bbSMika Westerberg .gpio_ranges = north_gpio_ranges, 4886e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 4896e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(north_pins), 49047c950d1SMika Westerberg /* 49147c950d1SMika Westerberg * North community can benerate GPIO interrupts only for the first 49247c950d1SMika Westerberg * 8 interrupts. The upper half (8-15) can only be used to trigger 49347c950d1SMika Westerberg * GPEs. 49447c950d1SMika Westerberg */ 49547c950d1SMika Westerberg .nirqs = 8, 4966e08d6bbSMika Westerberg }; 4976e08d6bbSMika Westerberg 4986e08d6bbSMika Westerberg static const struct pinctrl_pin_desc east_pins[] = { 4996e08d6bbSMika Westerberg PINCTRL_PIN(0, "PMU_SLP_S3_B"), 5006e08d6bbSMika Westerberg PINCTRL_PIN(1, "PMU_BATLOW_B"), 5016e08d6bbSMika Westerberg PINCTRL_PIN(2, "SUS_STAT_B"), 5026e08d6bbSMika Westerberg PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 5036e08d6bbSMika Westerberg PINCTRL_PIN(4, "PMU_AC_PRESENT"), 5046e08d6bbSMika Westerberg PINCTRL_PIN(5, "PMU_PLTRST_B"), 5056e08d6bbSMika Westerberg PINCTRL_PIN(6, "PMU_SUSCLK"), 5066e08d6bbSMika Westerberg PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 5076e08d6bbSMika Westerberg PINCTRL_PIN(8, "PMU_PWRBTN_B"), 5086e08d6bbSMika Westerberg PINCTRL_PIN(9, "PMU_SLP_S4_B"), 5096e08d6bbSMika Westerberg PINCTRL_PIN(10, "PMU_WAKE_B"), 5106e08d6bbSMika Westerberg PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 5116e08d6bbSMika Westerberg 5126e08d6bbSMika Westerberg PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 5136e08d6bbSMika Westerberg PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 5146e08d6bbSMika Westerberg PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 5156e08d6bbSMika Westerberg PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 5166e08d6bbSMika Westerberg PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 5176e08d6bbSMika Westerberg PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 5186e08d6bbSMika Westerberg PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 5196e08d6bbSMika Westerberg PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 5206e08d6bbSMika Westerberg PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 5216e08d6bbSMika Westerberg PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 5226e08d6bbSMika Westerberg PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 5236e08d6bbSMika Westerberg PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 5246e08d6bbSMika Westerberg }; 5256e08d6bbSMika Westerberg 5266e08d6bbSMika Westerberg static const struct chv_gpio_pinrange east_gpio_ranges[] = { 5276e08d6bbSMika Westerberg GPIO_PINRANGE(0, 11), 5286e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 5296e08d6bbSMika Westerberg }; 5306e08d6bbSMika Westerberg 5316e08d6bbSMika Westerberg static const struct chv_community east_community = { 5326e08d6bbSMika Westerberg .uid = "3", 5336e08d6bbSMika Westerberg .pins = east_pins, 5346e08d6bbSMika Westerberg .npins = ARRAY_SIZE(east_pins), 5356e08d6bbSMika Westerberg .gpio_ranges = east_gpio_ranges, 5366e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), 5376e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(east_pins), 53847c950d1SMika Westerberg .nirqs = 16, 5396e08d6bbSMika Westerberg }; 5406e08d6bbSMika Westerberg 5416e08d6bbSMika Westerberg static const struct pinctrl_pin_desc southeast_pins[] = { 5426e08d6bbSMika Westerberg PINCTRL_PIN(0, "MF_PLT_CLK0"), 5436e08d6bbSMika Westerberg PINCTRL_PIN(1, "PWM1"), 5446e08d6bbSMika Westerberg PINCTRL_PIN(2, "MF_PLT_CLK1"), 5456e08d6bbSMika Westerberg PINCTRL_PIN(3, "MF_PLT_CLK4"), 5466e08d6bbSMika Westerberg PINCTRL_PIN(4, "MF_PLT_CLK3"), 5476e08d6bbSMika Westerberg PINCTRL_PIN(5, "PWM0"), 5486e08d6bbSMika Westerberg PINCTRL_PIN(6, "MF_PLT_CLK5"), 5496e08d6bbSMika Westerberg PINCTRL_PIN(7, "MF_PLT_CLK2"), 5506e08d6bbSMika Westerberg 5516e08d6bbSMika Westerberg PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 5526e08d6bbSMika Westerberg PINCTRL_PIN(16, "SDMMC1_CLK"), 5536e08d6bbSMika Westerberg PINCTRL_PIN(17, "SDMMC1_D0"), 5546e08d6bbSMika Westerberg PINCTRL_PIN(18, "SDMMC2_D1"), 5556e08d6bbSMika Westerberg PINCTRL_PIN(19, "SDMMC2_CLK"), 5566e08d6bbSMika Westerberg PINCTRL_PIN(20, "SDMMC1_D2"), 5576e08d6bbSMika Westerberg PINCTRL_PIN(21, "SDMMC2_D2"), 5586e08d6bbSMika Westerberg PINCTRL_PIN(22, "SDMMC2_CMD"), 5596e08d6bbSMika Westerberg PINCTRL_PIN(23, "SDMMC1_CMD"), 5606e08d6bbSMika Westerberg PINCTRL_PIN(24, "SDMMC1_D1"), 5616e08d6bbSMika Westerberg PINCTRL_PIN(25, "SDMMC2_D0"), 5626e08d6bbSMika Westerberg PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 5636e08d6bbSMika Westerberg 5646e08d6bbSMika Westerberg PINCTRL_PIN(30, "SDMMC3_D1"), 5656e08d6bbSMika Westerberg PINCTRL_PIN(31, "SDMMC3_CLK"), 5666e08d6bbSMika Westerberg PINCTRL_PIN(32, "SDMMC3_D3"), 5676e08d6bbSMika Westerberg PINCTRL_PIN(33, "SDMMC3_D2"), 5686e08d6bbSMika Westerberg PINCTRL_PIN(34, "SDMMC3_CMD"), 5696e08d6bbSMika Westerberg PINCTRL_PIN(35, "SDMMC3_D0"), 5706e08d6bbSMika Westerberg 5716e08d6bbSMika Westerberg PINCTRL_PIN(45, "MF_LPC_AD2"), 5726e08d6bbSMika Westerberg PINCTRL_PIN(46, "LPC_CLKRUNB"), 5736e08d6bbSMika Westerberg PINCTRL_PIN(47, "MF_LPC_AD0"), 5746e08d6bbSMika Westerberg PINCTRL_PIN(48, "LPC_FRAMEB"), 5756e08d6bbSMika Westerberg PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 5766e08d6bbSMika Westerberg PINCTRL_PIN(50, "MF_LPC_AD3"), 5776e08d6bbSMika Westerberg PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 5786e08d6bbSMika Westerberg PINCTRL_PIN(52, "MF_LPC_AD1"), 5796e08d6bbSMika Westerberg 5806e08d6bbSMika Westerberg PINCTRL_PIN(60, "SPI1_MISO"), 5816e08d6bbSMika Westerberg PINCTRL_PIN(61, "SPI1_CSO_B"), 5826e08d6bbSMika Westerberg PINCTRL_PIN(62, "SPI1_CLK"), 5836e08d6bbSMika Westerberg PINCTRL_PIN(63, "MMC1_D6"), 5846e08d6bbSMika Westerberg PINCTRL_PIN(64, "SPI1_MOSI"), 5856e08d6bbSMika Westerberg PINCTRL_PIN(65, "MMC1_D5"), 5866e08d6bbSMika Westerberg PINCTRL_PIN(66, "SPI1_CS1_B"), 5876e08d6bbSMika Westerberg PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 5886e08d6bbSMika Westerberg PINCTRL_PIN(68, "MMC1_D7"), 5896e08d6bbSMika Westerberg PINCTRL_PIN(69, "MMC1_RCLK"), 5906e08d6bbSMika Westerberg 5916e08d6bbSMika Westerberg PINCTRL_PIN(75, "USB_OC1_B"), 5926e08d6bbSMika Westerberg PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 5936e08d6bbSMika Westerberg PINCTRL_PIN(77, "GPIO_ALERT"), 5946e08d6bbSMika Westerberg PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 5956e08d6bbSMika Westerberg PINCTRL_PIN(79, "ILB_SERIRQ"), 5966e08d6bbSMika Westerberg PINCTRL_PIN(80, "USB_OC0_B"), 5976e08d6bbSMika Westerberg PINCTRL_PIN(81, "SDMMC3_CD_B"), 5986e08d6bbSMika Westerberg PINCTRL_PIN(82, "SPKR"), 5996e08d6bbSMika Westerberg PINCTRL_PIN(83, "SUSPWRDNACK"), 6006e08d6bbSMika Westerberg PINCTRL_PIN(84, "SPARE_PIN"), 6016e08d6bbSMika Westerberg PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 6026e08d6bbSMika Westerberg }; 6036e08d6bbSMika Westerberg 6046e08d6bbSMika Westerberg static const unsigned southeast_pwm0_pins[] = { 5 }; 6056e08d6bbSMika Westerberg static const unsigned southeast_pwm1_pins[] = { 1 }; 6066e08d6bbSMika Westerberg static const unsigned southeast_sdmmc1_pins[] = { 6076e08d6bbSMika Westerberg 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 6086e08d6bbSMika Westerberg }; 6096e08d6bbSMika Westerberg static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 6106e08d6bbSMika Westerberg static const unsigned southeast_sdmmc3_pins[] = { 6116e08d6bbSMika Westerberg 30, 31, 32, 33, 34, 35, 78, 81, 85, 6126e08d6bbSMika Westerberg }; 6136e08d6bbSMika Westerberg static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 6146e08d6bbSMika Westerberg static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 6156e08d6bbSMika Westerberg 6166e08d6bbSMika Westerberg static const struct chv_pingroup southeast_groups[] = { 6176e08d6bbSMika Westerberg PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), 6186e08d6bbSMika Westerberg PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), 6196e08d6bbSMika Westerberg PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), 6206e08d6bbSMika Westerberg PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), 6216e08d6bbSMika Westerberg PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), 6226e08d6bbSMika Westerberg PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), 6236e08d6bbSMika Westerberg PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), 6246e08d6bbSMika Westerberg }; 6256e08d6bbSMika Westerberg 6266e08d6bbSMika Westerberg static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 6276e08d6bbSMika Westerberg static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 6286e08d6bbSMika Westerberg static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 6296e08d6bbSMika Westerberg static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 6306e08d6bbSMika Westerberg static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 6316e08d6bbSMika Westerberg static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 6326e08d6bbSMika Westerberg static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 6336e08d6bbSMika Westerberg 6346e08d6bbSMika Westerberg static const struct chv_function southeast_functions[] = { 6356e08d6bbSMika Westerberg FUNCTION("pwm0", southeast_pwm0_groups), 6366e08d6bbSMika Westerberg FUNCTION("pwm1", southeast_pwm1_groups), 6376e08d6bbSMika Westerberg FUNCTION("sdmmc1", southeast_sdmmc1_groups), 6386e08d6bbSMika Westerberg FUNCTION("sdmmc2", southeast_sdmmc2_groups), 6396e08d6bbSMika Westerberg FUNCTION("sdmmc3", southeast_sdmmc3_groups), 6406e08d6bbSMika Westerberg FUNCTION("spi1", southeast_spi1_groups), 6416e08d6bbSMika Westerberg FUNCTION("spi2", southeast_spi2_groups), 6426e08d6bbSMika Westerberg }; 6436e08d6bbSMika Westerberg 6446e08d6bbSMika Westerberg static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { 6456e08d6bbSMika Westerberg GPIO_PINRANGE(0, 7), 6466e08d6bbSMika Westerberg GPIO_PINRANGE(15, 26), 6476e08d6bbSMika Westerberg GPIO_PINRANGE(30, 35), 6486e08d6bbSMika Westerberg GPIO_PINRANGE(45, 52), 6496e08d6bbSMika Westerberg GPIO_PINRANGE(60, 69), 6506e08d6bbSMika Westerberg GPIO_PINRANGE(75, 85), 6516e08d6bbSMika Westerberg }; 6526e08d6bbSMika Westerberg 6536e08d6bbSMika Westerberg static const struct chv_community southeast_community = { 6546e08d6bbSMika Westerberg .uid = "4", 6556e08d6bbSMika Westerberg .pins = southeast_pins, 6566e08d6bbSMika Westerberg .npins = ARRAY_SIZE(southeast_pins), 6576e08d6bbSMika Westerberg .groups = southeast_groups, 6586e08d6bbSMika Westerberg .ngroups = ARRAY_SIZE(southeast_groups), 6596e08d6bbSMika Westerberg .functions = southeast_functions, 6606e08d6bbSMika Westerberg .nfunctions = ARRAY_SIZE(southeast_functions), 6616e08d6bbSMika Westerberg .gpio_ranges = southeast_gpio_ranges, 6626e08d6bbSMika Westerberg .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), 6636e08d6bbSMika Westerberg .ngpios = ARRAY_SIZE(southeast_pins), 66447c950d1SMika Westerberg .nirqs = 16, 6656e08d6bbSMika Westerberg }; 6666e08d6bbSMika Westerberg 6676e08d6bbSMika Westerberg static const struct chv_community *chv_communities[] = { 6686e08d6bbSMika Westerberg &southwest_community, 6696e08d6bbSMika Westerberg &north_community, 6706e08d6bbSMika Westerberg &east_community, 6716e08d6bbSMika Westerberg &southeast_community, 6726e08d6bbSMika Westerberg }; 6736e08d6bbSMika Westerberg 6740bd50d71SDan O'Donovan /* 6750bd50d71SDan O'Donovan * Lock to serialize register accesses 6760bd50d71SDan O'Donovan * 6770bd50d71SDan O'Donovan * Due to a silicon issue, a shared lock must be used to prevent 6780bd50d71SDan O'Donovan * concurrent accesses across the 4 GPIO controllers. 6790bd50d71SDan O'Donovan * 6800bd50d71SDan O'Donovan * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 6810bd50d71SDan O'Donovan * errata #CHT34, for further information. 6820bd50d71SDan O'Donovan */ 6830bd50d71SDan O'Donovan static DEFINE_RAW_SPINLOCK(chv_lock); 6840bd50d71SDan O'Donovan 6856e08d6bbSMika Westerberg static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, 6866e08d6bbSMika Westerberg unsigned reg) 6876e08d6bbSMika Westerberg { 6886e08d6bbSMika Westerberg unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 6896e08d6bbSMika Westerberg unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 6906e08d6bbSMika Westerberg 6916e08d6bbSMika Westerberg offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + 6926e08d6bbSMika Westerberg GPIO_REGS_SIZE * pad_no; 6936e08d6bbSMika Westerberg 6946e08d6bbSMika Westerberg return pctrl->regs + offset + reg; 6956e08d6bbSMika Westerberg } 6966e08d6bbSMika Westerberg 6976e08d6bbSMika Westerberg static void chv_writel(u32 value, void __iomem *reg) 6986e08d6bbSMika Westerberg { 6996e08d6bbSMika Westerberg writel(value, reg); 7006e08d6bbSMika Westerberg /* simple readback to confirm the bus transferring done */ 7016e08d6bbSMika Westerberg readl(reg); 7026e08d6bbSMika Westerberg } 7036e08d6bbSMika Westerberg 7046e08d6bbSMika Westerberg /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 7056e08d6bbSMika Westerberg static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) 7066e08d6bbSMika Westerberg { 7076e08d6bbSMika Westerberg void __iomem *reg; 7086e08d6bbSMika Westerberg 7096e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 7106e08d6bbSMika Westerberg return readl(reg) & CHV_PADCTRL1_CFGLOCK; 7116e08d6bbSMika Westerberg } 7126e08d6bbSMika Westerberg 7136e08d6bbSMika Westerberg static int chv_get_groups_count(struct pinctrl_dev *pctldev) 7146e08d6bbSMika Westerberg { 7156e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7166e08d6bbSMika Westerberg 7176e08d6bbSMika Westerberg return pctrl->community->ngroups; 7186e08d6bbSMika Westerberg } 7196e08d6bbSMika Westerberg 7206e08d6bbSMika Westerberg static const char *chv_get_group_name(struct pinctrl_dev *pctldev, 7216e08d6bbSMika Westerberg unsigned group) 7226e08d6bbSMika Westerberg { 7236e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7246e08d6bbSMika Westerberg 7256e08d6bbSMika Westerberg return pctrl->community->groups[group].name; 7266e08d6bbSMika Westerberg } 7276e08d6bbSMika Westerberg 7286e08d6bbSMika Westerberg static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 7296e08d6bbSMika Westerberg const unsigned **pins, unsigned *npins) 7306e08d6bbSMika Westerberg { 7316e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7326e08d6bbSMika Westerberg 7336e08d6bbSMika Westerberg *pins = pctrl->community->groups[group].pins; 7346e08d6bbSMika Westerberg *npins = pctrl->community->groups[group].npins; 7356e08d6bbSMika Westerberg return 0; 7366e08d6bbSMika Westerberg } 7376e08d6bbSMika Westerberg 7386e08d6bbSMika Westerberg static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 7396e08d6bbSMika Westerberg unsigned offset) 7406e08d6bbSMika Westerberg { 7416e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7426e08d6bbSMika Westerberg unsigned long flags; 7436e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 7446e08d6bbSMika Westerberg bool locked; 7456e08d6bbSMika Westerberg 7460bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 7476e08d6bbSMika Westerberg 7486e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 7496e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 7506e08d6bbSMika Westerberg locked = chv_pad_locked(pctrl, offset); 7516e08d6bbSMika Westerberg 7520bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 7536e08d6bbSMika Westerberg 7546e08d6bbSMika Westerberg if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 7556e08d6bbSMika Westerberg seq_puts(s, "GPIO "); 7566e08d6bbSMika Westerberg } else { 7576e08d6bbSMika Westerberg u32 mode; 7586e08d6bbSMika Westerberg 7596e08d6bbSMika Westerberg mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 7606e08d6bbSMika Westerberg mode >>= CHV_PADCTRL0_PMODE_SHIFT; 7616e08d6bbSMika Westerberg 7626e08d6bbSMika Westerberg seq_printf(s, "mode %d ", mode); 7636e08d6bbSMika Westerberg } 7646e08d6bbSMika Westerberg 7656e08d6bbSMika Westerberg seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1); 7666e08d6bbSMika Westerberg 7676e08d6bbSMika Westerberg if (locked) 7686e08d6bbSMika Westerberg seq_puts(s, " [LOCKED]"); 7696e08d6bbSMika Westerberg } 7706e08d6bbSMika Westerberg 7716e08d6bbSMika Westerberg static const struct pinctrl_ops chv_pinctrl_ops = { 7726e08d6bbSMika Westerberg .get_groups_count = chv_get_groups_count, 7736e08d6bbSMika Westerberg .get_group_name = chv_get_group_name, 7746e08d6bbSMika Westerberg .get_group_pins = chv_get_group_pins, 7756e08d6bbSMika Westerberg .pin_dbg_show = chv_pin_dbg_show, 7766e08d6bbSMika Westerberg }; 7776e08d6bbSMika Westerberg 7786e08d6bbSMika Westerberg static int chv_get_functions_count(struct pinctrl_dev *pctldev) 7796e08d6bbSMika Westerberg { 7806e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7816e08d6bbSMika Westerberg 7826e08d6bbSMika Westerberg return pctrl->community->nfunctions; 7836e08d6bbSMika Westerberg } 7846e08d6bbSMika Westerberg 7856e08d6bbSMika Westerberg static const char *chv_get_function_name(struct pinctrl_dev *pctldev, 7866e08d6bbSMika Westerberg unsigned function) 7876e08d6bbSMika Westerberg { 7886e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7896e08d6bbSMika Westerberg 7906e08d6bbSMika Westerberg return pctrl->community->functions[function].name; 7916e08d6bbSMika Westerberg } 7926e08d6bbSMika Westerberg 7936e08d6bbSMika Westerberg static int chv_get_function_groups(struct pinctrl_dev *pctldev, 7946e08d6bbSMika Westerberg unsigned function, 7956e08d6bbSMika Westerberg const char * const **groups, 7966e08d6bbSMika Westerberg unsigned * const ngroups) 7976e08d6bbSMika Westerberg { 7986e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 7996e08d6bbSMika Westerberg 8006e08d6bbSMika Westerberg *groups = pctrl->community->functions[function].groups; 8016e08d6bbSMika Westerberg *ngroups = pctrl->community->functions[function].ngroups; 8026e08d6bbSMika Westerberg return 0; 8036e08d6bbSMika Westerberg } 8046e08d6bbSMika Westerberg 8056e08d6bbSMika Westerberg static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, 8066e08d6bbSMika Westerberg unsigned group) 8076e08d6bbSMika Westerberg { 8086e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 8096e08d6bbSMika Westerberg const struct chv_pingroup *grp; 8106e08d6bbSMika Westerberg unsigned long flags; 8116e08d6bbSMika Westerberg int i; 8126e08d6bbSMika Westerberg 8136e08d6bbSMika Westerberg grp = &pctrl->community->groups[group]; 8146e08d6bbSMika Westerberg 8150bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 8166e08d6bbSMika Westerberg 8176e08d6bbSMika Westerberg /* Check first that the pad is not locked */ 8186e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 8196e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, grp->pins[i])) { 8206e08d6bbSMika Westerberg dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 8216e08d6bbSMika Westerberg grp->pins[i]); 8220bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8236e08d6bbSMika Westerberg return -EBUSY; 8246e08d6bbSMika Westerberg } 8256e08d6bbSMika Westerberg } 8266e08d6bbSMika Westerberg 8276e08d6bbSMika Westerberg for (i = 0; i < grp->npins; i++) { 8286e08d6bbSMika Westerberg const struct chv_alternate_function *altfunc = &grp->altfunc; 8296e08d6bbSMika Westerberg int pin = grp->pins[i]; 8306e08d6bbSMika Westerberg void __iomem *reg; 8316e08d6bbSMika Westerberg u32 value; 8326e08d6bbSMika Westerberg 8336e08d6bbSMika Westerberg /* Check if there is pin-specific config */ 8346e08d6bbSMika Westerberg if (grp->overrides) { 8356e08d6bbSMika Westerberg int j; 8366e08d6bbSMika Westerberg 8376e08d6bbSMika Westerberg for (j = 0; j < grp->noverrides; j++) { 8386e08d6bbSMika Westerberg if (grp->overrides[j].pin == pin) { 8396e08d6bbSMika Westerberg altfunc = &grp->overrides[j]; 8406e08d6bbSMika Westerberg break; 8416e08d6bbSMika Westerberg } 8426e08d6bbSMika Westerberg } 8436e08d6bbSMika Westerberg } 8446e08d6bbSMika Westerberg 8456e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 8466e08d6bbSMika Westerberg value = readl(reg); 8476e08d6bbSMika Westerberg /* Disable GPIO mode */ 8486e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_GPIOEN; 8496e08d6bbSMika Westerberg /* Set to desired mode */ 8506e08d6bbSMika Westerberg value &= ~CHV_PADCTRL0_PMODE_MASK; 8516e08d6bbSMika Westerberg value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; 8526e08d6bbSMika Westerberg chv_writel(value, reg); 8536e08d6bbSMika Westerberg 8546e08d6bbSMika Westerberg /* Update for invert_oe */ 8556e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 8566e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; 8576e08d6bbSMika Westerberg if (altfunc->invert_oe) 8586e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 8596e08d6bbSMika Westerberg chv_writel(value, reg); 8606e08d6bbSMika Westerberg 8616e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", 8626e08d6bbSMika Westerberg pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 8636e08d6bbSMika Westerberg } 8646e08d6bbSMika Westerberg 8650bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8666e08d6bbSMika Westerberg 8676e08d6bbSMika Westerberg return 0; 8686e08d6bbSMika Westerberg } 8696e08d6bbSMika Westerberg 8706e08d6bbSMika Westerberg static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 8716e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 8726e08d6bbSMika Westerberg unsigned offset) 8736e08d6bbSMika Westerberg { 8746e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 8756e08d6bbSMika Westerberg unsigned long flags; 8766e08d6bbSMika Westerberg void __iomem *reg; 8776e08d6bbSMika Westerberg u32 value; 8786e08d6bbSMika Westerberg 8790bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 8806e08d6bbSMika Westerberg 8816e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, offset)) { 8826e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 8836e08d6bbSMika Westerberg if (!(value & CHV_PADCTRL0_GPIOEN)) { 8846e08d6bbSMika Westerberg /* Locked so cannot enable */ 8850bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 8866e08d6bbSMika Westerberg return -EBUSY; 8876e08d6bbSMika Westerberg } 8886e08d6bbSMika Westerberg } else { 8896e08d6bbSMika Westerberg int i; 8906e08d6bbSMika Westerberg 8916e08d6bbSMika Westerberg /* Reset the interrupt mapping */ 8926e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { 8936e08d6bbSMika Westerberg if (pctrl->intr_lines[i] == offset) { 8946e08d6bbSMika Westerberg pctrl->intr_lines[i] = 0; 8956e08d6bbSMika Westerberg break; 8966e08d6bbSMika Westerberg } 8976e08d6bbSMika Westerberg } 8986e08d6bbSMika Westerberg 8996e08d6bbSMika Westerberg /* Disable interrupt generation */ 9006e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); 9016e08d6bbSMika Westerberg value = readl(reg); 9026e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 9036e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 9046e08d6bbSMika Westerberg chv_writel(value, reg); 9056e08d6bbSMika Westerberg 9066e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9072479c730SMika Westerberg value = readl(reg); 9082479c730SMika Westerberg 9092479c730SMika Westerberg /* 9102479c730SMika Westerberg * If the pin is in HiZ mode (both TX and RX buffers are 9112479c730SMika Westerberg * disabled) we turn it to be input now. 9122479c730SMika Westerberg */ 9132479c730SMika Westerberg if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 9142479c730SMika Westerberg (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 9152479c730SMika Westerberg value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 9162479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOCFG_GPI << 9172479c730SMika Westerberg CHV_PADCTRL0_GPIOCFG_SHIFT; 9182479c730SMika Westerberg } 9192479c730SMika Westerberg 9202479c730SMika Westerberg /* Switch to a GPIO mode */ 9212479c730SMika Westerberg value |= CHV_PADCTRL0_GPIOEN; 9226e08d6bbSMika Westerberg chv_writel(value, reg); 9236e08d6bbSMika Westerberg } 9246e08d6bbSMika Westerberg 9250bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9266e08d6bbSMika Westerberg 9276e08d6bbSMika Westerberg return 0; 9286e08d6bbSMika Westerberg } 9296e08d6bbSMika Westerberg 9306e08d6bbSMika Westerberg static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 9316e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9326e08d6bbSMika Westerberg unsigned offset) 9336e08d6bbSMika Westerberg { 9346e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9356e08d6bbSMika Westerberg unsigned long flags; 9366e08d6bbSMika Westerberg void __iomem *reg; 9376e08d6bbSMika Westerberg u32 value; 9386e08d6bbSMika Westerberg 9390bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9406e08d6bbSMika Westerberg 9416e08d6bbSMika Westerberg reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9426e08d6bbSMika Westerberg value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 9436e08d6bbSMika Westerberg chv_writel(value, reg); 9446e08d6bbSMika Westerberg 9450bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9466e08d6bbSMika Westerberg } 9476e08d6bbSMika Westerberg 9486e08d6bbSMika Westerberg static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 9496e08d6bbSMika Westerberg struct pinctrl_gpio_range *range, 9506e08d6bbSMika Westerberg unsigned offset, bool input) 9516e08d6bbSMika Westerberg { 9526e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9536e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 9546e08d6bbSMika Westerberg unsigned long flags; 9556e08d6bbSMika Westerberg u32 ctrl0; 9566e08d6bbSMika Westerberg 9570bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9586e08d6bbSMika Westerberg 9596e08d6bbSMika Westerberg ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 9606e08d6bbSMika Westerberg if (input) 9616e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 9626e08d6bbSMika Westerberg else 9636e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 9646e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 9656e08d6bbSMika Westerberg 9660bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9676e08d6bbSMika Westerberg 9686e08d6bbSMika Westerberg return 0; 9696e08d6bbSMika Westerberg } 9706e08d6bbSMika Westerberg 9716e08d6bbSMika Westerberg static const struct pinmux_ops chv_pinmux_ops = { 9726e08d6bbSMika Westerberg .get_functions_count = chv_get_functions_count, 9736e08d6bbSMika Westerberg .get_function_name = chv_get_function_name, 9746e08d6bbSMika Westerberg .get_function_groups = chv_get_function_groups, 9756e08d6bbSMika Westerberg .set_mux = chv_pinmux_set_mux, 9766e08d6bbSMika Westerberg .gpio_request_enable = chv_gpio_request_enable, 9776e08d6bbSMika Westerberg .gpio_disable_free = chv_gpio_disable_free, 9786e08d6bbSMika Westerberg .gpio_set_direction = chv_gpio_set_direction, 9796e08d6bbSMika Westerberg }; 9806e08d6bbSMika Westerberg 9816e08d6bbSMika Westerberg static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, 9826e08d6bbSMika Westerberg unsigned long *config) 9836e08d6bbSMika Westerberg { 9846e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 9856e08d6bbSMika Westerberg enum pin_config_param param = pinconf_to_config_param(*config); 9866e08d6bbSMika Westerberg unsigned long flags; 9876e08d6bbSMika Westerberg u32 ctrl0, ctrl1; 9886e08d6bbSMika Westerberg u16 arg = 0; 9896e08d6bbSMika Westerberg u32 term; 9906e08d6bbSMika Westerberg 9910bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 9926e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 9936e08d6bbSMika Westerberg ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 9940bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 9956e08d6bbSMika Westerberg 9966e08d6bbSMika Westerberg term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 9976e08d6bbSMika Westerberg 9986e08d6bbSMika Westerberg switch (param) { 9996e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 10006e08d6bbSMika Westerberg if (term) 10016e08d6bbSMika Westerberg return -EINVAL; 10026e08d6bbSMika Westerberg break; 10036e08d6bbSMika Westerberg 10046e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 10056e08d6bbSMika Westerberg if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 10066e08d6bbSMika Westerberg return -EINVAL; 10076e08d6bbSMika Westerberg 10086e08d6bbSMika Westerberg switch (term) { 10096e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 10106e08d6bbSMika Westerberg arg = 20000; 10116e08d6bbSMika Westerberg break; 10126e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 10136e08d6bbSMika Westerberg arg = 5000; 10146e08d6bbSMika Westerberg break; 10156e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_1K: 10166e08d6bbSMika Westerberg arg = 1000; 10176e08d6bbSMika Westerberg break; 10186e08d6bbSMika Westerberg } 10196e08d6bbSMika Westerberg 10206e08d6bbSMika Westerberg break; 10216e08d6bbSMika Westerberg 10226e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 10236e08d6bbSMika Westerberg if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 10246e08d6bbSMika Westerberg return -EINVAL; 10256e08d6bbSMika Westerberg 10266e08d6bbSMika Westerberg switch (term) { 10276e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_20K: 10286e08d6bbSMika Westerberg arg = 20000; 10296e08d6bbSMika Westerberg break; 10306e08d6bbSMika Westerberg case CHV_PADCTRL0_TERM_5K: 10316e08d6bbSMika Westerberg arg = 5000; 10326e08d6bbSMika Westerberg break; 10336e08d6bbSMika Westerberg } 10346e08d6bbSMika Westerberg 10356e08d6bbSMika Westerberg break; 10366e08d6bbSMika Westerberg 10376e08d6bbSMika Westerberg case PIN_CONFIG_DRIVE_OPEN_DRAIN: 10386e08d6bbSMika Westerberg if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 10396e08d6bbSMika Westerberg return -EINVAL; 10406e08d6bbSMika Westerberg break; 10416e08d6bbSMika Westerberg 10426e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 10436e08d6bbSMika Westerberg u32 cfg; 10446e08d6bbSMika Westerberg 10456e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 10466e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 10476e08d6bbSMika Westerberg if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 10486e08d6bbSMika Westerberg return -EINVAL; 10496e08d6bbSMika Westerberg 10506e08d6bbSMika Westerberg break; 10516e08d6bbSMika Westerberg } 10526e08d6bbSMika Westerberg 10536e08d6bbSMika Westerberg default: 10546e08d6bbSMika Westerberg return -ENOTSUPP; 10556e08d6bbSMika Westerberg } 10566e08d6bbSMika Westerberg 10576e08d6bbSMika Westerberg *config = pinconf_to_config_packed(param, arg); 10586e08d6bbSMika Westerberg return 0; 10596e08d6bbSMika Westerberg } 10606e08d6bbSMika Westerberg 10616e08d6bbSMika Westerberg static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, 10626e08d6bbSMika Westerberg enum pin_config_param param, u16 arg) 10636e08d6bbSMika Westerberg { 10646e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 10656e08d6bbSMika Westerberg unsigned long flags; 10666e08d6bbSMika Westerberg u32 ctrl0, pull; 10676e08d6bbSMika Westerberg 10680bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 10696e08d6bbSMika Westerberg ctrl0 = readl(reg); 10706e08d6bbSMika Westerberg 10716e08d6bbSMika Westerberg switch (param) { 10726e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 10736e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10746e08d6bbSMika Westerberg break; 10756e08d6bbSMika Westerberg 10766e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 10776e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 10786e08d6bbSMika Westerberg 10796e08d6bbSMika Westerberg switch (arg) { 10806e08d6bbSMika Westerberg case 1000: 10816e08d6bbSMika Westerberg /* For 1k there is only pull up */ 10826e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 10836e08d6bbSMika Westerberg break; 10846e08d6bbSMika Westerberg case 5000: 10856e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 10866e08d6bbSMika Westerberg break; 10876e08d6bbSMika Westerberg case 20000: 10886e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 10896e08d6bbSMika Westerberg break; 10906e08d6bbSMika Westerberg default: 10910bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 10926e08d6bbSMika Westerberg return -EINVAL; 10936e08d6bbSMika Westerberg } 10946e08d6bbSMika Westerberg 10956e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 10966e08d6bbSMika Westerberg break; 10976e08d6bbSMika Westerberg 10986e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 10996e08d6bbSMika Westerberg ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 11006e08d6bbSMika Westerberg 11016e08d6bbSMika Westerberg switch (arg) { 11026e08d6bbSMika Westerberg case 5000: 11036e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 11046e08d6bbSMika Westerberg break; 11056e08d6bbSMika Westerberg case 20000: 11066e08d6bbSMika Westerberg pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 11076e08d6bbSMika Westerberg break; 11086e08d6bbSMika Westerberg default: 11090bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11106e08d6bbSMika Westerberg return -EINVAL; 11116e08d6bbSMika Westerberg } 11126e08d6bbSMika Westerberg 11136e08d6bbSMika Westerberg ctrl0 |= pull; 11146e08d6bbSMika Westerberg break; 11156e08d6bbSMika Westerberg 11166e08d6bbSMika Westerberg default: 11170bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11186e08d6bbSMika Westerberg return -EINVAL; 11196e08d6bbSMika Westerberg } 11206e08d6bbSMika Westerberg 11216e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 11220bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 11236e08d6bbSMika Westerberg 11246e08d6bbSMika Westerberg return 0; 11256e08d6bbSMika Westerberg } 11266e08d6bbSMika Westerberg 1127ccdf81d0SDan O'Donovan static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, 1128ccdf81d0SDan O'Donovan bool enable) 1129ccdf81d0SDan O'Donovan { 1130ccdf81d0SDan O'Donovan void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 1131ccdf81d0SDan O'Donovan unsigned long flags; 1132ccdf81d0SDan O'Donovan u32 ctrl1; 1133ccdf81d0SDan O'Donovan 1134ccdf81d0SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1135ccdf81d0SDan O'Donovan ctrl1 = readl(reg); 1136ccdf81d0SDan O'Donovan 1137ccdf81d0SDan O'Donovan if (enable) 1138ccdf81d0SDan O'Donovan ctrl1 |= CHV_PADCTRL1_ODEN; 1139ccdf81d0SDan O'Donovan else 1140ccdf81d0SDan O'Donovan ctrl1 &= ~CHV_PADCTRL1_ODEN; 1141ccdf81d0SDan O'Donovan 1142ccdf81d0SDan O'Donovan chv_writel(ctrl1, reg); 1143ccdf81d0SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1144ccdf81d0SDan O'Donovan 1145ccdf81d0SDan O'Donovan return 0; 1146ccdf81d0SDan O'Donovan } 1147ccdf81d0SDan O'Donovan 11486e08d6bbSMika Westerberg static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, 11496e08d6bbSMika Westerberg unsigned long *configs, unsigned nconfigs) 11506e08d6bbSMika Westerberg { 11516e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 11526e08d6bbSMika Westerberg enum pin_config_param param; 11536e08d6bbSMika Westerberg int i, ret; 11546e08d6bbSMika Westerberg u16 arg; 11556e08d6bbSMika Westerberg 11566e08d6bbSMika Westerberg if (chv_pad_locked(pctrl, pin)) 11576e08d6bbSMika Westerberg return -EBUSY; 11586e08d6bbSMika Westerberg 11596e08d6bbSMika Westerberg for (i = 0; i < nconfigs; i++) { 11606e08d6bbSMika Westerberg param = pinconf_to_config_param(configs[i]); 11616e08d6bbSMika Westerberg arg = pinconf_to_config_argument(configs[i]); 11626e08d6bbSMika Westerberg 11636e08d6bbSMika Westerberg switch (param) { 11646e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_DISABLE: 11656e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_UP: 11666e08d6bbSMika Westerberg case PIN_CONFIG_BIAS_PULL_DOWN: 11676e08d6bbSMika Westerberg ret = chv_config_set_pull(pctrl, pin, param, arg); 11686e08d6bbSMika Westerberg if (ret) 11696e08d6bbSMika Westerberg return ret; 11706e08d6bbSMika Westerberg break; 11716e08d6bbSMika Westerberg 1172ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_PUSH_PULL: 1173ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, false); 1174ccdf81d0SDan O'Donovan if (ret) 1175ccdf81d0SDan O'Donovan return ret; 1176ccdf81d0SDan O'Donovan break; 1177ccdf81d0SDan O'Donovan 1178ccdf81d0SDan O'Donovan case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1179ccdf81d0SDan O'Donovan ret = chv_config_set_oden(pctrl, pin, true); 1180ccdf81d0SDan O'Donovan if (ret) 1181ccdf81d0SDan O'Donovan return ret; 1182ccdf81d0SDan O'Donovan break; 1183ccdf81d0SDan O'Donovan 11846e08d6bbSMika Westerberg default: 11856e08d6bbSMika Westerberg return -ENOTSUPP; 11866e08d6bbSMika Westerberg } 11876e08d6bbSMika Westerberg 11886e08d6bbSMika Westerberg dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, 11896e08d6bbSMika Westerberg param, arg); 11906e08d6bbSMika Westerberg } 11916e08d6bbSMika Westerberg 11926e08d6bbSMika Westerberg return 0; 11936e08d6bbSMika Westerberg } 11946e08d6bbSMika Westerberg 119577401d7fSDan O'Donovan static int chv_config_group_get(struct pinctrl_dev *pctldev, 119677401d7fSDan O'Donovan unsigned int group, 119777401d7fSDan O'Donovan unsigned long *config) 119877401d7fSDan O'Donovan { 119977401d7fSDan O'Donovan const unsigned int *pins; 120077401d7fSDan O'Donovan unsigned int npins; 120177401d7fSDan O'Donovan int ret; 120277401d7fSDan O'Donovan 120377401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 120477401d7fSDan O'Donovan if (ret) 120577401d7fSDan O'Donovan return ret; 120677401d7fSDan O'Donovan 120777401d7fSDan O'Donovan ret = chv_config_get(pctldev, pins[0], config); 120877401d7fSDan O'Donovan if (ret) 120977401d7fSDan O'Donovan return ret; 121077401d7fSDan O'Donovan 121177401d7fSDan O'Donovan return 0; 121277401d7fSDan O'Donovan } 121377401d7fSDan O'Donovan 121477401d7fSDan O'Donovan static int chv_config_group_set(struct pinctrl_dev *pctldev, 121577401d7fSDan O'Donovan unsigned int group, unsigned long *configs, 121677401d7fSDan O'Donovan unsigned int num_configs) 121777401d7fSDan O'Donovan { 121877401d7fSDan O'Donovan const unsigned int *pins; 121977401d7fSDan O'Donovan unsigned int npins; 122077401d7fSDan O'Donovan int i, ret; 122177401d7fSDan O'Donovan 122277401d7fSDan O'Donovan ret = chv_get_group_pins(pctldev, group, &pins, &npins); 122377401d7fSDan O'Donovan if (ret) 122477401d7fSDan O'Donovan return ret; 122577401d7fSDan O'Donovan 122677401d7fSDan O'Donovan for (i = 0; i < npins; i++) { 122777401d7fSDan O'Donovan ret = chv_config_set(pctldev, pins[i], configs, num_configs); 122877401d7fSDan O'Donovan if (ret) 122977401d7fSDan O'Donovan return ret; 123077401d7fSDan O'Donovan } 123177401d7fSDan O'Donovan 123277401d7fSDan O'Donovan return 0; 123377401d7fSDan O'Donovan } 123477401d7fSDan O'Donovan 12356e08d6bbSMika Westerberg static const struct pinconf_ops chv_pinconf_ops = { 12366e08d6bbSMika Westerberg .is_generic = true, 12376e08d6bbSMika Westerberg .pin_config_set = chv_config_set, 12386e08d6bbSMika Westerberg .pin_config_get = chv_config_get, 123977401d7fSDan O'Donovan .pin_config_group_get = chv_config_group_get, 124077401d7fSDan O'Donovan .pin_config_group_set = chv_config_group_set, 12416e08d6bbSMika Westerberg }; 12426e08d6bbSMika Westerberg 12436e08d6bbSMika Westerberg static struct pinctrl_desc chv_pinctrl_desc = { 12446e08d6bbSMika Westerberg .pctlops = &chv_pinctrl_ops, 12456e08d6bbSMika Westerberg .pmxops = &chv_pinmux_ops, 12466e08d6bbSMika Westerberg .confops = &chv_pinconf_ops, 12476e08d6bbSMika Westerberg .owner = THIS_MODULE, 12486e08d6bbSMika Westerberg }; 12496e08d6bbSMika Westerberg 12506e08d6bbSMika Westerberg static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, 12516e08d6bbSMika Westerberg unsigned offset) 12526e08d6bbSMika Westerberg { 12536e08d6bbSMika Westerberg return pctrl->community->pins[offset].number; 12546e08d6bbSMika Westerberg } 12556e08d6bbSMika Westerberg 12566e08d6bbSMika Westerberg static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) 12576e08d6bbSMika Westerberg { 12580587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12596e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 12604585b000SMika Westerberg unsigned long flags; 12616e08d6bbSMika Westerberg u32 ctrl0, cfg; 12626e08d6bbSMika Westerberg 12630bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12646e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 12650bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12666e08d6bbSMika Westerberg 12676e08d6bbSMika Westerberg cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 12686e08d6bbSMika Westerberg cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 12696e08d6bbSMika Westerberg 12706e08d6bbSMika Westerberg if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 12716e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 12726e08d6bbSMika Westerberg return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 12736e08d6bbSMika Westerberg } 12746e08d6bbSMika Westerberg 12756e08d6bbSMika Westerberg static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 12766e08d6bbSMika Westerberg { 12770587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 12786e08d6bbSMika Westerberg unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 12796e08d6bbSMika Westerberg unsigned long flags; 12806e08d6bbSMika Westerberg void __iomem *reg; 12816e08d6bbSMika Westerberg u32 ctrl0; 12826e08d6bbSMika Westerberg 12830bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 12846e08d6bbSMika Westerberg 12856e08d6bbSMika Westerberg reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 12866e08d6bbSMika Westerberg ctrl0 = readl(reg); 12876e08d6bbSMika Westerberg 12886e08d6bbSMika Westerberg if (value) 12896e08d6bbSMika Westerberg ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 12906e08d6bbSMika Westerberg else 12916e08d6bbSMika Westerberg ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 12926e08d6bbSMika Westerberg 12936e08d6bbSMika Westerberg chv_writel(ctrl0, reg); 12946e08d6bbSMika Westerberg 12950bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 12966e08d6bbSMika Westerberg } 12976e08d6bbSMika Westerberg 12986e08d6bbSMika Westerberg static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 12996e08d6bbSMika Westerberg { 13000587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(chip); 13016e08d6bbSMika Westerberg unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 13026e08d6bbSMika Westerberg u32 ctrl0, direction; 13034585b000SMika Westerberg unsigned long flags; 13046e08d6bbSMika Westerberg 13050bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 13066e08d6bbSMika Westerberg ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13070bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 13086e08d6bbSMika Westerberg 13096e08d6bbSMika Westerberg direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 13106e08d6bbSMika Westerberg direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 13116e08d6bbSMika Westerberg 13126e08d6bbSMika Westerberg return direction != CHV_PADCTRL0_GPIOCFG_GPO; 13136e08d6bbSMika Westerberg } 13146e08d6bbSMika Westerberg 13156e08d6bbSMika Westerberg static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 13166e08d6bbSMika Westerberg { 13176e08d6bbSMika Westerberg return pinctrl_gpio_direction_input(chip->base + offset); 13186e08d6bbSMika Westerberg } 13196e08d6bbSMika Westerberg 13206e08d6bbSMika Westerberg static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 13216e08d6bbSMika Westerberg int value) 13226e08d6bbSMika Westerberg { 1323549e783fSqipeng.zha chv_gpio_set(chip, offset, value); 13246e08d6bbSMika Westerberg return pinctrl_gpio_direction_output(chip->base + offset); 13256e08d6bbSMika Westerberg } 13266e08d6bbSMika Westerberg 13276e08d6bbSMika Westerberg static const struct gpio_chip chv_gpio_chip = { 13286e08d6bbSMika Westerberg .owner = THIS_MODULE, 132998c85d58SJonas Gorski .request = gpiochip_generic_request, 133098c85d58SJonas Gorski .free = gpiochip_generic_free, 13316e08d6bbSMika Westerberg .get_direction = chv_gpio_get_direction, 13326e08d6bbSMika Westerberg .direction_input = chv_gpio_direction_input, 13336e08d6bbSMika Westerberg .direction_output = chv_gpio_direction_output, 13346e08d6bbSMika Westerberg .get = chv_gpio_get, 13356e08d6bbSMika Westerberg .set = chv_gpio_set, 13366e08d6bbSMika Westerberg }; 13376e08d6bbSMika Westerberg 13386e08d6bbSMika Westerberg static void chv_gpio_irq_ack(struct irq_data *d) 13396e08d6bbSMika Westerberg { 13406e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13410587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 13426e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 13436e08d6bbSMika Westerberg u32 intr_line; 13446e08d6bbSMika Westerberg 13450bd50d71SDan O'Donovan raw_spin_lock(&chv_lock); 13466e08d6bbSMika Westerberg 13476e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13486e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13496e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13506e08d6bbSMika Westerberg chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 13516e08d6bbSMika Westerberg 13520bd50d71SDan O'Donovan raw_spin_unlock(&chv_lock); 13536e08d6bbSMika Westerberg } 13546e08d6bbSMika Westerberg 13556e08d6bbSMika Westerberg static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 13566e08d6bbSMika Westerberg { 13576e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 13580587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 13596e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 13606e08d6bbSMika Westerberg u32 value, intr_line; 13616e08d6bbSMika Westerberg unsigned long flags; 13626e08d6bbSMika Westerberg 13630bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 13646e08d6bbSMika Westerberg 13656e08d6bbSMika Westerberg intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 13666e08d6bbSMika Westerberg intr_line &= CHV_PADCTRL0_INTSEL_MASK; 13676e08d6bbSMika Westerberg intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 13686e08d6bbSMika Westerberg 13696e08d6bbSMika Westerberg value = readl(pctrl->regs + CHV_INTMASK); 13706e08d6bbSMika Westerberg if (mask) 13716e08d6bbSMika Westerberg value &= ~BIT(intr_line); 13726e08d6bbSMika Westerberg else 13736e08d6bbSMika Westerberg value |= BIT(intr_line); 13746e08d6bbSMika Westerberg chv_writel(value, pctrl->regs + CHV_INTMASK); 13756e08d6bbSMika Westerberg 13760bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 13776e08d6bbSMika Westerberg } 13786e08d6bbSMika Westerberg 13796e08d6bbSMika Westerberg static void chv_gpio_irq_mask(struct irq_data *d) 13806e08d6bbSMika Westerberg { 13816e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, true); 13826e08d6bbSMika Westerberg } 13836e08d6bbSMika Westerberg 13846e08d6bbSMika Westerberg static void chv_gpio_irq_unmask(struct irq_data *d) 13856e08d6bbSMika Westerberg { 13866e08d6bbSMika Westerberg chv_gpio_irq_mask_unmask(d, false); 13876e08d6bbSMika Westerberg } 13886e08d6bbSMika Westerberg 1389e6c906deSMika Westerberg static unsigned chv_gpio_irq_startup(struct irq_data *d) 1390e6c906deSMika Westerberg { 1391e6c906deSMika Westerberg /* 1392e6c906deSMika Westerberg * Check if the interrupt has been requested with 0 as triggering 1393e6c906deSMika Westerberg * type. In that case it is assumed that the current values 1394e6c906deSMika Westerberg * programmed to the hardware are used (e.g BIOS configured 1395e6c906deSMika Westerberg * defaults). 1396e6c906deSMika Westerberg * 1397e6c906deSMika Westerberg * In that case ->irq_set_type() will never be called so we need to 1398e6c906deSMika Westerberg * read back the values from hardware now, set correct flow handler 1399e6c906deSMika Westerberg * and update mappings before the interrupt is being used. 1400e6c906deSMika Westerberg */ 1401e6c906deSMika Westerberg if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { 1402e6c906deSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 14030587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1404e6c906deSMika Westerberg unsigned offset = irqd_to_hwirq(d); 1405e6c906deSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 1406e6c906deSMika Westerberg irq_flow_handler_t handler; 1407e6c906deSMika Westerberg unsigned long flags; 1408e6c906deSMika Westerberg u32 intsel, value; 1409e6c906deSMika Westerberg 14100bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 1411e6c906deSMika Westerberg intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1412e6c906deSMika Westerberg intsel &= CHV_PADCTRL0_INTSEL_MASK; 1413e6c906deSMika Westerberg intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1414e6c906deSMika Westerberg 1415e6c906deSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 1416e6c906deSMika Westerberg if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1417e6c906deSMika Westerberg handler = handle_level_irq; 1418e6c906deSMika Westerberg else 1419e6c906deSMika Westerberg handler = handle_edge_irq; 1420e6c906deSMika Westerberg 1421e6c906deSMika Westerberg if (!pctrl->intr_lines[intsel]) { 1422a4e3f783SThomas Gleixner irq_set_handler_locked(d, handler); 1423e6c906deSMika Westerberg pctrl->intr_lines[intsel] = offset; 1424e6c906deSMika Westerberg } 14250bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 1426e6c906deSMika Westerberg } 1427e6c906deSMika Westerberg 1428e6c906deSMika Westerberg chv_gpio_irq_unmask(d); 1429e6c906deSMika Westerberg return 0; 1430e6c906deSMika Westerberg } 1431e6c906deSMika Westerberg 14326e08d6bbSMika Westerberg static int chv_gpio_irq_type(struct irq_data *d, unsigned type) 14336e08d6bbSMika Westerberg { 14346e08d6bbSMika Westerberg struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 14350587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 14366e08d6bbSMika Westerberg unsigned offset = irqd_to_hwirq(d); 14376e08d6bbSMika Westerberg int pin = chv_gpio_offset_to_pin(pctrl, offset); 14386e08d6bbSMika Westerberg unsigned long flags; 14396e08d6bbSMika Westerberg u32 value; 14406e08d6bbSMika Westerberg 14410bd50d71SDan O'Donovan raw_spin_lock_irqsave(&chv_lock, flags); 14426e08d6bbSMika Westerberg 14436e08d6bbSMika Westerberg /* 14446e08d6bbSMika Westerberg * Pins which can be used as shared interrupt are configured in 14456e08d6bbSMika Westerberg * BIOS. Driver trusts BIOS configurations and assigns different 14466e08d6bbSMika Westerberg * handler according to the irq type. 14476e08d6bbSMika Westerberg * 14486e08d6bbSMika Westerberg * Driver needs to save the mapping between each pin and 14496e08d6bbSMika Westerberg * its interrupt line. 14506e08d6bbSMika Westerberg * 1. If the pin cfg is locked in BIOS: 14516e08d6bbSMika Westerberg * Trust BIOS has programmed IntWakeCfg bits correctly, 14526e08d6bbSMika Westerberg * driver just needs to save the mapping. 14536e08d6bbSMika Westerberg * 2. If the pin cfg is not locked in BIOS: 14546e08d6bbSMika Westerberg * Driver programs the IntWakeCfg bits and save the mapping. 14556e08d6bbSMika Westerberg */ 14566e08d6bbSMika Westerberg if (!chv_pad_locked(pctrl, pin)) { 14576e08d6bbSMika Westerberg void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); 14586e08d6bbSMika Westerberg 14596e08d6bbSMika Westerberg value = readl(reg); 14606e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 14616e08d6bbSMika Westerberg value &= ~CHV_PADCTRL1_INVRXTX_MASK; 14626e08d6bbSMika Westerberg 14636e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) { 14646e08d6bbSMika Westerberg if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 14656e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 14666e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_RISING) 14676e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_RISING; 14686e08d6bbSMika Westerberg else if (type & IRQ_TYPE_EDGE_FALLING) 14696e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 14706e08d6bbSMika Westerberg } else if (type & IRQ_TYPE_LEVEL_MASK) { 14716e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 14726e08d6bbSMika Westerberg if (type & IRQ_TYPE_LEVEL_LOW) 14736e08d6bbSMika Westerberg value |= CHV_PADCTRL1_INVRXTX_RXDATA; 14746e08d6bbSMika Westerberg } 14756e08d6bbSMika Westerberg 14766e08d6bbSMika Westerberg chv_writel(value, reg); 14776e08d6bbSMika Westerberg } 14786e08d6bbSMika Westerberg 14796e08d6bbSMika Westerberg value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 14806e08d6bbSMika Westerberg value &= CHV_PADCTRL0_INTSEL_MASK; 14816e08d6bbSMika Westerberg value >>= CHV_PADCTRL0_INTSEL_SHIFT; 14826e08d6bbSMika Westerberg 14836e08d6bbSMika Westerberg pctrl->intr_lines[value] = offset; 14846e08d6bbSMika Westerberg 14856e08d6bbSMika Westerberg if (type & IRQ_TYPE_EDGE_BOTH) 1486a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_edge_irq); 14876e08d6bbSMika Westerberg else if (type & IRQ_TYPE_LEVEL_MASK) 1488a4e3f783SThomas Gleixner irq_set_handler_locked(d, handle_level_irq); 14896e08d6bbSMika Westerberg 14900bd50d71SDan O'Donovan raw_spin_unlock_irqrestore(&chv_lock, flags); 14916e08d6bbSMika Westerberg 14926e08d6bbSMika Westerberg return 0; 14936e08d6bbSMika Westerberg } 14946e08d6bbSMika Westerberg 14956e08d6bbSMika Westerberg static struct irq_chip chv_gpio_irqchip = { 14966e08d6bbSMika Westerberg .name = "chv-gpio", 1497e6c906deSMika Westerberg .irq_startup = chv_gpio_irq_startup, 14986e08d6bbSMika Westerberg .irq_ack = chv_gpio_irq_ack, 14996e08d6bbSMika Westerberg .irq_mask = chv_gpio_irq_mask, 15006e08d6bbSMika Westerberg .irq_unmask = chv_gpio_irq_unmask, 15016e08d6bbSMika Westerberg .irq_set_type = chv_gpio_irq_type, 15026e08d6bbSMika Westerberg .flags = IRQCHIP_SKIP_SET_WAKE, 15036e08d6bbSMika Westerberg }; 15046e08d6bbSMika Westerberg 1505bd0b9ac4SThomas Gleixner static void chv_gpio_irq_handler(struct irq_desc *desc) 15066e08d6bbSMika Westerberg { 15076e08d6bbSMika Westerberg struct gpio_chip *gc = irq_desc_get_handler_data(desc); 15080587d3dbSLinus Walleij struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 15095663bb27SJiang Liu struct irq_chip *chip = irq_desc_get_chip(desc); 15106e08d6bbSMika Westerberg unsigned long pending; 15116e08d6bbSMika Westerberg u32 intr_line; 15126e08d6bbSMika Westerberg 15136e08d6bbSMika Westerberg chained_irq_enter(chip, desc); 15146e08d6bbSMika Westerberg 15156e08d6bbSMika Westerberg pending = readl(pctrl->regs + CHV_INTSTAT); 151647c950d1SMika Westerberg for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { 15176e08d6bbSMika Westerberg unsigned irq, offset; 15186e08d6bbSMika Westerberg 15196e08d6bbSMika Westerberg offset = pctrl->intr_lines[intr_line]; 15206e08d6bbSMika Westerberg irq = irq_find_mapping(gc->irqdomain, offset); 15216e08d6bbSMika Westerberg generic_handle_irq(irq); 15226e08d6bbSMika Westerberg } 15236e08d6bbSMika Westerberg 15246e08d6bbSMika Westerberg chained_irq_exit(chip, desc); 15256e08d6bbSMika Westerberg } 15266e08d6bbSMika Westerberg 15276e08d6bbSMika Westerberg static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 15286e08d6bbSMika Westerberg { 15296e08d6bbSMika Westerberg const struct chv_gpio_pinrange *range; 15306e08d6bbSMika Westerberg struct gpio_chip *chip = &pctrl->chip; 15316e08d6bbSMika Westerberg int ret, i, offset; 15326e08d6bbSMika Westerberg 15336e08d6bbSMika Westerberg *chip = chv_gpio_chip; 15346e08d6bbSMika Westerberg 15356e08d6bbSMika Westerberg chip->ngpio = pctrl->community->ngpios; 15366e08d6bbSMika Westerberg chip->label = dev_name(pctrl->dev); 153758383c78SLinus Walleij chip->parent = pctrl->dev; 15386e08d6bbSMika Westerberg chip->base = -1; 153947c950d1SMika Westerberg chip->irq_need_valid_mask = true; 15406e08d6bbSMika Westerberg 15410587d3dbSLinus Walleij ret = gpiochip_add_data(chip, pctrl); 15426e08d6bbSMika Westerberg if (ret) { 15436e08d6bbSMika Westerberg dev_err(pctrl->dev, "Failed to register gpiochip\n"); 15446e08d6bbSMika Westerberg return ret; 15456e08d6bbSMika Westerberg } 15466e08d6bbSMika Westerberg 15476e08d6bbSMika Westerberg for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { 15486e08d6bbSMika Westerberg range = &pctrl->community->gpio_ranges[i]; 15496e08d6bbSMika Westerberg ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, 15506e08d6bbSMika Westerberg range->base, range->npins); 15516e08d6bbSMika Westerberg if (ret) { 15526e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 15536e08d6bbSMika Westerberg goto fail; 15546e08d6bbSMika Westerberg } 15556e08d6bbSMika Westerberg 15566e08d6bbSMika Westerberg offset += range->npins; 15576e08d6bbSMika Westerberg } 15586e08d6bbSMika Westerberg 155947c950d1SMika Westerberg /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 156047c950d1SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 156147c950d1SMika Westerberg const struct pinctrl_pin_desc *desc; 156247c950d1SMika Westerberg u32 intsel; 156347c950d1SMika Westerberg 156447c950d1SMika Westerberg desc = &pctrl->community->pins[i]; 156547c950d1SMika Westerberg 156647c950d1SMika Westerberg intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); 156747c950d1SMika Westerberg intsel &= CHV_PADCTRL0_INTSEL_MASK; 156847c950d1SMika Westerberg intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 156947c950d1SMika Westerberg 157047c950d1SMika Westerberg if (intsel >= pctrl->community->nirqs) 157147c950d1SMika Westerberg clear_bit(i, chip->irq_valid_mask); 157247c950d1SMika Westerberg } 157347c950d1SMika Westerberg 1574bcb48ccaSMika Westerberg /* Clear all interrupts */ 15756e08d6bbSMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 15766e08d6bbSMika Westerberg 15776e08d6bbSMika Westerberg ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, 1578bcb48ccaSMika Westerberg handle_bad_irq, IRQ_TYPE_NONE); 15796e08d6bbSMika Westerberg if (ret) { 15806e08d6bbSMika Westerberg dev_err(pctrl->dev, "failed to add IRQ chip\n"); 15816e08d6bbSMika Westerberg goto fail; 15826e08d6bbSMika Westerberg } 15836e08d6bbSMika Westerberg 15846e08d6bbSMika Westerberg gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, 15856e08d6bbSMika Westerberg chv_gpio_irq_handler); 15866e08d6bbSMika Westerberg return 0; 15876e08d6bbSMika Westerberg 15886e08d6bbSMika Westerberg fail: 15896e08d6bbSMika Westerberg gpiochip_remove(chip); 15906e08d6bbSMika Westerberg 15916e08d6bbSMika Westerberg return ret; 15926e08d6bbSMika Westerberg } 15936e08d6bbSMika Westerberg 15946e08d6bbSMika Westerberg static int chv_pinctrl_probe(struct platform_device *pdev) 15956e08d6bbSMika Westerberg { 15966e08d6bbSMika Westerberg struct chv_pinctrl *pctrl; 15976e08d6bbSMika Westerberg struct acpi_device *adev; 15986e08d6bbSMika Westerberg struct resource *res; 15996e08d6bbSMika Westerberg int ret, irq, i; 16006e08d6bbSMika Westerberg 16016e08d6bbSMika Westerberg adev = ACPI_COMPANION(&pdev->dev); 16026e08d6bbSMika Westerberg if (!adev) 16036e08d6bbSMika Westerberg return -ENODEV; 16046e08d6bbSMika Westerberg 16056e08d6bbSMika Westerberg pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 16066e08d6bbSMika Westerberg if (!pctrl) 16076e08d6bbSMika Westerberg return -ENOMEM; 16086e08d6bbSMika Westerberg 16096e08d6bbSMika Westerberg for (i = 0; i < ARRAY_SIZE(chv_communities); i++) 16106e08d6bbSMika Westerberg if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { 16116e08d6bbSMika Westerberg pctrl->community = chv_communities[i]; 16126e08d6bbSMika Westerberg break; 16136e08d6bbSMika Westerberg } 16146e08d6bbSMika Westerberg if (i == ARRAY_SIZE(chv_communities)) 16156e08d6bbSMika Westerberg return -ENODEV; 16166e08d6bbSMika Westerberg 16176e08d6bbSMika Westerberg pctrl->dev = &pdev->dev; 16186e08d6bbSMika Westerberg 16199eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 16209eb457b5SMika Westerberg pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, 16219eb457b5SMika Westerberg pctrl->community->npins, sizeof(*pctrl->saved_pin_context), 16229eb457b5SMika Westerberg GFP_KERNEL); 16239eb457b5SMika Westerberg if (!pctrl->saved_pin_context) 16249eb457b5SMika Westerberg return -ENOMEM; 16259eb457b5SMika Westerberg #endif 16269eb457b5SMika Westerberg 16276e08d6bbSMika Westerberg res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 16286e08d6bbSMika Westerberg pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 16296e08d6bbSMika Westerberg if (IS_ERR(pctrl->regs)) 16306e08d6bbSMika Westerberg return PTR_ERR(pctrl->regs); 16316e08d6bbSMika Westerberg 16326e08d6bbSMika Westerberg irq = platform_get_irq(pdev, 0); 16336e08d6bbSMika Westerberg if (irq < 0) { 16346e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to get interrupt number\n"); 16356e08d6bbSMika Westerberg return irq; 16366e08d6bbSMika Westerberg } 16376e08d6bbSMika Westerberg 16386e08d6bbSMika Westerberg pctrl->pctldesc = chv_pinctrl_desc; 16396e08d6bbSMika Westerberg pctrl->pctldesc.name = dev_name(&pdev->dev); 16406e08d6bbSMika Westerberg pctrl->pctldesc.pins = pctrl->community->pins; 16416e08d6bbSMika Westerberg pctrl->pctldesc.npins = pctrl->community->npins; 16426e08d6bbSMika Westerberg 16437cf061faSLaxman Dewangan pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, 16447cf061faSLaxman Dewangan pctrl); 1645323de9efSMasahiro Yamada if (IS_ERR(pctrl->pctldev)) { 16466e08d6bbSMika Westerberg dev_err(&pdev->dev, "failed to register pinctrl driver\n"); 1647323de9efSMasahiro Yamada return PTR_ERR(pctrl->pctldev); 16486e08d6bbSMika Westerberg } 16496e08d6bbSMika Westerberg 16506e08d6bbSMika Westerberg ret = chv_gpio_probe(pctrl, irq); 16517cf061faSLaxman Dewangan if (ret) 16526e08d6bbSMika Westerberg return ret; 16536e08d6bbSMika Westerberg 16546e08d6bbSMika Westerberg platform_set_drvdata(pdev, pctrl); 16556e08d6bbSMika Westerberg 16566e08d6bbSMika Westerberg return 0; 16576e08d6bbSMika Westerberg } 16586e08d6bbSMika Westerberg 16596e08d6bbSMika Westerberg static int chv_pinctrl_remove(struct platform_device *pdev) 16606e08d6bbSMika Westerberg { 16616e08d6bbSMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 16626e08d6bbSMika Westerberg 16636e08d6bbSMika Westerberg gpiochip_remove(&pctrl->chip); 16646e08d6bbSMika Westerberg 16656e08d6bbSMika Westerberg return 0; 16666e08d6bbSMika Westerberg } 16676e08d6bbSMika Westerberg 16689eb457b5SMika Westerberg #ifdef CONFIG_PM_SLEEP 16699eb457b5SMika Westerberg static int chv_pinctrl_suspend(struct device *dev) 16709eb457b5SMika Westerberg { 16719eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 16729eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 16739eb457b5SMika Westerberg int i; 16749eb457b5SMika Westerberg 16759eb457b5SMika Westerberg pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); 16769eb457b5SMika Westerberg 16779eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 16789eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 16799eb457b5SMika Westerberg struct chv_pin_context *ctx; 16809eb457b5SMika Westerberg void __iomem *reg; 16819eb457b5SMika Westerberg 16829eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 16839eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 16849eb457b5SMika Westerberg continue; 16859eb457b5SMika Westerberg 16869eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 16879eb457b5SMika Westerberg 16889eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 16899eb457b5SMika Westerberg ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 16909eb457b5SMika Westerberg 16919eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 16929eb457b5SMika Westerberg ctx->padctrl1 = readl(reg); 16939eb457b5SMika Westerberg } 16949eb457b5SMika Westerberg 16959eb457b5SMika Westerberg return 0; 16969eb457b5SMika Westerberg } 16979eb457b5SMika Westerberg 16989eb457b5SMika Westerberg static int chv_pinctrl_resume(struct device *dev) 16999eb457b5SMika Westerberg { 17009eb457b5SMika Westerberg struct platform_device *pdev = to_platform_device(dev); 17019eb457b5SMika Westerberg struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); 17029eb457b5SMika Westerberg int i; 17039eb457b5SMika Westerberg 17049eb457b5SMika Westerberg /* 17059eb457b5SMika Westerberg * Mask all interrupts before restoring per-pin configuration 17069eb457b5SMika Westerberg * registers because we don't know in which state BIOS left them 17079eb457b5SMika Westerberg * upon exiting suspend. 17089eb457b5SMika Westerberg */ 17099eb457b5SMika Westerberg chv_writel(0, pctrl->regs + CHV_INTMASK); 17109eb457b5SMika Westerberg 17119eb457b5SMika Westerberg for (i = 0; i < pctrl->community->npins; i++) { 17129eb457b5SMika Westerberg const struct pinctrl_pin_desc *desc; 17139eb457b5SMika Westerberg const struct chv_pin_context *ctx; 17149eb457b5SMika Westerberg void __iomem *reg; 17159eb457b5SMika Westerberg u32 val; 17169eb457b5SMika Westerberg 17179eb457b5SMika Westerberg desc = &pctrl->community->pins[i]; 17189eb457b5SMika Westerberg if (chv_pad_locked(pctrl, desc->number)) 17199eb457b5SMika Westerberg continue; 17209eb457b5SMika Westerberg 17219eb457b5SMika Westerberg ctx = &pctrl->saved_pin_context[i]; 17229eb457b5SMika Westerberg 17239eb457b5SMika Westerberg /* Only restore if our saved state differs from the current */ 17249eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); 17259eb457b5SMika Westerberg val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; 17269eb457b5SMika Westerberg if (ctx->padctrl0 != val) { 17279eb457b5SMika Westerberg chv_writel(ctx->padctrl0, reg); 17289eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", 17299eb457b5SMika Westerberg desc->number, readl(reg)); 17309eb457b5SMika Westerberg } 17319eb457b5SMika Westerberg 17329eb457b5SMika Westerberg reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); 17339eb457b5SMika Westerberg val = readl(reg); 17349eb457b5SMika Westerberg if (ctx->padctrl1 != val) { 17359eb457b5SMika Westerberg chv_writel(ctx->padctrl1, reg); 17369eb457b5SMika Westerberg dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", 17379eb457b5SMika Westerberg desc->number, readl(reg)); 17389eb457b5SMika Westerberg } 17399eb457b5SMika Westerberg } 17409eb457b5SMika Westerberg 17419eb457b5SMika Westerberg /* 17429eb457b5SMika Westerberg * Now that all pins are restored to known state, we can restore 17439eb457b5SMika Westerberg * the interrupt mask register as well. 17449eb457b5SMika Westerberg */ 17459eb457b5SMika Westerberg chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); 17469eb457b5SMika Westerberg chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); 17479eb457b5SMika Westerberg 17489eb457b5SMika Westerberg return 0; 17499eb457b5SMika Westerberg } 17509eb457b5SMika Westerberg #endif 17519eb457b5SMika Westerberg 17529eb457b5SMika Westerberg static const struct dev_pm_ops chv_pinctrl_pm_ops = { 17539eb457b5SMika Westerberg SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) 17549eb457b5SMika Westerberg }; 17559eb457b5SMika Westerberg 17566e08d6bbSMika Westerberg static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 17576e08d6bbSMika Westerberg { "INT33FF" }, 17586e08d6bbSMika Westerberg { } 17596e08d6bbSMika Westerberg }; 17606e08d6bbSMika Westerberg MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 17616e08d6bbSMika Westerberg 17626e08d6bbSMika Westerberg static struct platform_driver chv_pinctrl_driver = { 17636e08d6bbSMika Westerberg .probe = chv_pinctrl_probe, 17646e08d6bbSMika Westerberg .remove = chv_pinctrl_remove, 17656e08d6bbSMika Westerberg .driver = { 17666e08d6bbSMika Westerberg .name = "cherryview-pinctrl", 17679eb457b5SMika Westerberg .pm = &chv_pinctrl_pm_ops, 17686e08d6bbSMika Westerberg .acpi_match_table = chv_pinctrl_acpi_match, 17696e08d6bbSMika Westerberg }, 17706e08d6bbSMika Westerberg }; 17716e08d6bbSMika Westerberg 17726e08d6bbSMika Westerberg static int __init chv_pinctrl_init(void) 17736e08d6bbSMika Westerberg { 17746e08d6bbSMika Westerberg return platform_driver_register(&chv_pinctrl_driver); 17756e08d6bbSMika Westerberg } 17766e08d6bbSMika Westerberg subsys_initcall(chv_pinctrl_init); 17776e08d6bbSMika Westerberg 17786e08d6bbSMika Westerberg static void __exit chv_pinctrl_exit(void) 17796e08d6bbSMika Westerberg { 17806e08d6bbSMika Westerberg platform_driver_unregister(&chv_pinctrl_driver); 17816e08d6bbSMika Westerberg } 17826e08d6bbSMika Westerberg module_exit(chv_pinctrl_exit); 17836e08d6bbSMika Westerberg 17846e08d6bbSMika Westerberg MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 17856e08d6bbSMika Westerberg MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 17866e08d6bbSMika Westerberg MODULE_LICENSE("GPL v2"); 1787