xref: /openbmc/linux/drivers/pinctrl/intel/Kconfig (revision bc5aa3a0)
1#
2# Intel pin control drivers
3#
4
5config PINCTRL_BAYTRAIL
6	bool "Intel Baytrail GPIO pin control"
7	depends on GPIOLIB && ACPI
8	select GPIOLIB_IRQCHIP
9	select PINMUX
10	select PINCONF
11	select GENERIC_PINCONF
12	help
13	  driver for memory mapped GPIO functionality on Intel Baytrail
14	  platforms. Supports 3 banks with 102, 28 and 44 gpios.
15	  Most pins are usually muxed to some other functionality by firmware,
16	  so only a small amount is available for gpio use.
17
18	  Requires ACPI device enumeration code to set up a platform device.
19
20config PINCTRL_CHERRYVIEW
21	tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
22	depends on ACPI
23	select PINMUX
24	select PINCONF
25	select GENERIC_PINCONF
26	select GPIOLIB
27	select GPIOLIB_IRQCHIP
28	help
29	  Cherryview/Braswell pinctrl driver provides an interface that
30	  allows configuring of SoC pins and using them as GPIOs.
31
32config PINCTRL_MERRIFIELD
33	tristate "Intel Merrifield pinctrl driver"
34	depends on X86_INTEL_MID
35	select PINMUX
36	select PINCONF
37	select GENERIC_PINCONF
38	help
39	  Merrifield Family-Level Interface Shim (FLIS) driver provides an
40	  interface that allows configuring of SoC pins and using them as
41	  GPIOs.
42
43config PINCTRL_INTEL
44	tristate
45	select PINMUX
46	select PINCONF
47	select GENERIC_PINCONF
48	select GPIOLIB
49	select GPIOLIB_IRQCHIP
50
51config PINCTRL_BROXTON
52	tristate "Intel Broxton pinctrl and GPIO driver"
53	depends on ACPI
54	select PINCTRL_INTEL
55	help
56	  Broxton pinctrl driver provides an interface that allows
57	  configuring of SoC pins and using them as GPIOs.
58
59config PINCTRL_SUNRISEPOINT
60	tristate "Intel Sunrisepoint pinctrl and GPIO driver"
61	depends on ACPI
62	select PINCTRL_INTEL
63	help
64	  Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
65	  provides an interface that allows configuring of PCH pins and
66	  using them as GPIOs.
67