1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2021 NXP 4 */ 5 6 #include <linux/err.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/pinctrl/pinctrl.h> 13 14 #include "pinctrl-imx.h" 15 16 enum imx93_pads { 17 IMX93_IOMUXC_DAP_TDI = 0, 18 IMX93_IOMUXC_DAP_TMS_SWDIO = 1, 19 IMX93_IOMUXC_DAP_TCLK_SWCLK = 2, 20 IMX93_IOMUXC_DAP_TDO_TRACESWO = 3, 21 IMX93_IOMUXC_GPIO_IO00 = 4, 22 IMX93_IOMUXC_GPIO_IO01 = 5, 23 IMX93_IOMUXC_GPIO_IO02 = 6, 24 IMX93_IOMUXC_GPIO_IO03 = 7, 25 IMX93_IOMUXC_GPIO_IO04 = 8, 26 IMX93_IOMUXC_GPIO_IO05 = 9, 27 IMX93_IOMUXC_GPIO_IO06 = 10, 28 IMX93_IOMUXC_GPIO_IO07 = 11, 29 IMX93_IOMUXC_GPIO_IO08 = 12, 30 IMX93_IOMUXC_GPIO_IO09 = 13, 31 IMX93_IOMUXC_GPIO_IO10 = 14, 32 IMX93_IOMUXC_GPIO_IO11 = 15, 33 IMX93_IOMUXC_GPIO_IO12 = 16, 34 IMX93_IOMUXC_GPIO_IO13 = 17, 35 IMX93_IOMUXC_GPIO_IO14 = 18, 36 IMX93_IOMUXC_GPIO_IO15 = 19, 37 IMX93_IOMUXC_GPIO_IO16 = 20, 38 IMX93_IOMUXC_GPIO_IO17 = 21, 39 IMX93_IOMUXC_GPIO_IO18 = 22, 40 IMX93_IOMUXC_GPIO_IO19 = 23, 41 IMX93_IOMUXC_GPIO_IO20 = 24, 42 IMX93_IOMUXC_GPIO_IO21 = 25, 43 IMX93_IOMUXC_GPIO_IO22 = 26, 44 IMX93_IOMUXC_GPIO_IO23 = 27, 45 IMX93_IOMUXC_GPIO_IO24 = 28, 46 IMX93_IOMUXC_GPIO_IO25 = 29, 47 IMX93_IOMUXC_GPIO_IO26 = 30, 48 IMX93_IOMUXC_GPIO_IO27 = 31, 49 IMX93_IOMUXC_GPIO_IO28 = 32, 50 IMX93_IOMUXC_GPIO_IO29 = 33, 51 IMX93_IOMUXC_CCM_CLKO1 = 34, 52 IMX93_IOMUXC_CCM_CLKO2 = 35, 53 IMX93_IOMUXC_CCM_CLKO3 = 36, 54 IMX93_IOMUXC_CCM_CLKO4 = 37, 55 IMX93_IOMUXC_ENET1_MDC = 38, 56 IMX93_IOMUXC_ENET1_MDIO = 39, 57 IMX93_IOMUXC_ENET1_TD3 = 40, 58 IMX93_IOMUXC_ENET1_TD2 = 41, 59 IMX93_IOMUXC_ENET1_TD1 = 42, 60 IMX93_IOMUXC_ENET1_TD0 = 43, 61 IMX93_IOMUXC_ENET1_TX_CTL = 44, 62 IMX93_IOMUXC_ENET1_TXC = 45, 63 IMX93_IOMUXC_ENET1_RX_CTL = 46, 64 IMX93_IOMUXC_ENET1_RXC = 47, 65 IMX93_IOMUXC_ENET1_RD0 = 48, 66 IMX93_IOMUXC_ENET1_RD1 = 49, 67 IMX93_IOMUXC_ENET1_RD2 = 50, 68 IMX93_IOMUXC_ENET1_RD3 = 51, 69 IMX93_IOMUXC_ENET2_MDC = 52, 70 IMX93_IOMUXC_ENET2_MDIO = 53, 71 IMX93_IOMUXC_ENET2_TD3 = 54, 72 IMX93_IOMUXC_ENET2_TD2 = 55, 73 IMX93_IOMUXC_ENET2_TD1 = 56, 74 IMX93_IOMUXC_ENET2_TD0 = 57, 75 IMX93_IOMUXC_ENET2_TX_CTL = 58, 76 IMX93_IOMUXC_ENET2_TXC = 59, 77 IMX93_IOMUXC_ENET2_RX_CTL = 60, 78 IMX93_IOMUXC_ENET2_RXC = 61, 79 IMX93_IOMUXC_ENET2_RD0 = 62, 80 IMX93_IOMUXC_ENET2_RD1 = 63, 81 IMX93_IOMUXC_ENET2_RD2 = 64, 82 IMX93_IOMUXC_ENET2_RD3 = 65, 83 IMX93_IOMUXC_SD1_CLK = 66, 84 IMX93_IOMUXC_SD1_CMD = 67, 85 IMX93_IOMUXC_SD1_DATA0 = 68, 86 IMX93_IOMUXC_SD1_DATA1 = 69, 87 IMX93_IOMUXC_SD1_DATA2 = 70, 88 IMX93_IOMUXC_SD1_DATA3 = 71, 89 IMX93_IOMUXC_SD1_DATA4 = 72, 90 IMX93_IOMUXC_SD1_DATA5 = 73, 91 IMX93_IOMUXC_SD1_DATA6 = 74, 92 IMX93_IOMUXC_SD1_DATA7 = 75, 93 IMX93_IOMUXC_SD1_STROBE = 76, 94 IMX93_IOMUXC_SD2_VSELECT = 77, 95 IMX93_IOMUXC_SD3_CLK = 78, 96 IMX93_IOMUXC_SD3_CMD = 79, 97 IMX93_IOMUXC_SD3_DATA0 = 80, 98 IMX93_IOMUXC_SD3_DATA1 = 81, 99 IMX93_IOMUXC_SD3_DATA2 = 82, 100 IMX93_IOMUXC_SD3_DATA3 = 83, 101 IMX93_IOMUXC_SD2_CD_B = 84, 102 IMX93_IOMUXC_SD2_CLK = 85, 103 IMX93_IOMUXC_SD2_CMD = 86, 104 IMX93_IOMUXC_SD2_DATA0 = 87, 105 IMX93_IOMUXC_SD2_DATA1 = 88, 106 IMX93_IOMUXC_SD2_DATA2 = 89, 107 IMX93_IOMUXC_SD2_DATA3 = 90, 108 IMX93_IOMUXC_SD2_RESET_B = 91, 109 IMX93_IOMUXC_I2C1_SCL = 92, 110 IMX93_IOMUXC_I2C1_SDA = 93, 111 IMX93_IOMUXC_I2C2_SCL = 94, 112 IMX93_IOMUXC_I2C2_SDA = 95, 113 IMX93_IOMUXC_UART1_RXD = 96, 114 IMX93_IOMUXC_UART1_TXD = 97, 115 IMX93_IOMUXC_UART2_RXD = 98, 116 IMX93_IOMUXC_UART2_TXD = 99, 117 IMX93_IOMUXC_PDM_CLK = 100, 118 IMX93_IOMUXC_PDM_BIT_STREAM0 = 101, 119 IMX93_IOMUXC_PDM_BIT_STREAM1 = 102, 120 IMX93_IOMUXC_SAI1_TXFS = 103, 121 IMX93_IOMUXC_SAI1_TXC = 104, 122 IMX93_IOMUXC_SAI1_TXD0 = 105, 123 IMX93_IOMUXC_SAI1_RXD0 = 106, 124 IMX93_IOMUXC_WDOG_ANY = 107, 125 }; 126 127 /* Pad names for the pinmux subsystem */ 128 static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = { 129 IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI), 130 IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO), 131 IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK), 132 IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO), 133 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00), 134 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01), 135 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02), 136 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03), 137 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04), 138 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05), 139 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06), 140 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07), 141 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08), 142 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09), 143 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10), 144 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11), 145 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12), 146 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13), 147 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14), 148 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15), 149 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16), 150 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17), 151 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18), 152 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19), 153 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20), 154 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21), 155 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22), 156 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23), 157 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24), 158 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25), 159 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26), 160 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27), 161 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28), 162 IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29), 163 IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1), 164 IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2), 165 IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3), 166 IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4), 167 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC), 168 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO), 169 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3), 170 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2), 171 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1), 172 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0), 173 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL), 174 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC), 175 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL), 176 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC), 177 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0), 178 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1), 179 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2), 180 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3), 181 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC), 182 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO), 183 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3), 184 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2), 185 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1), 186 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0), 187 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL), 188 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC), 189 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL), 190 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC), 191 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0), 192 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1), 193 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2), 194 IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3), 195 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK), 196 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD), 197 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0), 198 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1), 199 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2), 200 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3), 201 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4), 202 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5), 203 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6), 204 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7), 205 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE), 206 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT), 207 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK), 208 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD), 209 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0), 210 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1), 211 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2), 212 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3), 213 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B), 214 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK), 215 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD), 216 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0), 217 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1), 218 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2), 219 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3), 220 IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B), 221 IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL), 222 IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA), 223 IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL), 224 IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA), 225 IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD), 226 IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD), 227 IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD), 228 IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD), 229 IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK), 230 IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0), 231 IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1), 232 IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS), 233 IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC), 234 IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0), 235 IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0), 236 IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY), 237 }; 238 239 static const struct imx_pinctrl_soc_info imx93_pinctrl_info = { 240 .pins = imx93_pinctrl_pads, 241 .npins = ARRAY_SIZE(imx93_pinctrl_pads), 242 .flags = ZERO_OFFSET_VALID, 243 .gpr_compatible = "fsl,imx93-iomuxc-gpr", 244 }; 245 246 static const struct of_device_id imx93_pinctrl_of_match[] = { 247 { .compatible = "fsl,imx93-iomuxc", }, 248 { /* sentinel */ } 249 }; 250 251 static int imx93_pinctrl_probe(struct platform_device *pdev) 252 { 253 return imx_pinctrl_probe(pdev, &imx93_pinctrl_info); 254 } 255 256 static struct platform_driver imx93_pinctrl_driver = { 257 .driver = { 258 .name = "imx93-pinctrl", 259 .of_match_table = imx93_pinctrl_of_match, 260 .suppress_bind_attrs = true, 261 }, 262 .probe = imx93_pinctrl_probe, 263 }; 264 265 static int __init imx93_pinctrl_init(void) 266 { 267 return platform_driver_register(&imx93_pinctrl_driver); 268 } 269 arch_initcall(imx93_pinctrl_init); 270 271 MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>"); 272 MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver"); 273 MODULE_LICENSE("GPL v2"); 274