1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/pinctrl.h> 14 15 #include "pinctrl-imx.h" 16 17 enum imx8mq_pads { 18 MX8MQ_PAD_RESERVE0 = 0, 19 MX8MQ_PAD_RESERVE1 = 1, 20 MX8MQ_PAD_RESERVE2 = 2, 21 MX8MQ_PAD_RESERVE3 = 3, 22 MX8MQ_PAD_RESERVE4 = 4, 23 MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5, 24 MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6, 25 MX8MQ_IOMUXC_ONOFF_SNVSMIX = 7, 26 MX8MQ_IOMUXC_POR_B_SNVSMIX = 8, 27 MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9, 28 MX8MQ_IOMUXC_GPIO1_IO00 = 10, 29 MX8MQ_IOMUXC_GPIO1_IO01 = 11, 30 MX8MQ_IOMUXC_GPIO1_IO02 = 12, 31 MX8MQ_IOMUXC_GPIO1_IO03 = 13, 32 MX8MQ_IOMUXC_GPIO1_IO04 = 14, 33 MX8MQ_IOMUXC_GPIO1_IO05 = 15, 34 MX8MQ_IOMUXC_GPIO1_IO06 = 16, 35 MX8MQ_IOMUXC_GPIO1_IO07 = 17, 36 MX8MQ_IOMUXC_GPIO1_IO08 = 18, 37 MX8MQ_IOMUXC_GPIO1_IO09 = 19, 38 MX8MQ_IOMUXC_GPIO1_IO10 = 20, 39 MX8MQ_IOMUXC_GPIO1_IO11 = 21, 40 MX8MQ_IOMUXC_GPIO1_IO12 = 22, 41 MX8MQ_IOMUXC_GPIO1_IO13 = 23, 42 MX8MQ_IOMUXC_GPIO1_IO14 = 24, 43 MX8MQ_IOMUXC_GPIO1_IO15 = 25, 44 MX8MQ_IOMUXC_ENET_MDC = 26, 45 MX8MQ_IOMUXC_ENET_MDIO = 27, 46 MX8MQ_IOMUXC_ENET_TD3 = 28, 47 MX8MQ_IOMUXC_ENET_TD2 = 29, 48 MX8MQ_IOMUXC_ENET_TD1 = 30, 49 MX8MQ_IOMUXC_ENET_TD0 = 31, 50 MX8MQ_IOMUXC_ENET_TX_CTL = 32, 51 MX8MQ_IOMUXC_ENET_TXC = 33, 52 MX8MQ_IOMUXC_ENET_RX_CTL = 34, 53 MX8MQ_IOMUXC_ENET_RXC = 35, 54 MX8MQ_IOMUXC_ENET_RD0 = 36, 55 MX8MQ_IOMUXC_ENET_RD1 = 37, 56 MX8MQ_IOMUXC_ENET_RD2 = 38, 57 MX8MQ_IOMUXC_ENET_RD3 = 39, 58 MX8MQ_IOMUXC_SD1_CLK = 40, 59 MX8MQ_IOMUXC_SD1_CMD = 41, 60 MX8MQ_IOMUXC_SD1_DATA0 = 42, 61 MX8MQ_IOMUXC_SD1_DATA1 = 43, 62 MX8MQ_IOMUXC_SD1_DATA2 = 44, 63 MX8MQ_IOMUXC_SD1_DATA3 = 45, 64 MX8MQ_IOMUXC_SD1_DATA4 = 46, 65 MX8MQ_IOMUXC_SD1_DATA5 = 47, 66 MX8MQ_IOMUXC_SD1_DATA6 = 48, 67 MX8MQ_IOMUXC_SD1_DATA7 = 49, 68 MX8MQ_IOMUXC_SD1_RESET_B = 50, 69 MX8MQ_IOMUXC_SD1_STROBE = 51, 70 MX8MQ_IOMUXC_SD2_CD_B = 52, 71 MX8MQ_IOMUXC_SD2_CLK = 53, 72 MX8MQ_IOMUXC_SD2_CMD = 54, 73 MX8MQ_IOMUXC_SD2_DATA0 = 55, 74 MX8MQ_IOMUXC_SD2_DATA1 = 56, 75 MX8MQ_IOMUXC_SD2_DATA2 = 57, 76 MX8MQ_IOMUXC_SD2_DATA3 = 58, 77 MX8MQ_IOMUXC_SD2_RESET_B = 59, 78 MX8MQ_IOMUXC_SD2_WP = 60, 79 MX8MQ_IOMUXC_NAND_ALE = 61, 80 MX8MQ_IOMUXC_NAND_CE0_B = 62, 81 MX8MQ_IOMUXC_NAND_CE1_B = 63, 82 MX8MQ_IOMUXC_NAND_CE2_B = 64, 83 MX8MQ_IOMUXC_NAND_CE3_B = 65, 84 MX8MQ_IOMUXC_NAND_CLE = 66, 85 MX8MQ_IOMUXC_NAND_DATA00 = 67, 86 MX8MQ_IOMUXC_NAND_DATA01 = 68, 87 MX8MQ_IOMUXC_NAND_DATA02 = 69, 88 MX8MQ_IOMUXC_NAND_DATA03 = 70, 89 MX8MQ_IOMUXC_NAND_DATA04 = 71, 90 MX8MQ_IOMUXC_NAND_DATA05 = 72, 91 MX8MQ_IOMUXC_NAND_DATA06 = 73, 92 MX8MQ_IOMUXC_NAND_DATA07 = 74, 93 MX8MQ_IOMUXC_NAND_DQS = 75, 94 MX8MQ_IOMUXC_NAND_RE_B = 76, 95 MX8MQ_IOMUXC_NAND_READY_B = 77, 96 MX8MQ_IOMUXC_NAND_WE_B = 78, 97 MX8MQ_IOMUXC_NAND_WP_B = 79, 98 MX8MQ_IOMUXC_SAI5_RXFS = 80, 99 MX8MQ_IOMUXC_SAI5_RXC = 81, 100 MX8MQ_IOMUXC_SAI5_RXD0 = 82, 101 MX8MQ_IOMUXC_SAI5_RXD1 = 83, 102 MX8MQ_IOMUXC_SAI5_RXD2 = 84, 103 MX8MQ_IOMUXC_SAI5_RXD3 = 85, 104 MX8MQ_IOMUXC_SAI5_MCLK = 86, 105 MX8MQ_IOMUXC_SAI1_RXFS = 87, 106 MX8MQ_IOMUXC_SAI1_RXC = 88, 107 MX8MQ_IOMUXC_SAI1_RXD0 = 89, 108 MX8MQ_IOMUXC_SAI1_RXD1 = 90, 109 MX8MQ_IOMUXC_SAI1_RXD2 = 91, 110 MX8MQ_IOMUXC_SAI1_RXD3 = 92, 111 MX8MQ_IOMUXC_SAI1_RXD4 = 93, 112 MX8MQ_IOMUXC_SAI1_RXD5 = 94, 113 MX8MQ_IOMUXC_SAI1_RXD6 = 95, 114 MX8MQ_IOMUXC_SAI1_RXD7 = 96, 115 MX8MQ_IOMUXC_SAI1_TXFS = 97, 116 MX8MQ_IOMUXC_SAI1_TXC = 98, 117 MX8MQ_IOMUXC_SAI1_TXD0 = 99, 118 MX8MQ_IOMUXC_SAI1_TXD1 = 100, 119 MX8MQ_IOMUXC_SAI1_TXD2 = 101, 120 MX8MQ_IOMUXC_SAI1_TXD3 = 102, 121 MX8MQ_IOMUXC_SAI1_TXD4 = 103, 122 MX8MQ_IOMUXC_SAI1_TXD5 = 104, 123 MX8MQ_IOMUXC_SAI1_TXD6 = 105, 124 MX8MQ_IOMUXC_SAI1_TXD7 = 106, 125 MX8MQ_IOMUXC_SAI1_MCLK = 107, 126 MX8MQ_IOMUXC_SAI2_RXFS = 108, 127 MX8MQ_IOMUXC_SAI2_RXC = 109, 128 MX8MQ_IOMUXC_SAI2_RXD0 = 110, 129 MX8MQ_IOMUXC_SAI2_TXFS = 111, 130 MX8MQ_IOMUXC_SAI2_TXC = 112, 131 MX8MQ_IOMUXC_SAI2_TXD0 = 113, 132 MX8MQ_IOMUXC_SAI2_MCLK = 114, 133 MX8MQ_IOMUXC_SAI3_RXFS = 115, 134 MX8MQ_IOMUXC_SAI3_RXC = 116, 135 MX8MQ_IOMUXC_SAI3_RXD = 117, 136 MX8MQ_IOMUXC_SAI3_TXFS = 118, 137 MX8MQ_IOMUXC_SAI3_TXC = 119, 138 MX8MQ_IOMUXC_SAI3_TXD = 120, 139 MX8MQ_IOMUXC_SAI3_MCLK = 121, 140 MX8MQ_IOMUXC_SPDIF_TX = 122, 141 MX8MQ_IOMUXC_SPDIF_RX = 123, 142 MX8MQ_IOMUXC_SPDIF_EXT_CLK = 124, 143 MX8MQ_IOMUXC_ECSPI1_SCLK = 125, 144 MX8MQ_IOMUXC_ECSPI1_MOSI = 126, 145 MX8MQ_IOMUXC_ECSPI1_MISO = 127, 146 MX8MQ_IOMUXC_ECSPI1_SS0 = 128, 147 MX8MQ_IOMUXC_ECSPI2_SCLK = 129, 148 MX8MQ_IOMUXC_ECSPI2_MOSI = 130, 149 MX8MQ_IOMUXC_ECSPI2_MISO = 131, 150 MX8MQ_IOMUXC_ECSPI2_SS0 = 132, 151 MX8MQ_IOMUXC_I2C1_SCL = 133, 152 MX8MQ_IOMUXC_I2C1_SDA = 134, 153 MX8MQ_IOMUXC_I2C2_SCL = 135, 154 MX8MQ_IOMUXC_I2C2_SDA = 136, 155 MX8MQ_IOMUXC_I2C3_SCL = 137, 156 MX8MQ_IOMUXC_I2C3_SDA = 138, 157 MX8MQ_IOMUXC_I2C4_SCL = 139, 158 MX8MQ_IOMUXC_I2C4_SDA = 140, 159 MX8MQ_IOMUXC_UART1_RXD = 141, 160 MX8MQ_IOMUXC_UART1_TXD = 142, 161 MX8MQ_IOMUXC_UART2_RXD = 143, 162 MX8MQ_IOMUXC_UART2_TXD = 144, 163 MX8MQ_IOMUXC_UART3_RXD = 145, 164 MX8MQ_IOMUXC_UART3_TXD = 146, 165 MX8MQ_IOMUXC_UART4_RXD = 147, 166 MX8MQ_IOMUXC_UART4_TXD = 148, 167 }; 168 169 /* Pad names for the pinmux subsystem */ 170 static const struct pinctrl_pin_desc imx8mq_pinctrl_pads[] = { 171 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE0), 172 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE1), 173 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE2), 174 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE3), 175 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE4), 176 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX), 177 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX), 178 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ONOFF_SNVSMIX), 179 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_POR_B_SNVSMIX), 180 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX), 181 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO00), 182 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO01), 183 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO02), 184 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO03), 185 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO04), 186 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO05), 187 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO06), 188 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO07), 189 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO08), 190 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO09), 191 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO10), 192 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO11), 193 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO12), 194 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO13), 195 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO14), 196 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO15), 197 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDC), 198 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDIO), 199 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD3), 200 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD2), 201 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD1), 202 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD0), 203 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TX_CTL), 204 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TXC), 205 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RX_CTL), 206 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RXC), 207 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD0), 208 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD1), 209 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD2), 210 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD3), 211 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CLK), 212 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CMD), 213 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA0), 214 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA1), 215 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA2), 216 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA3), 217 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA4), 218 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA5), 219 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA6), 220 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA7), 221 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_RESET_B), 222 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_STROBE), 223 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CD_B), 224 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CLK), 225 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CMD), 226 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA0), 227 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA1), 228 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA2), 229 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA3), 230 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_RESET_B), 231 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_WP), 232 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_ALE), 233 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE0_B), 234 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE1_B), 235 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE2_B), 236 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE3_B), 237 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CLE), 238 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA00), 239 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA01), 240 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA02), 241 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA03), 242 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA04), 243 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA05), 244 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA06), 245 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA07), 246 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DQS), 247 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_RE_B), 248 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_READY_B), 249 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WE_B), 250 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WP_B), 251 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXFS), 252 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXC), 253 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD0), 254 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD1), 255 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD2), 256 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD3), 257 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_MCLK), 258 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXFS), 259 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXC), 260 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD0), 261 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD1), 262 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD2), 263 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD3), 264 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD4), 265 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD5), 266 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD6), 267 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD7), 268 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXFS), 269 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXC), 270 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD0), 271 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD1), 272 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD2), 273 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD3), 274 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD4), 275 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD5), 276 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD6), 277 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD7), 278 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_MCLK), 279 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXFS), 280 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXC), 281 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXD0), 282 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXFS), 283 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXC), 284 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXD0), 285 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_MCLK), 286 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXFS), 287 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXC), 288 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXD), 289 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXFS), 290 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXC), 291 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXD), 292 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_MCLK), 293 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_TX), 294 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_RX), 295 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_EXT_CLK), 296 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SCLK), 297 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MOSI), 298 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MISO), 299 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SS0), 300 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SCLK), 301 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MOSI), 302 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MISO), 303 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SS0), 304 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SCL), 305 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SDA), 306 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SCL), 307 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SDA), 308 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SCL), 309 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SDA), 310 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SCL), 311 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SDA), 312 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_RXD), 313 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_TXD), 314 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_RXD), 315 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_TXD), 316 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_RXD), 317 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_TXD), 318 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_RXD), 319 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_TXD), 320 }; 321 322 static const struct imx_pinctrl_soc_info imx8mq_pinctrl_info = { 323 .pins = imx8mq_pinctrl_pads, 324 .npins = ARRAY_SIZE(imx8mq_pinctrl_pads), 325 .gpr_compatible = "fsl,imx8mq-iomuxc-gpr", 326 }; 327 328 static const struct of_device_id imx8mq_pinctrl_of_match[] = { 329 { .compatible = "fsl,imx8mq-iomuxc", .data = &imx8mq_pinctrl_info, }, 330 { /* sentinel */ } 331 }; 332 333 static int imx8mq_pinctrl_probe(struct platform_device *pdev) 334 { 335 return imx_pinctrl_probe(pdev, &imx8mq_pinctrl_info); 336 } 337 338 static struct platform_driver imx8mq_pinctrl_driver = { 339 .driver = { 340 .name = "imx8mq-pinctrl", 341 .of_match_table = of_match_ptr(imx8mq_pinctrl_of_match), 342 .pm = &imx_pinctrl_pm_ops, 343 .suppress_bind_attrs = true, 344 }, 345 .probe = imx8mq_pinctrl_probe, 346 }; 347 348 static int __init imx8mq_pinctrl_init(void) 349 { 350 return platform_driver_register(&imx8mq_pinctrl_driver); 351 } 352 arch_initcall(imx8mq_pinctrl_init); 353