1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 NXP
4 */
5
6 #include <linux/err.h>
7 #include <linux/init.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/pinctrl/pinctrl.h>
11 #include <linux/platform_device.h>
12
13 #include "pinctrl-imx.h"
14
15 enum imx8mp_pads {
16 MX8MP_IOMUXC_RESERVE0 = 0,
17 MX8MP_IOMUXC_RESERVE1 = 1,
18 MX8MP_IOMUXC_RESERVE2 = 2,
19 MX8MP_IOMUXC_RESERVE3 = 3,
20 MX8MP_IOMUXC_RESERVE4 = 4,
21 MX8MP_IOMUXC_GPIO1_IO00 = 5,
22 MX8MP_IOMUXC_GPIO1_IO01 = 6,
23 MX8MP_IOMUXC_GPIO1_IO02 = 7,
24 MX8MP_IOMUXC_GPIO1_IO03 = 8,
25 MX8MP_IOMUXC_GPIO1_IO04 = 9,
26 MX8MP_IOMUXC_GPIO1_IO05 = 10,
27 MX8MP_IOMUXC_GPIO1_IO06 = 11,
28 MX8MP_IOMUXC_GPIO1_IO07 = 12,
29 MX8MP_IOMUXC_GPIO1_IO08 = 13,
30 MX8MP_IOMUXC_GPIO1_IO09 = 14,
31 MX8MP_IOMUXC_GPIO1_IO10 = 15,
32 MX8MP_IOMUXC_GPIO1_IO11 = 16,
33 MX8MP_IOMUXC_GPIO1_IO12 = 17,
34 MX8MP_IOMUXC_GPIO1_IO13 = 18,
35 MX8MP_IOMUXC_GPIO1_IO14 = 19,
36 MX8MP_IOMUXC_GPIO1_IO15 = 20,
37 MX8MP_IOMUXC_ENET_MDC = 21,
38 MX8MP_IOMUXC_ENET_MDIO = 22,
39 MX8MP_IOMUXC_ENET_TD3 = 23,
40 MX8MP_IOMUXC_ENET_TD2 = 24,
41 MX8MP_IOMUXC_ENET_TD1 = 25,
42 MX8MP_IOMUXC_ENET_TD0 = 26,
43 MX8MP_IOMUXC_ENET_TX_CTL = 27,
44 MX8MP_IOMUXC_ENET_TXC = 28,
45 MX8MP_IOMUXC_ENET_RX_CTL = 29,
46 MX8MP_IOMUXC_ENET_RXC = 30,
47 MX8MP_IOMUXC_ENET_RD0 = 31,
48 MX8MP_IOMUXC_ENET_RD1 = 32,
49 MX8MP_IOMUXC_ENET_RD2 = 33,
50 MX8MP_IOMUXC_ENET_RD3 = 34,
51 MX8MP_IOMUXC_SD1_CLK = 35,
52 MX8MP_IOMUXC_SD1_CMD = 36,
53 MX8MP_IOMUXC_SD1_DATA0 = 37,
54 MX8MP_IOMUXC_SD1_DATA1 = 38,
55 MX8MP_IOMUXC_SD1_DATA2 = 39,
56 MX8MP_IOMUXC_SD1_DATA3 = 40,
57 MX8MP_IOMUXC_SD1_DATA4 = 41,
58 MX8MP_IOMUXC_SD1_DATA5 = 42,
59 MX8MP_IOMUXC_SD1_DATA6 = 43,
60 MX8MP_IOMUXC_SD1_DATA7 = 44,
61 MX8MP_IOMUXC_SD1_RESET_B = 45,
62 MX8MP_IOMUXC_SD1_STROBE = 46,
63 MX8MP_IOMUXC_SD2_CD_B = 47,
64 MX8MP_IOMUXC_SD2_CLK = 48,
65 MX8MP_IOMUXC_SD2_CMD = 49,
66 MX8MP_IOMUXC_SD2_DATA0 = 50,
67 MX8MP_IOMUXC_SD2_DATA1 = 51,
68 MX8MP_IOMUXC_SD2_DATA2 = 52,
69 MX8MP_IOMUXC_SD2_DATA3 = 53,
70 MX8MP_IOMUXC_SD2_RESET_B = 54,
71 MX8MP_IOMUXC_SD2_WP = 55,
72 MX8MP_IOMUXC_NAND_ALE = 56,
73 MX8MP_IOMUXC_NAND_CE0_B = 57,
74 MX8MP_IOMUXC_NAND_CE1_B = 58,
75 MX8MP_IOMUXC_NAND_CE2_B = 59,
76 MX8MP_IOMUXC_NAND_CE3_B = 60,
77 MX8MP_IOMUXC_NAND_CLE = 61,
78 MX8MP_IOMUXC_NAND_DATA00 = 62,
79 MX8MP_IOMUXC_NAND_DATA01 = 63,
80 MX8MP_IOMUXC_NAND_DATA02 = 64,
81 MX8MP_IOMUXC_NAND_DATA03 = 65,
82 MX8MP_IOMUXC_NAND_DATA04 = 66,
83 MX8MP_IOMUXC_NAND_DATA05 = 67,
84 MX8MP_IOMUXC_NAND_DATA06 = 68,
85 MX8MP_IOMUXC_NAND_DATA07 = 69,
86 MX8MP_IOMUXC_NAND_DQS = 70,
87 MX8MP_IOMUXC_NAND_RE_B = 71,
88 MX8MP_IOMUXC_NAND_READY_B = 72,
89 MX8MP_IOMUXC_NAND_WE_B = 73,
90 MX8MP_IOMUXC_NAND_WP_B = 74,
91 MX8MP_IOMUXC_SAI5_RXFS = 75,
92 MX8MP_IOMUXC_SAI5_RXC = 76,
93 MX8MP_IOMUXC_SAI5_RXD0 = 77,
94 MX8MP_IOMUXC_SAI5_RXD1 = 78,
95 MX8MP_IOMUXC_SAI5_RXD2 = 79,
96 MX8MP_IOMUXC_SAI5_RXD3 = 80,
97 MX8MP_IOMUXC_SAI5_MCLK = 81,
98 MX8MP_IOMUXC_SAI1_RXFS = 82,
99 MX8MP_IOMUXC_SAI1_RXC = 83,
100 MX8MP_IOMUXC_SAI1_RXD0 = 84,
101 MX8MP_IOMUXC_SAI1_RXD1 = 85,
102 MX8MP_IOMUXC_SAI1_RXD2 = 86,
103 MX8MP_IOMUXC_SAI1_RXD3 = 87,
104 MX8MP_IOMUXC_SAI1_RXD4 = 88,
105 MX8MP_IOMUXC_SAI1_RXD5 = 89,
106 MX8MP_IOMUXC_SAI1_RXD6 = 90,
107 MX8MP_IOMUXC_SAI1_RXD7 = 91,
108 MX8MP_IOMUXC_SAI1_TXFS = 92,
109 MX8MP_IOMUXC_SAI1_TXC = 93,
110 MX8MP_IOMUXC_SAI1_TXD0 = 94,
111 MX8MP_IOMUXC_SAI1_TXD1 = 95,
112 MX8MP_IOMUXC_SAI1_TXD2 = 96,
113 MX8MP_IOMUXC_SAI1_TXD3 = 97,
114 MX8MP_IOMUXC_SAI1_TXD4 = 98,
115 MX8MP_IOMUXC_SAI1_TXD5 = 99,
116 MX8MP_IOMUXC_SAI1_TXD6 = 100,
117 MX8MP_IOMUXC_SAI1_TXD7 = 101,
118 MX8MP_IOMUXC_SAI1_MCLK = 102,
119 MX8MP_IOMUXC_SAI2_RXFS = 103,
120 MX8MP_IOMUXC_SAI2_RXC = 104,
121 MX8MP_IOMUXC_SAI2_RXD0 = 105,
122 MX8MP_IOMUXC_SAI2_TXFS = 106,
123 MX8MP_IOMUXC_SAI2_TXC = 107,
124 MX8MP_IOMUXC_SAI2_TXD0 = 108,
125 MX8MP_IOMUXC_SAI2_MCLK = 109,
126 MX8MP_IOMUXC_SAI3_RXFS = 110,
127 MX8MP_IOMUXC_SAI3_RXC = 111,
128 MX8MP_IOMUXC_SAI3_RXD = 112,
129 MX8MP_IOMUXC_SAI3_TXFS = 113,
130 MX8MP_IOMUXC_SAI3_TXC = 114,
131 MX8MP_IOMUXC_SAI3_TXD = 115,
132 MX8MP_IOMUXC_SAI3_MCLK = 116,
133 MX8MP_IOMUXC_SPDIF_TX = 117,
134 MX8MP_IOMUXC_SPDIF_RX = 118,
135 MX8MP_IOMUXC_SPDIF_EXT_CLK = 119,
136 MX8MP_IOMUXC_ECSPI1_SCLK = 120,
137 MX8MP_IOMUXC_ECSPI1_MOSI = 121,
138 MX8MP_IOMUXC_ECSPI1_MISO = 122,
139 MX8MP_IOMUXC_ECSPI1_SS0 = 123,
140 MX8MP_IOMUXC_ECSPI2_SCLK = 124,
141 MX8MP_IOMUXC_ECSPI2_MOSI = 125,
142 MX8MP_IOMUXC_ECSPI2_MISO = 126,
143 MX8MP_IOMUXC_ECSPI2_SS0 = 127,
144 MX8MP_IOMUXC_I2C1_SCL = 128,
145 MX8MP_IOMUXC_I2C1_SDA = 129,
146 MX8MP_IOMUXC_I2C2_SCL = 130,
147 MX8MP_IOMUXC_I2C2_SDA = 131,
148 MX8MP_IOMUXC_I2C3_SCL = 132,
149 MX8MP_IOMUXC_I2C3_SDA = 133,
150 MX8MP_IOMUXC_I2C4_SCL = 134,
151 MX8MP_IOMUXC_I2C4_SDA = 135,
152 MX8MP_IOMUXC_UART1_RXD = 136,
153 MX8MP_IOMUXC_UART1_TXD = 137,
154 MX8MP_IOMUXC_UART2_RXD = 138,
155 MX8MP_IOMUXC_UART2_TXD = 139,
156 MX8MP_IOMUXC_UART3_RXD = 140,
157 MX8MP_IOMUXC_UART3_TXD = 141,
158 MX8MP_IOMUXC_UART4_RXD = 142,
159 MX8MP_IOMUXC_UART4_TXD = 143,
160 MX8MP_IOMUXC_HDMI_DDC_SCL = 144,
161 MX8MP_IOMUXC_HDMI_DDC_SDA = 145,
162 MX8MP_IOMUXC_HDMI_CEC = 146,
163 MX8MP_IOMUXC_HDMI_HPD = 147,
164 };
165
166 /* Pad names for the pinmux subsystem */
167 static const struct pinctrl_pin_desc imx8mp_pinctrl_pads[] = {
168 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE0),
169 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE1),
170 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE2),
171 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE3),
172 IMX_PINCTRL_PIN(MX8MP_IOMUXC_RESERVE4),
173 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO00),
174 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO01),
175 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO02),
176 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO03),
177 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO04),
178 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO05),
179 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO06),
180 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO07),
181 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO08),
182 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO09),
183 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO10),
184 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO11),
185 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO12),
186 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO13),
187 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO14),
188 IMX_PINCTRL_PIN(MX8MP_IOMUXC_GPIO1_IO15),
189 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDC),
190 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_MDIO),
191 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD3),
192 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD2),
193 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD1),
194 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TD0),
195 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TX_CTL),
196 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_TXC),
197 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RX_CTL),
198 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RXC),
199 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD0),
200 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD1),
201 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD2),
202 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ENET_RD3),
203 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CLK),
204 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_CMD),
205 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA0),
206 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA1),
207 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA2),
208 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA3),
209 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA4),
210 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA5),
211 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA6),
212 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_DATA7),
213 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_RESET_B),
214 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD1_STROBE),
215 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CD_B),
216 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CLK),
217 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_CMD),
218 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA0),
219 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA1),
220 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA2),
221 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_DATA3),
222 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_RESET_B),
223 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SD2_WP),
224 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_ALE),
225 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE0_B),
226 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE1_B),
227 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE2_B),
228 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CE3_B),
229 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_CLE),
230 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA00),
231 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA01),
232 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA02),
233 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA03),
234 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA04),
235 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA05),
236 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA06),
237 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DATA07),
238 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_DQS),
239 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_RE_B),
240 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_READY_B),
241 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WE_B),
242 IMX_PINCTRL_PIN(MX8MP_IOMUXC_NAND_WP_B),
243 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXFS),
244 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXC),
245 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD0),
246 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD1),
247 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD2),
248 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_RXD3),
249 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI5_MCLK),
250 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXFS),
251 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXC),
252 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD0),
253 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD1),
254 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD2),
255 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD3),
256 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD4),
257 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD5),
258 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD6),
259 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_RXD7),
260 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXFS),
261 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXC),
262 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD0),
263 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD1),
264 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD2),
265 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD3),
266 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD4),
267 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD5),
268 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD6),
269 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_TXD7),
270 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI1_MCLK),
271 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXFS),
272 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXC),
273 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_RXD0),
274 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXFS),
275 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXC),
276 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_TXD0),
277 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI2_MCLK),
278 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXFS),
279 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXC),
280 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_RXD),
281 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXFS),
282 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXC),
283 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_TXD),
284 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SAI3_MCLK),
285 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_TX),
286 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_RX),
287 IMX_PINCTRL_PIN(MX8MP_IOMUXC_SPDIF_EXT_CLK),
288 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SCLK),
289 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MOSI),
290 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_MISO),
291 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI1_SS0),
292 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SCLK),
293 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MOSI),
294 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_MISO),
295 IMX_PINCTRL_PIN(MX8MP_IOMUXC_ECSPI2_SS0),
296 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SCL),
297 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C1_SDA),
298 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SCL),
299 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C2_SDA),
300 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SCL),
301 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C3_SDA),
302 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SCL),
303 IMX_PINCTRL_PIN(MX8MP_IOMUXC_I2C4_SDA),
304 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_RXD),
305 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART1_TXD),
306 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_RXD),
307 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART2_TXD),
308 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_RXD),
309 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART3_TXD),
310 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_RXD),
311 IMX_PINCTRL_PIN(MX8MP_IOMUXC_UART4_TXD),
312 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SCL),
313 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_DDC_SDA),
314 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_CEC),
315 IMX_PINCTRL_PIN(MX8MP_IOMUXC_HDMI_HPD),
316 };
317
318 static const struct imx_pinctrl_soc_info imx8mp_pinctrl_info = {
319 .pins = imx8mp_pinctrl_pads,
320 .npins = ARRAY_SIZE(imx8mp_pinctrl_pads),
321 .gpr_compatible = "fsl,imx8mp-iomuxc-gpr",
322 };
323
324 static const struct of_device_id imx8mp_pinctrl_of_match[] = {
325 { .compatible = "fsl,imx8mp-iomuxc", .data = &imx8mp_pinctrl_info, },
326 { /* sentinel */ }
327 };
328 MODULE_DEVICE_TABLE(of, imx8mp_pinctrl_of_match);
329
imx8mp_pinctrl_probe(struct platform_device * pdev)330 static int imx8mp_pinctrl_probe(struct platform_device *pdev)
331 {
332 return imx_pinctrl_probe(pdev, &imx8mp_pinctrl_info);
333 }
334
335 static struct platform_driver imx8mp_pinctrl_driver = {
336 .driver = {
337 .name = "imx8mp-pinctrl",
338 .of_match_table = imx8mp_pinctrl_of_match,
339 .suppress_bind_attrs = true,
340 },
341 .probe = imx8mp_pinctrl_probe,
342 };
343
imx8mp_pinctrl_init(void)344 static int __init imx8mp_pinctrl_init(void)
345 {
346 return platform_driver_register(&imx8mp_pinctrl_driver);
347 }
348 arch_initcall(imx8mp_pinctrl_init);
349
350 MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
351 MODULE_DESCRIPTION("NXP i.MX8MP pinctrl driver");
352 MODULE_LICENSE("GPL v2");
353