1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2018-2019 NXP
4  */
5 
6 #include <linux/err.h>
7 #include <linux/init.h>
8 #include <linux/of.h>
9 #include <linux/pinctrl/pinctrl.h>
10 #include <linux/platform_device.h>
11 
12 #include "pinctrl-imx.h"
13 
14 enum imx8mn_pads {
15 	MX8MN_PAD_RESERVE0 = 0,
16 	MX8MN_PAD_RESERVE1 = 1,
17 	MX8MN_PAD_RESERVE2 = 2,
18 	MX8MN_PAD_RESERVE3 = 3,
19 	MX8MN_PAD_RESERVE4 = 4,
20 	MX8MN_PAD_RESERVE5 = 5,
21 	MX8MN_PAD_RESERVE6 = 6,
22 	MX8MN_PAD_RESERVE7 = 7,
23 	MX8MN_IOMUXC_BOOT_MODE2 = 8,
24 	MX8MN_IOMUXC_BOOT_MODE3 = 9,
25 	MX8MN_IOMUXC_GPIO1_IO00 = 10,
26 	MX8MN_IOMUXC_GPIO1_IO01 = 11,
27 	MX8MN_IOMUXC_GPIO1_IO02 = 12,
28 	MX8MN_IOMUXC_GPIO1_IO03 = 13,
29 	MX8MN_IOMUXC_GPIO1_IO04 = 14,
30 	MX8MN_IOMUXC_GPIO1_IO05 = 15,
31 	MX8MN_IOMUXC_GPIO1_IO06 = 16,
32 	MX8MN_IOMUXC_GPIO1_IO07 = 17,
33 	MX8MN_IOMUXC_GPIO1_IO08 = 18,
34 	MX8MN_IOMUXC_GPIO1_IO09 = 19,
35 	MX8MN_IOMUXC_GPIO1_IO10 = 20,
36 	MX8MN_IOMUXC_GPIO1_IO11 = 21,
37 	MX8MN_IOMUXC_GPIO1_IO12 = 22,
38 	MX8MN_IOMUXC_GPIO1_IO13 = 23,
39 	MX8MN_IOMUXC_GPIO1_IO14 = 24,
40 	MX8MN_IOMUXC_GPIO1_IO15 = 25,
41 	MX8MN_IOMUXC_ENET_MDC = 26,
42 	MX8MN_IOMUXC_ENET_MDIO = 27,
43 	MX8MN_IOMUXC_ENET_TD3 = 28,
44 	MX8MN_IOMUXC_ENET_TD2 = 29,
45 	MX8MN_IOMUXC_ENET_TD1 = 30,
46 	MX8MN_IOMUXC_ENET_TD0 = 31,
47 	MX8MN_IOMUXC_ENET_TX_CTL = 32,
48 	MX8MN_IOMUXC_ENET_TXC = 33,
49 	MX8MN_IOMUXC_ENET_RX_CTL = 34,
50 	MX8MN_IOMUXC_ENET_RXC = 35,
51 	MX8MN_IOMUXC_ENET_RD0 = 36,
52 	MX8MN_IOMUXC_ENET_RD1 = 37,
53 	MX8MN_IOMUXC_ENET_RD2 = 38,
54 	MX8MN_IOMUXC_ENET_RD3 = 39,
55 	MX8MN_IOMUXC_SD1_CLK = 40,
56 	MX8MN_IOMUXC_SD1_CMD = 41,
57 	MX8MN_IOMUXC_SD1_DATA0 = 42,
58 	MX8MN_IOMUXC_SD1_DATA1 = 43,
59 	MX8MN_IOMUXC_SD1_DATA2 = 44,
60 	MX8MN_IOMUXC_SD1_DATA3 = 45,
61 	MX8MN_IOMUXC_SD1_DATA4 = 46,
62 	MX8MN_IOMUXC_SD1_DATA5 = 47,
63 	MX8MN_IOMUXC_SD1_DATA6 = 48,
64 	MX8MN_IOMUXC_SD1_DATA7 = 49,
65 	MX8MN_IOMUXC_SD1_RESET_B = 50,
66 	MX8MN_IOMUXC_SD1_STROBE = 51,
67 	MX8MN_IOMUXC_SD2_CD_B = 52,
68 	MX8MN_IOMUXC_SD2_CLK = 53,
69 	MX8MN_IOMUXC_SD2_CMD = 54,
70 	MX8MN_IOMUXC_SD2_DATA0 = 55,
71 	MX8MN_IOMUXC_SD2_DATA1 = 56,
72 	MX8MN_IOMUXC_SD2_DATA2 = 57,
73 	MX8MN_IOMUXC_SD2_DATA3 = 58,
74 	MX8MN_IOMUXC_SD2_RESET_B = 59,
75 	MX8MN_IOMUXC_SD2_WP = 60,
76 	MX8MN_IOMUXC_NAND_ALE = 61,
77 	MX8MN_IOMUXC_NAND_CE0 = 62,
78 	MX8MN_IOMUXC_NAND_CE1 = 63,
79 	MX8MN_IOMUXC_NAND_CE2 = 64,
80 	MX8MN_IOMUXC_NAND_CE3 = 65,
81 	MX8MN_IOMUXC_NAND_CLE = 66,
82 	MX8MN_IOMUXC_NAND_DATA00 = 67,
83 	MX8MN_IOMUXC_NAND_DATA01 = 68,
84 	MX8MN_IOMUXC_NAND_DATA02 = 69,
85 	MX8MN_IOMUXC_NAND_DATA03 = 70,
86 	MX8MN_IOMUXC_NAND_DATA04 = 71,
87 	MX8MN_IOMUXC_NAND_DATA05 = 72,
88 	MX8MN_IOMUXC_NAND_DATA06 = 73,
89 	MX8MN_IOMUXC_NAND_DATA07 = 74,
90 	MX8MN_IOMUXC_NAND_DQS = 75,
91 	MX8MN_IOMUXC_NAND_RE_B = 76,
92 	MX8MN_IOMUXC_NAND_READY_B = 77,
93 	MX8MN_IOMUXC_NAND_WE_B = 78,
94 	MX8MN_IOMUXC_NAND_WP_B = 79,
95 	MX8MN_IOMUXC_SAI5_RXFS = 80,
96 	MX8MN_IOMUXC_SAI5_RXC = 81,
97 	MX8MN_IOMUXC_SAI5_RXD0 = 82,
98 	MX8MN_IOMUXC_SAI5_RXD1 = 83,
99 	MX8MN_IOMUXC_SAI5_RXD2 = 84,
100 	MX8MN_IOMUXC_SAI5_RXD3 = 85,
101 	MX8MN_IOMUXC_SAI5_MCLK = 86,
102 	MX8MN_IOMUXC_SAI1_RXFS = 87,
103 	MX8MN_IOMUXC_SAI1_RXC = 88,
104 	MX8MN_IOMUXC_SAI1_RXD0 = 89,
105 	MX8MN_IOMUXC_SAI1_RXD1 = 90,
106 	MX8MN_IOMUXC_SAI1_RXD2 = 91,
107 	MX8MN_IOMUXC_SAI1_RXD3 = 92,
108 	MX8MN_IOMUXC_SAI1_RXD4 = 93,
109 	MX8MN_IOMUXC_SAI1_RXD5 = 94,
110 	MX8MN_IOMUXC_SAI1_RXD6 = 95,
111 	MX8MN_IOMUXC_SAI1_RXD7 = 96,
112 	MX8MN_IOMUXC_SAI1_TXFS = 97,
113 	MX8MN_IOMUXC_SAI1_TXC = 98,
114 	MX8MN_IOMUXC_SAI1_TXD0 = 99,
115 	MX8MN_IOMUXC_SAI1_TXD1 = 100,
116 	MX8MN_IOMUXC_SAI1_TXD2 = 101,
117 	MX8MN_IOMUXC_SAI1_TXD3 = 102,
118 	MX8MN_IOMUXC_SAI1_TXD4 = 103,
119 	MX8MN_IOMUXC_SAI1_TXD5 = 104,
120 	MX8MN_IOMUXC_SAI1_TXD6 = 105,
121 	MX8MN_IOMUXC_SAI1_TXD7 = 106,
122 	MX8MN_IOMUXC_SAI1_MCLK = 107,
123 	MX8MN_IOMUXC_SAI2_RXFS = 108,
124 	MX8MN_IOMUXC_SAI2_RXC = 109,
125 	MX8MN_IOMUXC_SAI2_RXD0 = 110,
126 	MX8MN_IOMUXC_SAI2_TXFS = 111,
127 	MX8MN_IOMUXC_SAI2_TXC = 112,
128 	MX8MN_IOMUXC_SAI2_TXD0 = 113,
129 	MX8MN_IOMUXC_SAI2_MCLK = 114,
130 	MX8MN_IOMUXC_SAI3_RXFS = 115,
131 	MX8MN_IOMUXC_SAI3_RXC = 116,
132 	MX8MN_IOMUXC_SAI3_RXD = 117,
133 	MX8MN_IOMUXC_SAI3_TXFS = 118,
134 	MX8MN_IOMUXC_SAI3_TXC = 119,
135 	MX8MN_IOMUXC_SAI3_TXD = 120,
136 	MX8MN_IOMUXC_SAI3_MCLK = 121,
137 	MX8MN_IOMUXC_SPDIF_TX = 122,
138 	MX8MN_IOMUXC_SPDIF_RX = 123,
139 	MX8MN_IOMUXC_SPDIF_EXT_CLK = 124,
140 	MX8MN_IOMUXC_ECSPI1_SCLK = 125,
141 	MX8MN_IOMUXC_ECSPI1_MOSI = 126,
142 	MX8MN_IOMUXC_ECSPI1_MISO = 127,
143 	MX8MN_IOMUXC_ECSPI1_SS0 = 128,
144 	MX8MN_IOMUXC_ECSPI2_SCLK = 129,
145 	MX8MN_IOMUXC_ECSPI2_MOSI = 130,
146 	MX8MN_IOMUXC_ECSPI2_MISO = 131,
147 	MX8MN_IOMUXC_ECSPI2_SS0 = 132,
148 	MX8MN_IOMUXC_I2C1_SCL = 133,
149 	MX8MN_IOMUXC_I2C1_SDA = 134,
150 	MX8MN_IOMUXC_I2C2_SCL = 135,
151 	MX8MN_IOMUXC_I2C2_SDA = 136,
152 	MX8MN_IOMUXC_I2C3_SCL = 137,
153 	MX8MN_IOMUXC_I2C3_SDA = 138,
154 	MX8MN_IOMUXC_I2C4_SCL = 139,
155 	MX8MN_IOMUXC_I2C4_SDA = 140,
156 	MX8MN_IOMUXC_UART1_RXD = 141,
157 	MX8MN_IOMUXC_UART1_TXD = 142,
158 	MX8MN_IOMUXC_UART2_RXD = 143,
159 	MX8MN_IOMUXC_UART2_TXD = 144,
160 	MX8MN_IOMUXC_UART3_RXD = 145,
161 	MX8MN_IOMUXC_UART3_TXD = 146,
162 	MX8MN_IOMUXC_UART4_RXD = 147,
163 	MX8MN_IOMUXC_UART4_TXD = 148,
164 };
165 
166 /* Pad names for the pinmux subsystem */
167 static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = {
168 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE0),
169 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE1),
170 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE2),
171 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE3),
172 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE4),
173 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE5),
174 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE6),
175 	IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE7),
176 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE2),
177 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE3),
178 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO00),
179 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO01),
180 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO02),
181 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO03),
182 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO04),
183 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO05),
184 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO06),
185 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO07),
186 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO08),
187 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO09),
188 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO10),
189 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO11),
190 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO12),
191 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO13),
192 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO14),
193 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO15),
194 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDC),
195 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDIO),
196 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD3),
197 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD2),
198 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD1),
199 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD0),
200 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TX_CTL),
201 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TXC),
202 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RX_CTL),
203 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RXC),
204 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD0),
205 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD1),
206 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD2),
207 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD3),
208 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CLK),
209 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CMD),
210 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA0),
211 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA1),
212 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA2),
213 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA3),
214 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA4),
215 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA5),
216 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA6),
217 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA7),
218 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_RESET_B),
219 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_STROBE),
220 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CD_B),
221 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CLK),
222 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CMD),
223 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA0),
224 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA1),
225 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA2),
226 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA3),
227 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_RESET_B),
228 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_WP),
229 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_ALE),
230 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE0),
231 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE1),
232 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE2),
233 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE3),
234 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CLE),
235 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA00),
236 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA01),
237 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA02),
238 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA03),
239 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA04),
240 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA05),
241 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA06),
242 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA07),
243 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DQS),
244 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_RE_B),
245 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_READY_B),
246 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WE_B),
247 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WP_B),
248 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXFS),
249 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXC),
250 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD0),
251 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD1),
252 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD2),
253 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD3),
254 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_MCLK),
255 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXFS),
256 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXC),
257 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD0),
258 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD1),
259 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD2),
260 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD3),
261 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD4),
262 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD5),
263 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD6),
264 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD7),
265 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXFS),
266 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXC),
267 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD0),
268 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD1),
269 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD2),
270 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD3),
271 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD4),
272 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD5),
273 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD6),
274 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD7),
275 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_MCLK),
276 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXFS),
277 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXC),
278 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXD0),
279 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXFS),
280 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXC),
281 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXD0),
282 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_MCLK),
283 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXFS),
284 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXC),
285 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXD),
286 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXFS),
287 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXC),
288 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXD),
289 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_MCLK),
290 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_TX),
291 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_RX),
292 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_EXT_CLK),
293 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SCLK),
294 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MOSI),
295 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MISO),
296 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SS0),
297 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SCLK),
298 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MOSI),
299 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MISO),
300 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SS0),
301 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SCL),
302 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SDA),
303 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SCL),
304 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SDA),
305 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SCL),
306 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SDA),
307 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SCL),
308 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SDA),
309 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_RXD),
310 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_TXD),
311 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_RXD),
312 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_TXD),
313 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_RXD),
314 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_TXD),
315 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_RXD),
316 	IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD),
317 };
318 
319 static struct imx_pinctrl_soc_info imx8mn_pinctrl_info = {
320 	.pins = imx8mn_pinctrl_pads,
321 	.npins = ARRAY_SIZE(imx8mn_pinctrl_pads),
322 	.gpr_compatible = "fsl,imx8mn-iomuxc-gpr",
323 };
324 
325 static const struct of_device_id imx8mn_pinctrl_of_match[] = {
326 	{ .compatible = "fsl,imx8mn-iomuxc", .data = &imx8mn_pinctrl_info, },
327 	{ /* sentinel */ }
328 };
329 
330 static int imx8mn_pinctrl_probe(struct platform_device *pdev)
331 {
332 	return imx_pinctrl_probe(pdev, &imx8mn_pinctrl_info);
333 }
334 
335 static struct platform_driver imx8mn_pinctrl_driver = {
336 	.driver = {
337 		.name = "imx8mn-pinctrl",
338 		.of_match_table = of_match_ptr(imx8mn_pinctrl_of_match),
339 		.suppress_bind_attrs = true,
340 	},
341 	.probe = imx8mn_pinctrl_probe,
342 };
343 
344 static int __init imx8mn_pinctrl_init(void)
345 {
346 	return platform_driver_register(&imx8mn_pinctrl_driver);
347 }
348 arch_initcall(imx8mn_pinctrl_init);
349