1d9c238c5SAnson Huang // SPDX-License-Identifier: GPL-2.0 2d9c238c5SAnson Huang /* 3d9c238c5SAnson Huang * Copyright 2018-2019 NXP 4d9c238c5SAnson Huang */ 5d9c238c5SAnson Huang 6d9c238c5SAnson Huang #include <linux/err.h> 7d9c238c5SAnson Huang #include <linux/init.h> 84bb63d21SAnson Huang #include <linux/module.h> 9d9c238c5SAnson Huang #include <linux/of.h> 10d9c238c5SAnson Huang #include <linux/pinctrl/pinctrl.h> 11d9c238c5SAnson Huang #include <linux/platform_device.h> 12d9c238c5SAnson Huang 13d9c238c5SAnson Huang #include "pinctrl-imx.h" 14d9c238c5SAnson Huang 15d9c238c5SAnson Huang enum imx8mn_pads { 16d9c238c5SAnson Huang MX8MN_PAD_RESERVE0 = 0, 17d9c238c5SAnson Huang MX8MN_PAD_RESERVE1 = 1, 18d9c238c5SAnson Huang MX8MN_PAD_RESERVE2 = 2, 19d9c238c5SAnson Huang MX8MN_PAD_RESERVE3 = 3, 20d9c238c5SAnson Huang MX8MN_PAD_RESERVE4 = 4, 21d9c238c5SAnson Huang MX8MN_PAD_RESERVE5 = 5, 22d9c238c5SAnson Huang MX8MN_PAD_RESERVE6 = 6, 23d9c238c5SAnson Huang MX8MN_PAD_RESERVE7 = 7, 24d9c238c5SAnson Huang MX8MN_IOMUXC_BOOT_MODE2 = 8, 25d9c238c5SAnson Huang MX8MN_IOMUXC_BOOT_MODE3 = 9, 26d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO00 = 10, 27d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO01 = 11, 28d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO02 = 12, 29d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO03 = 13, 30d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO04 = 14, 31d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO05 = 15, 32d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO06 = 16, 33d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO07 = 17, 34d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO08 = 18, 35d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO09 = 19, 36d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO10 = 20, 37d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO11 = 21, 38d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO12 = 22, 39d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO13 = 23, 40d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO14 = 24, 41d9c238c5SAnson Huang MX8MN_IOMUXC_GPIO1_IO15 = 25, 42d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_MDC = 26, 43d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_MDIO = 27, 44d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_TD3 = 28, 45d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_TD2 = 29, 46d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_TD1 = 30, 47d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_TD0 = 31, 48d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_TX_CTL = 32, 49d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_TXC = 33, 50d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_RX_CTL = 34, 51d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_RXC = 35, 52d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_RD0 = 36, 53d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_RD1 = 37, 54d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_RD2 = 38, 55d9c238c5SAnson Huang MX8MN_IOMUXC_ENET_RD3 = 39, 56d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_CLK = 40, 57d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_CMD = 41, 58d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA0 = 42, 59d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA1 = 43, 60d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA2 = 44, 61d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA3 = 45, 62d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA4 = 46, 63d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA5 = 47, 64d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA6 = 48, 65d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_DATA7 = 49, 66d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_RESET_B = 50, 67d9c238c5SAnson Huang MX8MN_IOMUXC_SD1_STROBE = 51, 68d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_CD_B = 52, 69d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_CLK = 53, 70d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_CMD = 54, 71d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_DATA0 = 55, 72d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_DATA1 = 56, 73d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_DATA2 = 57, 74d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_DATA3 = 58, 75d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_RESET_B = 59, 76d9c238c5SAnson Huang MX8MN_IOMUXC_SD2_WP = 60, 77d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_ALE = 61, 78d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_CE0 = 62, 79d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_CE1 = 63, 80d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_CE2 = 64, 81d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_CE3 = 65, 82d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_CLE = 66, 83d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA00 = 67, 84d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA01 = 68, 85d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA02 = 69, 86d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA03 = 70, 87d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA04 = 71, 88d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA05 = 72, 89d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA06 = 73, 90d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DATA07 = 74, 91d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_DQS = 75, 92d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_RE_B = 76, 93d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_READY_B = 77, 94d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_WE_B = 78, 95d9c238c5SAnson Huang MX8MN_IOMUXC_NAND_WP_B = 79, 96d9c238c5SAnson Huang MX8MN_IOMUXC_SAI5_RXFS = 80, 97d9c238c5SAnson Huang MX8MN_IOMUXC_SAI5_RXC = 81, 98d9c238c5SAnson Huang MX8MN_IOMUXC_SAI5_RXD0 = 82, 99d9c238c5SAnson Huang MX8MN_IOMUXC_SAI5_RXD1 = 83, 100d9c238c5SAnson Huang MX8MN_IOMUXC_SAI5_RXD2 = 84, 101d9c238c5SAnson Huang MX8MN_IOMUXC_SAI5_RXD3 = 85, 102d9c238c5SAnson Huang MX8MN_IOMUXC_SAI5_MCLK = 86, 103d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXFS = 87, 104d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXC = 88, 105d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD0 = 89, 106d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD1 = 90, 107d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD2 = 91, 108d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD3 = 92, 109d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD4 = 93, 110d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD5 = 94, 111d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD6 = 95, 112d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_RXD7 = 96, 113d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXFS = 97, 114d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXC = 98, 115d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD0 = 99, 116d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD1 = 100, 117d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD2 = 101, 118d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD3 = 102, 119d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD4 = 103, 120d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD5 = 104, 121d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD6 = 105, 122d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_TXD7 = 106, 123d9c238c5SAnson Huang MX8MN_IOMUXC_SAI1_MCLK = 107, 124d9c238c5SAnson Huang MX8MN_IOMUXC_SAI2_RXFS = 108, 125d9c238c5SAnson Huang MX8MN_IOMUXC_SAI2_RXC = 109, 126d9c238c5SAnson Huang MX8MN_IOMUXC_SAI2_RXD0 = 110, 127d9c238c5SAnson Huang MX8MN_IOMUXC_SAI2_TXFS = 111, 128d9c238c5SAnson Huang MX8MN_IOMUXC_SAI2_TXC = 112, 129d9c238c5SAnson Huang MX8MN_IOMUXC_SAI2_TXD0 = 113, 130d9c238c5SAnson Huang MX8MN_IOMUXC_SAI2_MCLK = 114, 131d9c238c5SAnson Huang MX8MN_IOMUXC_SAI3_RXFS = 115, 132d9c238c5SAnson Huang MX8MN_IOMUXC_SAI3_RXC = 116, 133d9c238c5SAnson Huang MX8MN_IOMUXC_SAI3_RXD = 117, 134d9c238c5SAnson Huang MX8MN_IOMUXC_SAI3_TXFS = 118, 135d9c238c5SAnson Huang MX8MN_IOMUXC_SAI3_TXC = 119, 136d9c238c5SAnson Huang MX8MN_IOMUXC_SAI3_TXD = 120, 137d9c238c5SAnson Huang MX8MN_IOMUXC_SAI3_MCLK = 121, 138d9c238c5SAnson Huang MX8MN_IOMUXC_SPDIF_TX = 122, 139d9c238c5SAnson Huang MX8MN_IOMUXC_SPDIF_RX = 123, 140d9c238c5SAnson Huang MX8MN_IOMUXC_SPDIF_EXT_CLK = 124, 141d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI1_SCLK = 125, 142d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI1_MOSI = 126, 143d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI1_MISO = 127, 144d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI1_SS0 = 128, 145d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI2_SCLK = 129, 146d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI2_MOSI = 130, 147d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI2_MISO = 131, 148d9c238c5SAnson Huang MX8MN_IOMUXC_ECSPI2_SS0 = 132, 149d9c238c5SAnson Huang MX8MN_IOMUXC_I2C1_SCL = 133, 150d9c238c5SAnson Huang MX8MN_IOMUXC_I2C1_SDA = 134, 151d9c238c5SAnson Huang MX8MN_IOMUXC_I2C2_SCL = 135, 152d9c238c5SAnson Huang MX8MN_IOMUXC_I2C2_SDA = 136, 153d9c238c5SAnson Huang MX8MN_IOMUXC_I2C3_SCL = 137, 154d9c238c5SAnson Huang MX8MN_IOMUXC_I2C3_SDA = 138, 155d9c238c5SAnson Huang MX8MN_IOMUXC_I2C4_SCL = 139, 156d9c238c5SAnson Huang MX8MN_IOMUXC_I2C4_SDA = 140, 157d9c238c5SAnson Huang MX8MN_IOMUXC_UART1_RXD = 141, 158d9c238c5SAnson Huang MX8MN_IOMUXC_UART1_TXD = 142, 159d9c238c5SAnson Huang MX8MN_IOMUXC_UART2_RXD = 143, 160d9c238c5SAnson Huang MX8MN_IOMUXC_UART2_TXD = 144, 161d9c238c5SAnson Huang MX8MN_IOMUXC_UART3_RXD = 145, 162d9c238c5SAnson Huang MX8MN_IOMUXC_UART3_TXD = 146, 163d9c238c5SAnson Huang MX8MN_IOMUXC_UART4_RXD = 147, 164d9c238c5SAnson Huang MX8MN_IOMUXC_UART4_TXD = 148, 165d9c238c5SAnson Huang }; 166d9c238c5SAnson Huang 167d9c238c5SAnson Huang /* Pad names for the pinmux subsystem */ 168d9c238c5SAnson Huang static const struct pinctrl_pin_desc imx8mn_pinctrl_pads[] = { 169d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE0), 170d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE1), 171d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE2), 172d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE3), 173d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE4), 174d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE5), 175d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE6), 176d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_PAD_RESERVE7), 177d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE2), 178d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_BOOT_MODE3), 179d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO00), 180d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO01), 181d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO02), 182d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO03), 183d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO04), 184d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO05), 185d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO06), 186d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO07), 187d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO08), 188d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO09), 189d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO10), 190d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO11), 191d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO12), 192d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO13), 193d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO14), 194d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_GPIO1_IO15), 195d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDC), 196d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_MDIO), 197d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD3), 198d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD2), 199d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD1), 200d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TD0), 201d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TX_CTL), 202d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_TXC), 203d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RX_CTL), 204d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RXC), 205d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD0), 206d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD1), 207d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD2), 208d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ENET_RD3), 209d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CLK), 210d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_CMD), 211d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA0), 212d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA1), 213d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA2), 214d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA3), 215d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA4), 216d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA5), 217d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA6), 218d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_DATA7), 219d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_RESET_B), 220d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD1_STROBE), 221d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CD_B), 222d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CLK), 223d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_CMD), 224d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA0), 225d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA1), 226d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA2), 227d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_DATA3), 228d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_RESET_B), 229d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SD2_WP), 230d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_ALE), 231d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE0), 232d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE1), 233d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE2), 234d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CE3), 235d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_CLE), 236d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA00), 237d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA01), 238d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA02), 239d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA03), 240d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA04), 241d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA05), 242d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA06), 243d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DATA07), 244d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_DQS), 245d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_RE_B), 246d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_READY_B), 247d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WE_B), 248d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_NAND_WP_B), 249d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXFS), 250d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXC), 251d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD0), 252d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD1), 253d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD2), 254d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_RXD3), 255d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI5_MCLK), 256d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXFS), 257d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXC), 258d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD0), 259d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD1), 260d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD2), 261d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD3), 262d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD4), 263d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD5), 264d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD6), 265d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_RXD7), 266d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXFS), 267d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXC), 268d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD0), 269d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD1), 270d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD2), 271d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD3), 272d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD4), 273d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD5), 274d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD6), 275d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_TXD7), 276d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI1_MCLK), 277d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXFS), 278d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXC), 279d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_RXD0), 280d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXFS), 281d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXC), 282d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_TXD0), 283d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI2_MCLK), 284d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXFS), 285d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXC), 286d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_RXD), 287d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXFS), 288d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXC), 289d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_TXD), 290d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SAI3_MCLK), 291d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_TX), 292d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_RX), 293d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_SPDIF_EXT_CLK), 294d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SCLK), 295d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MOSI), 296d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_MISO), 297d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI1_SS0), 298d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SCLK), 299d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MOSI), 300d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_MISO), 301d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_ECSPI2_SS0), 302d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SCL), 303d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C1_SDA), 304d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SCL), 305d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C2_SDA), 306d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SCL), 307d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C3_SDA), 308d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SCL), 309d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_I2C4_SDA), 310d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_RXD), 311d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART1_TXD), 312d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_RXD), 313d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART2_TXD), 314d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_RXD), 315d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART3_TXD), 316d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_RXD), 317d9c238c5SAnson Huang IMX_PINCTRL_PIN(MX8MN_IOMUXC_UART4_TXD), 318d9c238c5SAnson Huang }; 319d9c238c5SAnson Huang 320d9c238c5SAnson Huang static struct imx_pinctrl_soc_info imx8mn_pinctrl_info = { 321d9c238c5SAnson Huang .pins = imx8mn_pinctrl_pads, 322d9c238c5SAnson Huang .npins = ARRAY_SIZE(imx8mn_pinctrl_pads), 323d9c238c5SAnson Huang .gpr_compatible = "fsl,imx8mn-iomuxc-gpr", 324d9c238c5SAnson Huang }; 325d9c238c5SAnson Huang 326d9c238c5SAnson Huang static const struct of_device_id imx8mn_pinctrl_of_match[] = { 327d9c238c5SAnson Huang { .compatible = "fsl,imx8mn-iomuxc", .data = &imx8mn_pinctrl_info, }, 328d9c238c5SAnson Huang { /* sentinel */ } 329d9c238c5SAnson Huang }; 3304bb63d21SAnson Huang MODULE_DEVICE_TABLE(of, imx8mn_pinctrl_of_match); 331d9c238c5SAnson Huang 332d9c238c5SAnson Huang static int imx8mn_pinctrl_probe(struct platform_device *pdev) 333d9c238c5SAnson Huang { 334d9c238c5SAnson Huang return imx_pinctrl_probe(pdev, &imx8mn_pinctrl_info); 335d9c238c5SAnson Huang } 336d9c238c5SAnson Huang 337d9c238c5SAnson Huang static struct platform_driver imx8mn_pinctrl_driver = { 338d9c238c5SAnson Huang .driver = { 339d9c238c5SAnson Huang .name = "imx8mn-pinctrl", 340d9c238c5SAnson Huang .of_match_table = of_match_ptr(imx8mn_pinctrl_of_match), 341d9c238c5SAnson Huang .suppress_bind_attrs = true, 342d9c238c5SAnson Huang }, 343d9c238c5SAnson Huang .probe = imx8mn_pinctrl_probe, 344d9c238c5SAnson Huang }; 345d9c238c5SAnson Huang 346d9c238c5SAnson Huang static int __init imx8mn_pinctrl_init(void) 347d9c238c5SAnson Huang { 348d9c238c5SAnson Huang return platform_driver_register(&imx8mn_pinctrl_driver); 349d9c238c5SAnson Huang } 350d9c238c5SAnson Huang arch_initcall(imx8mn_pinctrl_init); 3514bb63d21SAnson Huang 3524bb63d21SAnson Huang MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>"); 3534bb63d21SAnson Huang MODULE_DESCRIPTION("NXP i.MX8MN pinctrl driver"); 3544bb63d21SAnson Huang MODULE_LICENSE("GPL v2"); 355