1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (C) 2016 Freescale Semiconductor, Inc.
4 // Copyright (C) 2017 NXP
5 //
6 // Author: Dong Aisheng <aisheng.dong@nxp.com>
7 
8 #include <linux/err.h>
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/pinctrl/pinctrl.h>
15 
16 #include "pinctrl-imx.h"
17 
18 enum imx7ulp_pads {
19 	IMX7ULP_PAD_PTC0 = 0,
20 	IMX7ULP_PAD_PTC1,
21 	IMX7ULP_PAD_PTC2,
22 	IMX7ULP_PAD_PTC3,
23 	IMX7ULP_PAD_PTC4,
24 	IMX7ULP_PAD_PTC5,
25 	IMX7ULP_PAD_PTC6,
26 	IMX7ULP_PAD_PTC7,
27 	IMX7ULP_PAD_PTC8,
28 	IMX7ULP_PAD_PTC9,
29 	IMX7ULP_PAD_PTC10,
30 	IMX7ULP_PAD_PTC11,
31 	IMX7ULP_PAD_PTC12,
32 	IMX7ULP_PAD_PTC13,
33 	IMX7ULP_PAD_PTC14,
34 	IMX7ULP_PAD_PTC15,
35 	IMX7ULP_PAD_PTC16,
36 	IMX7ULP_PAD_PTC17,
37 	IMX7ULP_PAD_PTC18,
38 	IMX7ULP_PAD_PTC19,
39 	IMX7ULP_PAD_RESERVE0,
40 	IMX7ULP_PAD_RESERVE1,
41 	IMX7ULP_PAD_RESERVE2,
42 	IMX7ULP_PAD_RESERVE3,
43 	IMX7ULP_PAD_RESERVE4,
44 	IMX7ULP_PAD_RESERVE5,
45 	IMX7ULP_PAD_RESERVE6,
46 	IMX7ULP_PAD_RESERVE7,
47 	IMX7ULP_PAD_RESERVE8,
48 	IMX7ULP_PAD_RESERVE9,
49 	IMX7ULP_PAD_RESERVE10,
50 	IMX7ULP_PAD_RESERVE11,
51 	IMX7ULP_PAD_PTD0,
52 	IMX7ULP_PAD_PTD1,
53 	IMX7ULP_PAD_PTD2,
54 	IMX7ULP_PAD_PTD3,
55 	IMX7ULP_PAD_PTD4,
56 	IMX7ULP_PAD_PTD5,
57 	IMX7ULP_PAD_PTD6,
58 	IMX7ULP_PAD_PTD7,
59 	IMX7ULP_PAD_PTD8,
60 	IMX7ULP_PAD_PTD9,
61 	IMX7ULP_PAD_PTD10,
62 	IMX7ULP_PAD_PTD11,
63 	IMX7ULP_PAD_RESERVE12,
64 	IMX7ULP_PAD_RESERVE13,
65 	IMX7ULP_PAD_RESERVE14,
66 	IMX7ULP_PAD_RESERVE15,
67 	IMX7ULP_PAD_RESERVE16,
68 	IMX7ULP_PAD_RESERVE17,
69 	IMX7ULP_PAD_RESERVE18,
70 	IMX7ULP_PAD_RESERVE19,
71 	IMX7ULP_PAD_RESERVE20,
72 	IMX7ULP_PAD_RESERVE21,
73 	IMX7ULP_PAD_RESERVE22,
74 	IMX7ULP_PAD_RESERVE23,
75 	IMX7ULP_PAD_RESERVE24,
76 	IMX7ULP_PAD_RESERVE25,
77 	IMX7ULP_PAD_RESERVE26,
78 	IMX7ULP_PAD_RESERVE27,
79 	IMX7ULP_PAD_RESERVE28,
80 	IMX7ULP_PAD_RESERVE29,
81 	IMX7ULP_PAD_RESERVE30,
82 	IMX7ULP_PAD_RESERVE31,
83 	IMX7ULP_PAD_PTE0,
84 	IMX7ULP_PAD_PTE1,
85 	IMX7ULP_PAD_PTE2,
86 	IMX7ULP_PAD_PTE3,
87 	IMX7ULP_PAD_PTE4,
88 	IMX7ULP_PAD_PTE5,
89 	IMX7ULP_PAD_PTE6,
90 	IMX7ULP_PAD_PTE7,
91 	IMX7ULP_PAD_PTE8,
92 	IMX7ULP_PAD_PTE9,
93 	IMX7ULP_PAD_PTE10,
94 	IMX7ULP_PAD_PTE11,
95 	IMX7ULP_PAD_PTE12,
96 	IMX7ULP_PAD_PTE13,
97 	IMX7ULP_PAD_PTE14,
98 	IMX7ULP_PAD_PTE15,
99 	IMX7ULP_PAD_RESERVE32,
100 	IMX7ULP_PAD_RESERVE33,
101 	IMX7ULP_PAD_RESERVE34,
102 	IMX7ULP_PAD_RESERVE35,
103 	IMX7ULP_PAD_RESERVE36,
104 	IMX7ULP_PAD_RESERVE37,
105 	IMX7ULP_PAD_RESERVE38,
106 	IMX7ULP_PAD_RESERVE39,
107 	IMX7ULP_PAD_RESERVE40,
108 	IMX7ULP_PAD_RESERVE41,
109 	IMX7ULP_PAD_RESERVE42,
110 	IMX7ULP_PAD_RESERVE43,
111 	IMX7ULP_PAD_RESERVE44,
112 	IMX7ULP_PAD_RESERVE45,
113 	IMX7ULP_PAD_RESERVE46,
114 	IMX7ULP_PAD_RESERVE47,
115 	IMX7ULP_PAD_PTF0,
116 	IMX7ULP_PAD_PTF1,
117 	IMX7ULP_PAD_PTF2,
118 	IMX7ULP_PAD_PTF3,
119 	IMX7ULP_PAD_PTF4,
120 	IMX7ULP_PAD_PTF5,
121 	IMX7ULP_PAD_PTF6,
122 	IMX7ULP_PAD_PTF7,
123 	IMX7ULP_PAD_PTF8,
124 	IMX7ULP_PAD_PTF9,
125 	IMX7ULP_PAD_PTF10,
126 	IMX7ULP_PAD_PTF11,
127 	IMX7ULP_PAD_PTF12,
128 	IMX7ULP_PAD_PTF13,
129 	IMX7ULP_PAD_PTF14,
130 	IMX7ULP_PAD_PTF15,
131 	IMX7ULP_PAD_PTF16,
132 	IMX7ULP_PAD_PTF17,
133 	IMX7ULP_PAD_PTF18,
134 	IMX7ULP_PAD_PTF19,
135 };
136 
137 /* Pad names for the pinmux subsystem */
138 static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
139 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
140 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
141 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
142 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
143 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
144 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
145 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
146 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
147 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
148 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
149 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
150 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
151 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
152 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
153 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
154 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
155 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
156 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
157 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
158 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
159 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
160 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
161 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
162 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
163 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
164 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
165 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
166 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
167 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
168 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
169 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
170 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
171 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
172 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
173 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
174 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
175 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
176 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
177 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
178 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
179 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
180 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
181 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
182 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
183 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
184 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
185 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
186 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
187 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
188 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
189 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
190 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
191 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
192 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
193 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
194 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
195 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
196 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
197 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
198 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
199 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
200 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
201 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
202 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
203 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
204 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
205 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
206 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
207 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
208 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
209 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
210 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
211 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
212 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
213 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
214 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
215 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
216 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
217 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
218 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
219 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
220 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
221 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
222 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
223 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
224 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
225 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
226 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
227 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
228 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
229 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
230 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
231 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
232 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
233 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
234 	IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
235 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
236 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
237 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
238 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
239 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
240 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
241 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
242 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
243 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
244 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
245 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
246 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
247 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
248 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
249 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
250 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
251 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
252 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
253 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
254 	IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
255 };
256 
257 #define BM_OBE_ENABLED		BIT(17)
258 #define BM_IBE_ENABLED		BIT(16)
259 #define BM_LK_ENABLED		BIT(15)
260 #define BM_MUX_MODE		0xf00
261 #define BP_MUX_MODE		8
262 #define BM_PULL_ENABLED		BIT(1)
263 
264 static const struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
265 	IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, 		BIT(6), 6),
266 	IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL,		BIT(5), 5),
267 	IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE,			BIT(2), 2),
268 	IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE,			BIT(1), 1),
269 	IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP,			BIT(0), 0),
270 
271 	IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN,	BIT(5), 5),
272 	IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN,		BIT(0), 0),
273 };
274 
275 static void imx7ulp_cfg_params_fixup(unsigned long *configs,
276 				    unsigned int num_configs,
277 				    u32 *raw_config)
278 {
279 	enum pin_config_param param;
280 	u32 param_val;
281 	int i;
282 
283 	/* lock field disabled */
284 	*raw_config &= ~BM_LK_ENABLED;
285 
286 	for (i = 0; i < num_configs; i++) {
287 		param = pinconf_to_config_param(configs[i]);
288 		param_val = pinconf_to_config_argument(configs[i]);
289 
290 		if ((param == PIN_CONFIG_BIAS_PULL_UP) ||
291 		    (param == PIN_CONFIG_BIAS_PULL_DOWN)) {
292 			/* pull enabled */
293 			*raw_config |= BM_PULL_ENABLED;
294 
295 			return;
296 		}
297 	}
298 }
299 
300 static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
301 					  struct pinctrl_gpio_range *range,
302 					  unsigned offset, bool input)
303 {
304 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
305 	const struct imx_pin_reg *pin_reg;
306 	u32 reg;
307 
308 	pin_reg = &ipctl->pin_regs[offset];
309 	if (pin_reg->mux_reg == -1)
310 		return -EINVAL;
311 
312 	reg = readl(ipctl->base + pin_reg->mux_reg);
313 	if (input)
314 		reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
315 	else
316 		reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
317 	writel(reg, ipctl->base + pin_reg->mux_reg);
318 
319 	return 0;
320 }
321 
322 static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
323 	.pins = imx7ulp_pinctrl_pads,
324 	.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
325 	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
326 	.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
327 	.mux_mask = BM_MUX_MODE,
328 	.mux_shift = BP_MUX_MODE,
329 	.generic_pinconf = true,
330 	.decodes = imx7ulp_cfg_decodes,
331 	.num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes),
332 	.fixup = imx7ulp_cfg_params_fixup,
333 };
334 
335 static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
336 	{ .compatible = "fsl,imx7ulp-iomuxc1", },
337 	{ /* sentinel */ }
338 };
339 
340 static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
341 {
342 	return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info);
343 }
344 
345 static struct platform_driver imx7ulp_pinctrl_driver = {
346 	.driver = {
347 		.name = "imx7ulp-pinctrl",
348 		.of_match_table = of_match_ptr(imx7ulp_pinctrl_of_match),
349 		.suppress_bind_attrs = true,
350 	},
351 	.probe = imx7ulp_pinctrl_probe,
352 };
353 
354 static int __init imx7ulp_pinctrl_init(void)
355 {
356 	return platform_driver_register(&imx7ulp_pinctrl_driver);
357 }
358 arch_initcall(imx7ulp_pinctrl_init);
359