1 /*
2  * imx50 pinctrl driver based on imx pinmux core
3  *
4  * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
5  * Copyright (C) 2012 Freescale Semiconductor, Inc.
6  * Copyright (C) 2012 Linaro, Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13 
14 #include <linux/err.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/pinctrl/pinctrl.h>
20 
21 #include "pinctrl-imx.h"
22 
23 enum imx50_pads {
24 	MX50_PAD_RESERVE0 = 0,
25 	MX50_PAD_RESERVE1 = 1,
26 	MX50_PAD_RESERVE2 = 2,
27 	MX50_PAD_RESERVE3 = 3,
28 	MX50_PAD_RESERVE4 = 4,
29 	MX50_PAD_RESERVE5 = 5,
30 	MX50_PAD_RESERVE6 = 6,
31 	MX50_PAD_RESERVE7 = 7,
32 	MX50_PAD_KEY_COL0 = 8,
33 	MX50_PAD_KEY_ROW0 = 9,
34 	MX50_PAD_KEY_COL1 = 10,
35 	MX50_PAD_KEY_ROW1 = 11,
36 	MX50_PAD_KEY_COL2 = 12,
37 	MX50_PAD_KEY_ROW2 = 13,
38 	MX50_PAD_KEY_COL3 = 14,
39 	MX50_PAD_KEY_ROW3 = 15,
40 	MX50_PAD_I2C1_SCL = 16,
41 	MX50_PAD_I2C1_SDA = 17,
42 	MX50_PAD_I2C2_SCL = 18,
43 	MX50_PAD_I2C2_SDA = 19,
44 	MX50_PAD_I2C3_SCL = 20,
45 	MX50_PAD_I2C3_SDA = 21,
46 	MX50_PAD_PWM1 = 22,
47 	MX50_PAD_PWM2 = 23,
48 	MX50_PAD_0WIRE = 24,
49 	MX50_PAD_EPITO = 25,
50 	MX50_PAD_WDOG = 26,
51 	MX50_PAD_SSI_TXFS = 27,
52 	MX50_PAD_SSI_TXC = 28,
53 	MX50_PAD_SSI_TXD = 29,
54 	MX50_PAD_SSI_RXD = 30,
55 	MX50_PAD_SSI_RXF = 31,
56 	MX50_PAD_SSI_RXC = 32,
57 	MX50_PAD_UART1_TXD = 33,
58 	MX50_PAD_UART1_RXD = 34,
59 	MX50_PAD_UART1_CTS = 35,
60 	MX50_PAD_UART1_RTS = 36,
61 	MX50_PAD_UART2_TXD = 37,
62 	MX50_PAD_UART2_RXD = 38,
63 	MX50_PAD_UART2_CTS = 39,
64 	MX50_PAD_UART2_RTS = 40,
65 	MX50_PAD_UART3_TXD = 41,
66 	MX50_PAD_UART3_RXD = 42,
67 	MX50_PAD_UART4_TXD = 43,
68 	MX50_PAD_UART4_RXD = 44,
69 	MX50_PAD_CSPI_CLK = 45,
70 	MX50_PAD_CSPI_MOSI = 46,
71 	MX50_PAD_CSPI_MISO = 47,
72 	MX50_PAD_CSPI_SS0 = 48,
73 	MX50_PAD_ECSPI1_CLK = 49,
74 	MX50_PAD_ECSPI1_MOSI = 50,
75 	MX50_PAD_ECSPI1_MISO = 51,
76 	MX50_PAD_ECSPI1_SS0 = 52,
77 	MX50_PAD_ECSPI2_CLK = 53,
78 	MX50_PAD_ECSPI2_MOSI = 54,
79 	MX50_PAD_ECSPI2_MISO = 55,
80 	MX50_PAD_ECSPI2_SS0 = 56,
81 	MX50_PAD_SD1_CLK = 57,
82 	MX50_PAD_SD1_CMD = 58,
83 	MX50_PAD_SD1_D0 = 59,
84 	MX50_PAD_SD1_D1 = 60,
85 	MX50_PAD_SD1_D2 = 61,
86 	MX50_PAD_SD1_D3 = 62,
87 	MX50_PAD_SD2_CLK = 63,
88 	MX50_PAD_SD2_CMD = 64,
89 	MX50_PAD_SD2_D0 = 65,
90 	MX50_PAD_SD2_D1 = 66,
91 	MX50_PAD_SD2_D2 = 67,
92 	MX50_PAD_SD2_D3 = 68,
93 	MX50_PAD_SD2_D4 = 69,
94 	MX50_PAD_SD2_D5 = 70,
95 	MX50_PAD_SD2_D6 = 71,
96 	MX50_PAD_SD2_D7 = 72,
97 	MX50_PAD_SD2_WP = 73,
98 	MX50_PAD_SD2_CD = 74,
99 	MX50_PAD_DISP_D0 = 75,
100 	MX50_PAD_DISP_D1 = 76,
101 	MX50_PAD_DISP_D2 = 77,
102 	MX50_PAD_DISP_D3 = 78,
103 	MX50_PAD_DISP_D4 = 79,
104 	MX50_PAD_DISP_D5 = 80,
105 	MX50_PAD_DISP_D6 = 81,
106 	MX50_PAD_DISP_D7 = 82,
107 	MX50_PAD_DISP_WR = 83,
108 	MX50_PAD_DISP_RD = 84,
109 	MX50_PAD_DISP_RS = 85,
110 	MX50_PAD_DISP_CS = 86,
111 	MX50_PAD_DISP_BUSY = 87,
112 	MX50_PAD_DISP_RESET = 88,
113 	MX50_PAD_SD3_CLK = 89,
114 	MX50_PAD_SD3_CMD = 90,
115 	MX50_PAD_SD3_D0 = 91,
116 	MX50_PAD_SD3_D1 = 92,
117 	MX50_PAD_SD3_D2 = 93,
118 	MX50_PAD_SD3_D3 = 94,
119 	MX50_PAD_SD3_D4 = 95,
120 	MX50_PAD_SD3_D5 = 96,
121 	MX50_PAD_SD3_D6 = 97,
122 	MX50_PAD_SD3_D7 = 98,
123 	MX50_PAD_SD3_WP = 99,
124 	MX50_PAD_DISP_D8 = 100,
125 	MX50_PAD_DISP_D9 = 101,
126 	MX50_PAD_DISP_D10 = 102,
127 	MX50_PAD_DISP_D11 = 103,
128 	MX50_PAD_DISP_D12 = 104,
129 	MX50_PAD_DISP_D13 = 105,
130 	MX50_PAD_DISP_D14 = 106,
131 	MX50_PAD_DISP_D15 = 107,
132 	MX50_PAD_EPDC_D0 = 108,
133 	MX50_PAD_EPDC_D1 = 109,
134 	MX50_PAD_EPDC_D2 = 110,
135 	MX50_PAD_EPDC_D3 = 111,
136 	MX50_PAD_EPDC_D4 = 112,
137 	MX50_PAD_EPDC_D5 = 113,
138 	MX50_PAD_EPDC_D6 = 114,
139 	MX50_PAD_EPDC_D7 = 115,
140 	MX50_PAD_EPDC_D8 = 116,
141 	MX50_PAD_EPDC_D9 = 117,
142 	MX50_PAD_EPDC_D10 = 118,
143 	MX50_PAD_EPDC_D11 = 119,
144 	MX50_PAD_EPDC_D12 = 120,
145 	MX50_PAD_EPDC_D13 = 121,
146 	MX50_PAD_EPDC_D14 = 122,
147 	MX50_PAD_EPDC_D15 = 123,
148 	MX50_PAD_EPDC_GDCLK = 124,
149 	MX50_PAD_EPDC_GDSP = 125,
150 	MX50_PAD_EPDC_GDOE = 126,
151 	MX50_PAD_EPDC_GDRL = 127,
152 	MX50_PAD_EPDC_SDCLK = 128,
153 	MX50_PAD_EPDC_SDOEZ = 129,
154 	MX50_PAD_EPDC_SDOED = 130,
155 	MX50_PAD_EPDC_SDOE = 131,
156 	MX50_PAD_EPDC_SDLE = 132,
157 	MX50_PAD_EPDC_SDCLKN = 133,
158 	MX50_PAD_EPDC_SDSHR = 134,
159 	MX50_PAD_EPDC_PWRCOM = 135,
160 	MX50_PAD_EPDC_PWRSTAT = 136,
161 	MX50_PAD_EPDC_PWRCTRL0 = 137,
162 	MX50_PAD_EPDC_PWRCTRL1 = 138,
163 	MX50_PAD_EPDC_PWRCTRL2 = 139,
164 	MX50_PAD_EPDC_PWRCTRL3 = 140,
165 	MX50_PAD_EPDC_VCOM0 = 141,
166 	MX50_PAD_EPDC_VCOM1 = 142,
167 	MX50_PAD_EPDC_BDR0 = 143,
168 	MX50_PAD_EPDC_BDR1 = 144,
169 	MX50_PAD_EPDC_SDCE0 = 145,
170 	MX50_PAD_EPDC_SDCE1 = 146,
171 	MX50_PAD_EPDC_SDCE2 = 147,
172 	MX50_PAD_EPDC_SDCE3 = 148,
173 	MX50_PAD_EPDC_SDCE4 = 149,
174 	MX50_PAD_EPDC_SDCE5 = 150,
175 	MX50_PAD_EIM_DA0 = 151,
176 	MX50_PAD_EIM_DA1 = 152,
177 	MX50_PAD_EIM_DA2 = 153,
178 	MX50_PAD_EIM_DA3 = 154,
179 	MX50_PAD_EIM_DA4 = 155,
180 	MX50_PAD_EIM_DA5 = 156,
181 	MX50_PAD_EIM_DA6 = 157,
182 	MX50_PAD_EIM_DA7 = 158,
183 	MX50_PAD_EIM_DA8 = 159,
184 	MX50_PAD_EIM_DA9 = 160,
185 	MX50_PAD_EIM_DA10 = 161,
186 	MX50_PAD_EIM_DA11 = 162,
187 	MX50_PAD_EIM_DA12 = 163,
188 	MX50_PAD_EIM_DA13 = 164,
189 	MX50_PAD_EIM_DA14 = 165,
190 	MX50_PAD_EIM_DA15 = 166,
191 	MX50_PAD_EIM_CS2 = 167,
192 	MX50_PAD_EIM_CS1 = 168,
193 	MX50_PAD_EIM_CS0 = 169,
194 	MX50_PAD_EIM_EB0 = 170,
195 	MX50_PAD_EIM_EB1 = 171,
196 	MX50_PAD_EIM_WAIT = 172,
197 	MX50_PAD_EIM_BCLK = 173,
198 	MX50_PAD_EIM_RDY = 174,
199 	MX50_PAD_EIM_OE = 175,
200 	MX50_PAD_EIM_RW = 176,
201 	MX50_PAD_EIM_LBA = 177,
202 	MX50_PAD_EIM_CRE = 178,
203 };
204 
205 /* Pad names for the pinmux subsystem */
206 static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
207 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
208 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
209 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
210 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
211 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
212 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
213 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
214 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
215 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
216 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
217 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
218 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
219 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
220 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
221 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
222 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
223 	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
224 	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
225 	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
226 	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
227 	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
228 	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
229 	IMX_PINCTRL_PIN(MX50_PAD_PWM1),
230 	IMX_PINCTRL_PIN(MX50_PAD_PWM2),
231 	IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
232 	IMX_PINCTRL_PIN(MX50_PAD_EPITO),
233 	IMX_PINCTRL_PIN(MX50_PAD_WDOG),
234 	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
235 	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
236 	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
237 	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
238 	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
239 	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
240 	IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
241 	IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
242 	IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
243 	IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
244 	IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
245 	IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
246 	IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
247 	IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
248 	IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
249 	IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
250 	IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
251 	IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
252 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
253 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
254 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
255 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
256 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
257 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
258 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
259 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
260 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
261 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
262 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
263 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
264 	IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
265 	IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
266 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
267 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
268 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
269 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
270 	IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
271 	IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
272 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
273 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
274 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
275 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
276 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
277 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
278 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
279 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
280 	IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
281 	IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
282 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
283 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
284 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
285 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
286 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
287 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
288 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
289 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
290 	IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
291 	IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
292 	IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
293 	IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
294 	IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
295 	IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
296 	IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
297 	IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
298 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
299 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
300 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
301 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
302 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
303 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
304 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
305 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
306 	IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
307 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
308 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
309 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
310 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
311 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
312 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
313 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
314 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
315 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
316 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
317 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
318 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
319 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
320 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
321 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
322 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
323 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
324 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
325 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
326 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
327 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
328 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
329 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
330 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
331 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
332 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
333 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
334 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
335 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
336 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
337 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
338 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
339 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
340 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
341 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
342 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
343 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
344 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
345 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
346 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
347 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
348 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
349 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
350 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
351 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
352 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
353 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
354 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
355 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
356 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
357 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
358 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
359 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
360 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
361 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
362 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
363 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
364 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
365 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
366 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
367 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
368 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
369 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
370 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
371 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
372 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
373 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
374 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
375 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
376 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
377 	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
378 	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
379 	IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
380 	IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
381 	IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
382 	IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
383 	IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
384 	IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
385 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
386 };
387 
388 static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
389 	.pins = imx50_pinctrl_pads,
390 	.npins = ARRAY_SIZE(imx50_pinctrl_pads),
391 	.gpr_compatible = "fsl,imx50-iomuxc-gpr",
392 };
393 
394 static const struct of_device_id imx50_pinctrl_of_match[] = {
395 	{ .compatible = "fsl,imx50-iomuxc", },
396 	{ /* sentinel */ }
397 };
398 
399 static int imx50_pinctrl_probe(struct platform_device *pdev)
400 {
401 	return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
402 }
403 
404 static struct platform_driver imx50_pinctrl_driver = {
405 	.driver = {
406 		.name = "imx50-pinctrl",
407 		.of_match_table = of_match_ptr(imx50_pinctrl_of_match),
408 	},
409 	.probe = imx50_pinctrl_probe,
410 };
411 
412 static int __init imx50_pinctrl_init(void)
413 {
414 	return platform_driver_register(&imx50_pinctrl_driver);
415 }
416 arch_initcall(imx50_pinctrl_init);
417