1edad3b2aSLinus Walleij /* 2edad3b2aSLinus Walleij * i.MX1 pinctrl driver based on imx pinmux core 3edad3b2aSLinus Walleij * 4edad3b2aSLinus Walleij * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 5edad3b2aSLinus Walleij * 6edad3b2aSLinus Walleij * This program is free software; you can redistribute it and/or modify 7edad3b2aSLinus Walleij * it under the terms of the GNU General Public License as published by 8edad3b2aSLinus Walleij * the Free Software Foundation; either version 2 of the License, or 9edad3b2aSLinus Walleij * (at your option) any later version. 10edad3b2aSLinus Walleij */ 11edad3b2aSLinus Walleij 12edad3b2aSLinus Walleij #include <linux/module.h> 13edad3b2aSLinus Walleij #include <linux/of.h> 14edad3b2aSLinus Walleij #include <linux/platform_device.h> 15edad3b2aSLinus Walleij #include <linux/pinctrl/pinctrl.h> 16edad3b2aSLinus Walleij 17edad3b2aSLinus Walleij #include "pinctrl-imx1.h" 18edad3b2aSLinus Walleij 19edad3b2aSLinus Walleij #define PAD_ID(port, pin) ((port) * 32 + (pin)) 20edad3b2aSLinus Walleij #define PA 0 21edad3b2aSLinus Walleij #define PB 1 22edad3b2aSLinus Walleij #define PC 2 23edad3b2aSLinus Walleij #define PD 3 24edad3b2aSLinus Walleij 25edad3b2aSLinus Walleij enum imx1_pads { 26edad3b2aSLinus Walleij MX1_PAD_A24 = PAD_ID(PA, 0), 27edad3b2aSLinus Walleij MX1_PAD_TIN = PAD_ID(PA, 1), 28edad3b2aSLinus Walleij MX1_PAD_PWMO = PAD_ID(PA, 2), 29edad3b2aSLinus Walleij MX1_PAD_CSI_MCLK = PAD_ID(PA, 3), 30edad3b2aSLinus Walleij MX1_PAD_CSI_D0 = PAD_ID(PA, 4), 31edad3b2aSLinus Walleij MX1_PAD_CSI_D1 = PAD_ID(PA, 5), 32edad3b2aSLinus Walleij MX1_PAD_CSI_D2 = PAD_ID(PA, 6), 33edad3b2aSLinus Walleij MX1_PAD_CSI_D3 = PAD_ID(PA, 7), 34edad3b2aSLinus Walleij MX1_PAD_CSI_D4 = PAD_ID(PA, 8), 35edad3b2aSLinus Walleij MX1_PAD_CSI_D5 = PAD_ID(PA, 9), 36edad3b2aSLinus Walleij MX1_PAD_CSI_D6 = PAD_ID(PA, 10), 37edad3b2aSLinus Walleij MX1_PAD_CSI_D7 = PAD_ID(PA, 11), 38edad3b2aSLinus Walleij MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12), 39edad3b2aSLinus Walleij MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13), 40edad3b2aSLinus Walleij MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14), 41edad3b2aSLinus Walleij MX1_PAD_I2C_SDA = PAD_ID(PA, 15), 42edad3b2aSLinus Walleij MX1_PAD_I2C_SCL = PAD_ID(PA, 16), 43edad3b2aSLinus Walleij MX1_PAD_DTACK = PAD_ID(PA, 17), 44edad3b2aSLinus Walleij MX1_PAD_BCLK = PAD_ID(PA, 18), 45edad3b2aSLinus Walleij MX1_PAD_LBA = PAD_ID(PA, 19), 46edad3b2aSLinus Walleij MX1_PAD_ECB = PAD_ID(PA, 20), 47edad3b2aSLinus Walleij MX1_PAD_A0 = PAD_ID(PA, 21), 48edad3b2aSLinus Walleij MX1_PAD_CS4 = PAD_ID(PA, 22), 49edad3b2aSLinus Walleij MX1_PAD_CS5 = PAD_ID(PA, 23), 50edad3b2aSLinus Walleij MX1_PAD_A16 = PAD_ID(PA, 24), 51edad3b2aSLinus Walleij MX1_PAD_A17 = PAD_ID(PA, 25), 52edad3b2aSLinus Walleij MX1_PAD_A18 = PAD_ID(PA, 26), 53edad3b2aSLinus Walleij MX1_PAD_A19 = PAD_ID(PA, 27), 54edad3b2aSLinus Walleij MX1_PAD_A20 = PAD_ID(PA, 28), 55edad3b2aSLinus Walleij MX1_PAD_A21 = PAD_ID(PA, 29), 56edad3b2aSLinus Walleij MX1_PAD_A22 = PAD_ID(PA, 30), 57edad3b2aSLinus Walleij MX1_PAD_A23 = PAD_ID(PA, 31), 58edad3b2aSLinus Walleij MX1_PAD_SD_DAT0 = PAD_ID(PB, 8), 59edad3b2aSLinus Walleij MX1_PAD_SD_DAT1 = PAD_ID(PB, 9), 60edad3b2aSLinus Walleij MX1_PAD_SD_DAT2 = PAD_ID(PB, 10), 61edad3b2aSLinus Walleij MX1_PAD_SD_DAT3 = PAD_ID(PB, 11), 62edad3b2aSLinus Walleij MX1_PAD_SD_SCLK = PAD_ID(PB, 12), 63edad3b2aSLinus Walleij MX1_PAD_SD_CMD = PAD_ID(PB, 13), 64edad3b2aSLinus Walleij MX1_PAD_SIM_SVEN = PAD_ID(PB, 14), 65edad3b2aSLinus Walleij MX1_PAD_SIM_PD = PAD_ID(PB, 15), 66edad3b2aSLinus Walleij MX1_PAD_SIM_TX = PAD_ID(PB, 16), 67edad3b2aSLinus Walleij MX1_PAD_SIM_RX = PAD_ID(PB, 17), 68edad3b2aSLinus Walleij MX1_PAD_SIM_RST = PAD_ID(PB, 18), 69edad3b2aSLinus Walleij MX1_PAD_SIM_CLK = PAD_ID(PB, 19), 70edad3b2aSLinus Walleij MX1_PAD_USBD_AFE = PAD_ID(PB, 20), 71edad3b2aSLinus Walleij MX1_PAD_USBD_OE = PAD_ID(PB, 21), 72edad3b2aSLinus Walleij MX1_PAD_USBD_RCV = PAD_ID(PB, 22), 73edad3b2aSLinus Walleij MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23), 74edad3b2aSLinus Walleij MX1_PAD_USBD_VP = PAD_ID(PB, 24), 75edad3b2aSLinus Walleij MX1_PAD_USBD_VM = PAD_ID(PB, 25), 76edad3b2aSLinus Walleij MX1_PAD_USBD_VPO = PAD_ID(PB, 26), 77edad3b2aSLinus Walleij MX1_PAD_USBD_VMO = PAD_ID(PB, 27), 78edad3b2aSLinus Walleij MX1_PAD_UART2_CTS = PAD_ID(PB, 28), 79edad3b2aSLinus Walleij MX1_PAD_UART2_RTS = PAD_ID(PB, 29), 80edad3b2aSLinus Walleij MX1_PAD_UART2_TXD = PAD_ID(PB, 30), 81edad3b2aSLinus Walleij MX1_PAD_UART2_RXD = PAD_ID(PB, 31), 82edad3b2aSLinus Walleij MX1_PAD_SSI_RXFS = PAD_ID(PC, 3), 83edad3b2aSLinus Walleij MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4), 84edad3b2aSLinus Walleij MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5), 85edad3b2aSLinus Walleij MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6), 86edad3b2aSLinus Walleij MX1_PAD_SSI_TXFS = PAD_ID(PC, 7), 87edad3b2aSLinus Walleij MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8), 88edad3b2aSLinus Walleij MX1_PAD_UART1_CTS = PAD_ID(PC, 9), 89edad3b2aSLinus Walleij MX1_PAD_UART1_RTS = PAD_ID(PC, 10), 90edad3b2aSLinus Walleij MX1_PAD_UART1_TXD = PAD_ID(PC, 11), 91edad3b2aSLinus Walleij MX1_PAD_UART1_RXD = PAD_ID(PC, 12), 92edad3b2aSLinus Walleij MX1_PAD_SPI1_RDY = PAD_ID(PC, 13), 93edad3b2aSLinus Walleij MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14), 94edad3b2aSLinus Walleij MX1_PAD_SPI1_SS = PAD_ID(PC, 15), 95edad3b2aSLinus Walleij MX1_PAD_SPI1_MISO = PAD_ID(PC, 16), 96edad3b2aSLinus Walleij MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17), 97edad3b2aSLinus Walleij MX1_PAD_BT13 = PAD_ID(PC, 19), 98edad3b2aSLinus Walleij MX1_PAD_BT12 = PAD_ID(PC, 20), 99edad3b2aSLinus Walleij MX1_PAD_BT11 = PAD_ID(PC, 21), 100edad3b2aSLinus Walleij MX1_PAD_BT10 = PAD_ID(PC, 22), 101edad3b2aSLinus Walleij MX1_PAD_BT9 = PAD_ID(PC, 23), 102edad3b2aSLinus Walleij MX1_PAD_BT8 = PAD_ID(PC, 24), 103edad3b2aSLinus Walleij MX1_PAD_BT7 = PAD_ID(PC, 25), 104edad3b2aSLinus Walleij MX1_PAD_BT6 = PAD_ID(PC, 26), 105edad3b2aSLinus Walleij MX1_PAD_BT5 = PAD_ID(PC, 27), 106edad3b2aSLinus Walleij MX1_PAD_BT4 = PAD_ID(PC, 28), 107edad3b2aSLinus Walleij MX1_PAD_BT3 = PAD_ID(PC, 29), 108edad3b2aSLinus Walleij MX1_PAD_BT2 = PAD_ID(PC, 30), 109edad3b2aSLinus Walleij MX1_PAD_BT1 = PAD_ID(PC, 31), 110edad3b2aSLinus Walleij MX1_PAD_LSCLK = PAD_ID(PD, 6), 111edad3b2aSLinus Walleij MX1_PAD_REV = PAD_ID(PD, 7), 112edad3b2aSLinus Walleij MX1_PAD_CLS = PAD_ID(PD, 8), 113edad3b2aSLinus Walleij MX1_PAD_PS = PAD_ID(PD, 9), 114edad3b2aSLinus Walleij MX1_PAD_SPL_SPR = PAD_ID(PD, 10), 115edad3b2aSLinus Walleij MX1_PAD_CONTRAST = PAD_ID(PD, 11), 116edad3b2aSLinus Walleij MX1_PAD_ACD_OE = PAD_ID(PD, 12), 117edad3b2aSLinus Walleij MX1_PAD_LP_HSYNC = PAD_ID(PD, 13), 118edad3b2aSLinus Walleij MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14), 119edad3b2aSLinus Walleij MX1_PAD_LD0 = PAD_ID(PD, 15), 120edad3b2aSLinus Walleij MX1_PAD_LD1 = PAD_ID(PD, 16), 121edad3b2aSLinus Walleij MX1_PAD_LD2 = PAD_ID(PD, 17), 122edad3b2aSLinus Walleij MX1_PAD_LD3 = PAD_ID(PD, 18), 123edad3b2aSLinus Walleij MX1_PAD_LD4 = PAD_ID(PD, 19), 124edad3b2aSLinus Walleij MX1_PAD_LD5 = PAD_ID(PD, 20), 125edad3b2aSLinus Walleij MX1_PAD_LD6 = PAD_ID(PD, 21), 126edad3b2aSLinus Walleij MX1_PAD_LD7 = PAD_ID(PD, 22), 127edad3b2aSLinus Walleij MX1_PAD_LD8 = PAD_ID(PD, 23), 128edad3b2aSLinus Walleij MX1_PAD_LD9 = PAD_ID(PD, 24), 129edad3b2aSLinus Walleij MX1_PAD_LD10 = PAD_ID(PD, 25), 130edad3b2aSLinus Walleij MX1_PAD_LD11 = PAD_ID(PD, 26), 131edad3b2aSLinus Walleij MX1_PAD_LD12 = PAD_ID(PD, 27), 132edad3b2aSLinus Walleij MX1_PAD_LD13 = PAD_ID(PD, 28), 133edad3b2aSLinus Walleij MX1_PAD_LD14 = PAD_ID(PD, 29), 134edad3b2aSLinus Walleij MX1_PAD_LD15 = PAD_ID(PD, 30), 135edad3b2aSLinus Walleij MX1_PAD_TMR2OUT = PAD_ID(PD, 31), 136edad3b2aSLinus Walleij }; 137edad3b2aSLinus Walleij 138edad3b2aSLinus Walleij /* Pad names for the pinmux subsystem */ 139edad3b2aSLinus Walleij static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = { 140edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A24), 141edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_TIN), 142edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_PWMO), 143edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK), 144edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D0), 145edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D1), 146edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D2), 147edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D3), 148edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D4), 149edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D5), 150edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D6), 151edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D7), 152edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC), 153edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC), 154edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK), 155edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA), 156edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL), 157edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_DTACK), 158edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BCLK), 159edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LBA), 160edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_ECB), 161edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A0), 162edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CS4), 163edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CS5), 164edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A16), 165edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A17), 166edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A18), 167edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A19), 168edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A20), 169edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A21), 170edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A22), 171edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A23), 172edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0), 173edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1), 174edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2), 175edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3), 176edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK), 177edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_CMD), 178edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN), 179edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_PD), 180edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_TX), 181edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_RX), 182edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK), 183edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE), 184edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_OE), 185edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV), 186edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND), 187edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VP), 188edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VM), 189edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO), 190edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO), 191edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS), 192edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS), 193edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD), 194edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD), 195edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS), 196edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK), 197edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT), 198edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT), 199edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS), 200edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK), 201edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS), 202edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS), 203edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD), 204edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD), 205edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY), 206edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK), 207edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS), 208edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO), 209edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI), 210edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT13), 211edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT12), 212edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT11), 213edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT10), 214edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT9), 215edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT8), 216edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT7), 217edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT6), 218edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT5), 219edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT4), 220edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT3), 221edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT2), 222edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT1), 223edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LSCLK), 224edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_REV), 225edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CLS), 226edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_PS), 227edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR), 228edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CONTRAST), 229edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_ACD_OE), 230edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC), 231edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC), 232edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD0), 233edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD1), 234edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD2), 235edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD3), 236edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD4), 237edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD5), 238edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD6), 239edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD7), 240edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD8), 241edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD9), 242edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD10), 243edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD11), 244edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD12), 245edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD13), 246edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD14), 247edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD15), 248edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT), 249edad3b2aSLinus Walleij }; 250edad3b2aSLinus Walleij 251edad3b2aSLinus Walleij static struct imx1_pinctrl_soc_info imx1_pinctrl_info = { 252edad3b2aSLinus Walleij .pins = imx1_pinctrl_pads, 253edad3b2aSLinus Walleij .npins = ARRAY_SIZE(imx1_pinctrl_pads), 254edad3b2aSLinus Walleij }; 255edad3b2aSLinus Walleij 256edad3b2aSLinus Walleij static int __init imx1_pinctrl_probe(struct platform_device *pdev) 257edad3b2aSLinus Walleij { 258edad3b2aSLinus Walleij return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info); 259edad3b2aSLinus Walleij } 260edad3b2aSLinus Walleij 261edad3b2aSLinus Walleij static const struct of_device_id imx1_pinctrl_of_match[] = { 262edad3b2aSLinus Walleij { .compatible = "fsl,imx1-iomuxc", }, 263edad3b2aSLinus Walleij { } 264edad3b2aSLinus Walleij }; 265edad3b2aSLinus Walleij MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match); 266edad3b2aSLinus Walleij 267edad3b2aSLinus Walleij static struct platform_driver imx1_pinctrl_driver = { 268edad3b2aSLinus Walleij .driver = { 269edad3b2aSLinus Walleij .name = "imx1-pinctrl", 270edad3b2aSLinus Walleij .owner = THIS_MODULE, 271edad3b2aSLinus Walleij .of_match_table = imx1_pinctrl_of_match, 272edad3b2aSLinus Walleij }, 273edad3b2aSLinus Walleij .remove = imx1_pinctrl_core_remove, 274edad3b2aSLinus Walleij }; 275edad3b2aSLinus Walleij module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe); 276edad3b2aSLinus Walleij 277edad3b2aSLinus Walleij MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 278edad3b2aSLinus Walleij MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver"); 279edad3b2aSLinus Walleij MODULE_LICENSE("GPL"); 280