1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * IMX pinmux core definitions 4 * 5 * Copyright (C) 2012 Freescale Semiconductor, Inc. 6 * Copyright (C) 2012 Linaro Ltd. 7 * 8 * Author: Dong Aisheng <dong.aisheng@linaro.org> 9 */ 10 11 #ifndef __DRIVERS_PINCTRL_IMX_H 12 #define __DRIVERS_PINCTRL_IMX_H 13 14 #include <linux/pinctrl/pinconf-generic.h> 15 #include <linux/pinctrl/pinmux.h> 16 17 struct platform_device; 18 19 extern struct pinmux_ops imx_pmx_ops; 20 21 /** 22 * struct imx_pin_mmio - MMIO pin configurations 23 * @mux_mode: the mux mode for this pin. 24 * @input_reg: the select input register offset for this pin if any 25 * 0 if no select input setting needed. 26 * @input_val: the select input value for this pin. 27 * @configs: the config for this pin. 28 */ 29 struct imx_pin_mmio { 30 unsigned int mux_mode; 31 u16 input_reg; 32 unsigned int input_val; 33 unsigned long config; 34 }; 35 36 /** 37 * struct imx_pin_scu - SCU pin configurations 38 * @mux: the mux mode for this pin. 39 * @configs: the config for this pin. 40 */ 41 struct imx_pin_scu { 42 unsigned int mux_mode; 43 unsigned long config; 44 }; 45 46 /** 47 * struct imx_pin - describes a single i.MX pin 48 * @pin: the pin_id of this pin 49 * @conf: config type of this pin, either mmio or scu 50 */ 51 struct imx_pin { 52 unsigned int pin; 53 union { 54 struct imx_pin_mmio mmio; 55 struct imx_pin_scu scu; 56 } conf; 57 }; 58 59 /** 60 * struct imx_pin_reg - describe a pin reg map 61 * @mux_reg: mux register offset 62 * @conf_reg: config register offset 63 */ 64 struct imx_pin_reg { 65 s16 mux_reg; 66 s16 conf_reg; 67 }; 68 69 /* decode a generic config into raw register value */ 70 struct imx_cfg_params_decode { 71 enum pin_config_param param; 72 u32 mask; 73 u8 shift; 74 bool invert; 75 }; 76 77 struct imx_pinctrl_soc_info { 78 const struct pinctrl_pin_desc *pins; 79 unsigned int npins; 80 unsigned int flags; 81 const char *gpr_compatible; 82 83 /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */ 84 unsigned int mux_mask; 85 u8 mux_shift; 86 87 /* generic pinconf */ 88 bool generic_pinconf; 89 const struct pinconf_generic_params *custom_params; 90 unsigned int num_custom_params; 91 const struct imx_cfg_params_decode *decodes; 92 unsigned int num_decodes; 93 void (*fixup)(unsigned long *configs, unsigned int num_configs, 94 u32 *raw_config); 95 96 int (*gpio_set_direction)(struct pinctrl_dev *pctldev, 97 struct pinctrl_gpio_range *range, 98 unsigned offset, 99 bool input); 100 }; 101 102 /** 103 * @dev: a pointer back to containing device 104 * @base: the offset to the controller in virtual memory 105 */ 106 struct imx_pinctrl { 107 struct device *dev; 108 struct pinctrl_dev *pctl; 109 void __iomem *base; 110 void __iomem *input_sel_base; 111 const struct imx_pinctrl_soc_info *info; 112 struct imx_pin_reg *pin_regs; 113 unsigned int group_index; 114 struct mutex mutex; 115 }; 116 117 #define IMX_CFG_PARAMS_DECODE(p, m, o) \ 118 { .param = p, .mask = m, .shift = o, .invert = false, } 119 120 #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ 121 { .param = p, .mask = m, .shift = o, .invert = true, } 122 123 #define SHARE_MUX_CONF_REG BIT(0) 124 #define ZERO_OFFSET_VALID BIT(1) 125 #define IMX_USE_SCU BIT(2) 126 127 #define NO_MUX 0x0 128 #define NO_PAD 0x0 129 130 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 131 132 #define PAD_CTL_MASK(len) ((1 << len) - 1) 133 #define IMX_MUX_MASK 0x7 134 #define IOMUXC_CONFIG_SION (0x1 << 4) 135 136 int imx_pinctrl_probe(struct platform_device *pdev, 137 const struct imx_pinctrl_soc_info *info); 138 139 #ifdef CONFIG_PINCTRL_IMX_SCU 140 #define BM_PAD_CTL_GP_ENABLE BIT(30) 141 #define BM_PAD_CTL_IFMUX_ENABLE BIT(31) 142 #define BP_PAD_CTL_IFMUX 27 143 144 int imx_pinctrl_sc_ipc_init(struct platform_device *pdev); 145 int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, 146 unsigned long *config); 147 int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, 148 unsigned long *configs, unsigned num_configs); 149 void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, 150 unsigned int *pin_id, struct imx_pin *pin, 151 const __be32 **list_p); 152 #else 153 static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, 154 unsigned pin_id, unsigned long *config) 155 { 156 return -EINVAL; 157 } 158 static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, 159 unsigned pin_id, unsigned long *configs, 160 unsigned num_configs) 161 { 162 return -EINVAL; 163 } 164 static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, 165 unsigned int *pin_id, 166 struct imx_pin *pin, 167 const __be32 **list_p) 168 { 169 } 170 #endif 171 #endif /* __DRIVERS_PINCTRL_IMX_H */ 172