1 /* 2 * IMX pinmux core definitions 3 * 4 * Copyright (C) 2012 Freescale Semiconductor, Inc. 5 * Copyright (C) 2012 Linaro Ltd. 6 * 7 * Author: Dong Aisheng <dong.aisheng@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef __DRIVERS_PINCTRL_IMX_H 16 #define __DRIVERS_PINCTRL_IMX_H 17 18 struct platform_device; 19 20 /** 21 * struct imx_pin - describes a single i.MX pin 22 * @pin: the pin_id of this pin 23 * @mux_mode: the mux mode for this pin. 24 * @input_reg: the select input register offset for this pin if any 25 * 0 if no select input setting needed. 26 * @input_val: the select input value for this pin. 27 * @configs: the config for this pin. 28 */ 29 struct imx_pin { 30 unsigned int pin; 31 unsigned int mux_mode; 32 u16 input_reg; 33 unsigned int input_val; 34 unsigned long config; 35 }; 36 37 /** 38 * struct imx_pin_reg - describe a pin reg map 39 * @mux_reg: mux register offset 40 * @conf_reg: config register offset 41 */ 42 struct imx_pin_reg { 43 s16 mux_reg; 44 s16 conf_reg; 45 }; 46 47 struct imx_pinctrl_soc_info { 48 struct device *dev; 49 const struct pinctrl_pin_desc *pins; 50 unsigned int npins; 51 struct imx_pin_reg *pin_regs; 52 unsigned int group_index; 53 unsigned int flags; 54 const char *gpr_compatible; 55 struct mutex mutex; 56 }; 57 58 #define SHARE_MUX_CONF_REG 0x1 59 #define ZERO_OFFSET_VALID 0x2 60 61 #define NO_MUX 0x0 62 #define NO_PAD 0x0 63 64 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 65 66 #define PAD_CTL_MASK(len) ((1 << len) - 1) 67 #define IMX_MUX_MASK 0x7 68 #define IOMUXC_CONFIG_SION (0x1 << 4) 69 70 int imx_pinctrl_probe(struct platform_device *pdev, 71 struct imx_pinctrl_soc_info *info); 72 #endif /* __DRIVERS_PINCTRL_IMX_H */ 73