1 /* 2 * Core driver for the imx pin controller 3 * 4 * Copyright (C) 2012 Freescale Semiconductor, Inc. 5 * Copyright (C) 2012 Linaro Ltd. 6 * 7 * Author: Dong Aisheng <dong.aisheng@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/err.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_address.h> 22 #include <linux/pinctrl/machine.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/slab.h> 27 #include <linux/regmap.h> 28 29 #include "../core.h" 30 #include "../pinconf.h" 31 #include "../pinmux.h" 32 #include "pinctrl-imx.h" 33 34 /* The bits in CONFIG cell defined in binding doc*/ 35 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 36 #define IMX_PAD_SION 0x40000000 /* set SION */ 37 38 /** 39 * @dev: a pointer back to containing device 40 * @base: the offset to the controller in virtual memory 41 */ 42 struct imx_pinctrl { 43 struct device *dev; 44 struct pinctrl_dev *pctl; 45 void __iomem *base; 46 void __iomem *input_sel_base; 47 struct imx_pinctrl_soc_info *info; 48 }; 49 50 static inline const struct group_desc *imx_pinctrl_find_group_by_name( 51 struct pinctrl_dev *pctldev, 52 const char *name) 53 { 54 const struct group_desc *grp = NULL; 55 int i; 56 57 for (i = 0; i < pctldev->num_groups; i++) { 58 grp = pinctrl_generic_get_group(pctldev, i); 59 if (grp && !strcmp(grp->name, name)) 60 break; 61 } 62 63 return grp; 64 } 65 66 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 67 unsigned offset) 68 { 69 seq_printf(s, "%s", dev_name(pctldev->dev)); 70 } 71 72 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 73 struct device_node *np, 74 struct pinctrl_map **map, unsigned *num_maps) 75 { 76 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 77 struct imx_pinctrl_soc_info *info = ipctl->info; 78 const struct group_desc *grp; 79 struct pinctrl_map *new_map; 80 struct device_node *parent; 81 int map_num = 1; 82 int i, j; 83 84 /* 85 * first find the group of this node and check if we need create 86 * config maps for pins 87 */ 88 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); 89 if (!grp) { 90 dev_err(info->dev, "unable to find group for node %s\n", 91 np->name); 92 return -EINVAL; 93 } 94 95 for (i = 0; i < grp->num_pins; i++) { 96 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 97 98 if (!(pin->config & IMX_NO_PAD_CTL)) 99 map_num++; 100 } 101 102 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); 103 if (!new_map) 104 return -ENOMEM; 105 106 *map = new_map; 107 *num_maps = map_num; 108 109 /* create mux map */ 110 parent = of_get_parent(np); 111 if (!parent) { 112 kfree(new_map); 113 return -EINVAL; 114 } 115 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 116 new_map[0].data.mux.function = parent->name; 117 new_map[0].data.mux.group = np->name; 118 of_node_put(parent); 119 120 /* create config map */ 121 new_map++; 122 for (i = j = 0; i < grp->num_pins; i++) { 123 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 124 125 if (!(pin->config & IMX_NO_PAD_CTL)) { 126 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 127 new_map[j].data.configs.group_or_pin = 128 pin_get_name(pctldev, pin->pin); 129 new_map[j].data.configs.configs = &pin->config; 130 new_map[j].data.configs.num_configs = 1; 131 j++; 132 } 133 } 134 135 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 136 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 137 138 return 0; 139 } 140 141 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 142 struct pinctrl_map *map, unsigned num_maps) 143 { 144 kfree(map); 145 } 146 147 static const struct pinctrl_ops imx_pctrl_ops = { 148 .get_groups_count = pinctrl_generic_get_group_count, 149 .get_group_name = pinctrl_generic_get_group_name, 150 .get_group_pins = pinctrl_generic_get_group_pins, 151 .pin_dbg_show = imx_pin_dbg_show, 152 .dt_node_to_map = imx_dt_node_to_map, 153 .dt_free_map = imx_dt_free_map, 154 155 }; 156 157 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 158 unsigned group) 159 { 160 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 161 struct imx_pinctrl_soc_info *info = ipctl->info; 162 const struct imx_pin_reg *pin_reg; 163 unsigned int npins, pin_id; 164 int i; 165 struct group_desc *grp = NULL; 166 struct function_desc *func = NULL; 167 168 /* 169 * Configure the mux mode for each pin in the group for a specific 170 * function. 171 */ 172 grp = pinctrl_generic_get_group(pctldev, group); 173 if (!grp) 174 return -EINVAL; 175 176 func = pinmux_generic_get_function(pctldev, selector); 177 if (!func) 178 return -EINVAL; 179 180 npins = grp->num_pins; 181 182 dev_dbg(ipctl->dev, "enable function %s group %s\n", 183 func->name, grp->name); 184 185 for (i = 0; i < npins; i++) { 186 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 187 188 pin_id = pin->pin; 189 pin_reg = &info->pin_regs[pin_id]; 190 191 if (pin_reg->mux_reg == -1) { 192 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", 193 info->pins[pin_id].name); 194 continue; 195 } 196 197 if (info->flags & SHARE_MUX_CONF_REG) { 198 u32 reg; 199 reg = readl(ipctl->base + pin_reg->mux_reg); 200 reg &= ~info->mux_mask; 201 reg |= (pin->mux_mode << info->mux_shift); 202 writel(reg, ipctl->base + pin_reg->mux_reg); 203 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 204 pin_reg->mux_reg, reg); 205 } else { 206 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); 207 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 208 pin_reg->mux_reg, pin->mux_mode); 209 } 210 211 /* 212 * If the select input value begins with 0xff, it's a quirky 213 * select input and the value should be interpreted as below. 214 * 31 23 15 7 0 215 * | 0xff | shift | width | select | 216 * It's used to work around the problem that the select 217 * input for some pin is not implemented in the select 218 * input register but in some general purpose register. 219 * We encode the select input value, width and shift of 220 * the bit field into input_val cell of pin function ID 221 * in device tree, and then decode them here for setting 222 * up the select input bits in general purpose register. 223 */ 224 if (pin->input_val >> 24 == 0xff) { 225 u32 val = pin->input_val; 226 u8 select = val & 0xff; 227 u8 width = (val >> 8) & 0xff; 228 u8 shift = (val >> 16) & 0xff; 229 u32 mask = ((1 << width) - 1) << shift; 230 /* 231 * The input_reg[i] here is actually some IOMUXC general 232 * purpose register, not regular select input register. 233 */ 234 val = readl(ipctl->base + pin->input_reg); 235 val &= ~mask; 236 val |= select << shift; 237 writel(val, ipctl->base + pin->input_reg); 238 } else if (pin->input_reg) { 239 /* 240 * Regular select input register can never be at offset 241 * 0, and we only print register value for regular case. 242 */ 243 if (ipctl->input_sel_base) 244 writel(pin->input_val, ipctl->input_sel_base + 245 pin->input_reg); 246 else 247 writel(pin->input_val, ipctl->base + 248 pin->input_reg); 249 dev_dbg(ipctl->dev, 250 "==>select_input: offset 0x%x val 0x%x\n", 251 pin->input_reg, pin->input_val); 252 } 253 } 254 255 return 0; 256 } 257 258 static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 259 struct pinctrl_gpio_range *range, unsigned offset) 260 { 261 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 262 struct imx_pinctrl_soc_info *info = ipctl->info; 263 const struct imx_pin_reg *pin_reg; 264 struct group_desc *grp; 265 struct imx_pin *imx_pin; 266 unsigned int pin, group; 267 u32 reg; 268 269 /* Currently implementation only for shared mux/conf register */ 270 if (!(info->flags & SHARE_MUX_CONF_REG)) 271 return 0; 272 273 pin_reg = &info->pin_regs[offset]; 274 if (pin_reg->mux_reg == -1) 275 return -EINVAL; 276 277 /* Find the pinctrl config with GPIO mux mode for the requested pin */ 278 for (group = 0; group < pctldev->num_groups; group++) { 279 grp = pinctrl_generic_get_group(pctldev, group); 280 if (!grp) 281 continue; 282 for (pin = 0; pin < grp->num_pins; pin++) { 283 imx_pin = &((struct imx_pin *)(grp->data))[pin]; 284 if (imx_pin->pin == offset && !imx_pin->mux_mode) 285 goto mux_pin; 286 } 287 } 288 289 return -EINVAL; 290 291 mux_pin: 292 reg = readl(ipctl->base + pin_reg->mux_reg); 293 reg &= ~info->mux_mask; 294 reg |= imx_pin->config; 295 writel(reg, ipctl->base + pin_reg->mux_reg); 296 297 return 0; 298 } 299 300 static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 301 struct pinctrl_gpio_range *range, unsigned offset) 302 { 303 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 304 struct imx_pinctrl_soc_info *info = ipctl->info; 305 const struct imx_pin_reg *pin_reg; 306 u32 reg; 307 308 /* 309 * Only Vybrid has the input/output buffer enable flags (IBE/OBE) 310 * They are part of the shared mux/conf register. 311 */ 312 if (!(info->flags & SHARE_MUX_CONF_REG)) 313 return; 314 315 pin_reg = &info->pin_regs[offset]; 316 if (pin_reg->mux_reg == -1) 317 return; 318 319 /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */ 320 reg = readl(ipctl->base + pin_reg->mux_reg); 321 reg &= ~0x7; 322 writel(reg, ipctl->base + pin_reg->mux_reg); 323 } 324 325 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 326 struct pinctrl_gpio_range *range, unsigned offset, bool input) 327 { 328 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 329 struct imx_pinctrl_soc_info *info = ipctl->info; 330 const struct imx_pin_reg *pin_reg; 331 u32 reg; 332 333 /* 334 * Only Vybrid has the input/output buffer enable flags (IBE/OBE) 335 * They are part of the shared mux/conf register. 336 */ 337 if (!(info->flags & SHARE_MUX_CONF_REG)) 338 return 0; 339 340 pin_reg = &info->pin_regs[offset]; 341 if (pin_reg->mux_reg == -1) 342 return -EINVAL; 343 344 /* IBE always enabled allows us to read the value "on the wire" */ 345 reg = readl(ipctl->base + pin_reg->mux_reg); 346 if (input) 347 reg &= ~0x2; 348 else 349 reg |= 0x2; 350 writel(reg, ipctl->base + pin_reg->mux_reg); 351 352 return 0; 353 } 354 355 static const struct pinmux_ops imx_pmx_ops = { 356 .get_functions_count = pinmux_generic_get_function_count, 357 .get_function_name = pinmux_generic_get_function_name, 358 .get_function_groups = pinmux_generic_get_function_groups, 359 .set_mux = imx_pmx_set, 360 .gpio_request_enable = imx_pmx_gpio_request_enable, 361 .gpio_disable_free = imx_pmx_gpio_disable_free, 362 .gpio_set_direction = imx_pmx_gpio_set_direction, 363 }; 364 365 /* decode generic config into raw register values */ 366 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, 367 unsigned long *configs, 368 unsigned int num_configs) 369 { 370 struct imx_pinctrl_soc_info *info = ipctl->info; 371 struct imx_cfg_params_decode *decode; 372 enum pin_config_param param; 373 u32 raw_config = 0; 374 u32 param_val; 375 int i, j; 376 377 WARN_ON(num_configs > info->num_decodes); 378 379 for (i = 0; i < num_configs; i++) { 380 param = pinconf_to_config_param(configs[i]); 381 param_val = pinconf_to_config_argument(configs[i]); 382 decode = info->decodes; 383 for (j = 0; j < info->num_decodes; j++) { 384 if (param == decode->param) { 385 if (decode->invert) 386 param_val = !param_val; 387 raw_config |= (param_val << decode->shift) 388 & decode->mask; 389 break; 390 } 391 decode++; 392 } 393 } 394 395 if (info->fixup) 396 info->fixup(configs, num_configs, &raw_config); 397 398 return raw_config; 399 } 400 401 static u32 imx_pinconf_parse_generic_config(struct device_node *np, 402 struct imx_pinctrl *ipctl) 403 { 404 struct imx_pinctrl_soc_info *info = ipctl->info; 405 struct pinctrl_dev *pctl = ipctl->pctl; 406 unsigned int num_configs; 407 unsigned long *configs; 408 int ret; 409 410 if (!info->generic_pinconf) 411 return 0; 412 413 ret = pinconf_generic_parse_dt_config(np, pctl, &configs, 414 &num_configs); 415 if (ret) 416 return 0; 417 418 return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); 419 } 420 421 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 422 unsigned pin_id, unsigned long *config) 423 { 424 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 425 struct imx_pinctrl_soc_info *info = ipctl->info; 426 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 427 428 if (pin_reg->conf_reg == -1) { 429 dev_err(info->dev, "Pin(%s) does not support config function\n", 430 info->pins[pin_id].name); 431 return -EINVAL; 432 } 433 434 *config = readl(ipctl->base + pin_reg->conf_reg); 435 436 if (info->flags & SHARE_MUX_CONF_REG) 437 *config &= ~info->mux_mask; 438 439 return 0; 440 } 441 442 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 443 unsigned pin_id, unsigned long *configs, 444 unsigned num_configs) 445 { 446 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 447 struct imx_pinctrl_soc_info *info = ipctl->info; 448 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 449 int i; 450 451 if (pin_reg->conf_reg == -1) { 452 dev_err(info->dev, "Pin(%s) does not support config function\n", 453 info->pins[pin_id].name); 454 return -EINVAL; 455 } 456 457 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 458 info->pins[pin_id].name); 459 460 for (i = 0; i < num_configs; i++) { 461 if (info->flags & SHARE_MUX_CONF_REG) { 462 u32 reg; 463 reg = readl(ipctl->base + pin_reg->conf_reg); 464 reg &= info->mux_mask; 465 reg |= configs[i]; 466 writel(reg, ipctl->base + pin_reg->conf_reg); 467 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 468 pin_reg->conf_reg, reg); 469 } else { 470 writel(configs[i], ipctl->base + pin_reg->conf_reg); 471 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 472 pin_reg->conf_reg, configs[i]); 473 } 474 } /* for each config */ 475 476 return 0; 477 } 478 479 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 480 struct seq_file *s, unsigned pin_id) 481 { 482 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 483 struct imx_pinctrl_soc_info *info = ipctl->info; 484 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 485 unsigned long config; 486 487 if (!pin_reg || pin_reg->conf_reg == -1) { 488 seq_printf(s, "N/A"); 489 return; 490 } 491 492 config = readl(ipctl->base + pin_reg->conf_reg); 493 seq_printf(s, "0x%lx", config); 494 } 495 496 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 497 struct seq_file *s, unsigned group) 498 { 499 struct group_desc *grp; 500 unsigned long config; 501 const char *name; 502 int i, ret; 503 504 if (group > pctldev->num_groups) 505 return; 506 507 seq_printf(s, "\n"); 508 grp = pinctrl_generic_get_group(pctldev, group); 509 if (!grp) 510 return; 511 512 for (i = 0; i < grp->num_pins; i++) { 513 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 514 515 name = pin_get_name(pctldev, pin->pin); 516 ret = imx_pinconf_get(pctldev, pin->pin, &config); 517 if (ret) 518 return; 519 seq_printf(s, " %s: 0x%lx\n", name, config); 520 } 521 } 522 523 static const struct pinconf_ops imx_pinconf_ops = { 524 .pin_config_get = imx_pinconf_get, 525 .pin_config_set = imx_pinconf_set, 526 .pin_config_dbg_show = imx_pinconf_dbg_show, 527 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 528 }; 529 530 /* 531 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and 532 * 1 u32 CONFIG, so 24 types in total for each pin. 533 */ 534 #define FSL_PIN_SIZE 24 535 #define SHARE_FSL_PIN_SIZE 20 536 537 static int imx_pinctrl_parse_groups(struct device_node *np, 538 struct group_desc *grp, 539 struct imx_pinctrl *ipctl, 540 u32 index) 541 { 542 struct imx_pinctrl_soc_info *info = ipctl->info; 543 int size, pin_size; 544 const __be32 *list; 545 int i; 546 u32 config; 547 548 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 549 550 if (info->flags & SHARE_MUX_CONF_REG) 551 pin_size = SHARE_FSL_PIN_SIZE; 552 else 553 pin_size = FSL_PIN_SIZE; 554 555 if (info->generic_pinconf) 556 pin_size -= 4; 557 558 /* Initialise group */ 559 grp->name = np->name; 560 561 /* 562 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 563 * do sanity check and calculate pins number 564 * 565 * First try legacy 'fsl,pins' property, then fall back to the 566 * generic 'pins'. 567 * 568 * Note: for generic 'pins' case, there's no CONFIG part in 569 * the binding format. 570 */ 571 list = of_get_property(np, "fsl,pins", &size); 572 if (!list) { 573 list = of_get_property(np, "pins", &size); 574 if (!list) { 575 dev_err(info->dev, 576 "no fsl,pins and pins property in node %s\n", 577 np->full_name); 578 return -EINVAL; 579 } 580 } 581 582 /* we do not check return since it's safe node passed down */ 583 if (!size || size % pin_size) { 584 dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n", 585 np->full_name); 586 return -EINVAL; 587 } 588 589 /* first try to parse the generic pin config */ 590 config = imx_pinconf_parse_generic_config(np, ipctl); 591 592 grp->num_pins = size / pin_size; 593 grp->data = devm_kzalloc(info->dev, grp->num_pins * 594 sizeof(struct imx_pin), GFP_KERNEL); 595 grp->pins = devm_kzalloc(info->dev, grp->num_pins * 596 sizeof(unsigned int), GFP_KERNEL); 597 if (!grp->pins || !grp->data) 598 return -ENOMEM; 599 600 for (i = 0; i < grp->num_pins; i++) { 601 u32 mux_reg = be32_to_cpu(*list++); 602 u32 conf_reg; 603 unsigned int pin_id; 604 struct imx_pin_reg *pin_reg; 605 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 606 607 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 608 mux_reg = -1; 609 610 if (info->flags & SHARE_MUX_CONF_REG) { 611 conf_reg = mux_reg; 612 } else { 613 conf_reg = be32_to_cpu(*list++); 614 if (!conf_reg) 615 conf_reg = -1; 616 } 617 618 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 619 pin_reg = &info->pin_regs[pin_id]; 620 pin->pin = pin_id; 621 grp->pins[i] = pin_id; 622 pin_reg->mux_reg = mux_reg; 623 pin_reg->conf_reg = conf_reg; 624 pin->input_reg = be32_to_cpu(*list++); 625 pin->mux_mode = be32_to_cpu(*list++); 626 pin->input_val = be32_to_cpu(*list++); 627 628 if (info->generic_pinconf) { 629 /* generic pin config decoded */ 630 pin->config = config; 631 } else { 632 /* legacy pin config read from devicetree */ 633 config = be32_to_cpu(*list++); 634 635 /* SION bit is in mux register */ 636 if (config & IMX_PAD_SION) 637 pin->mux_mode |= IOMUXC_CONFIG_SION; 638 pin->config = config & ~IMX_PAD_SION; 639 } 640 641 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, 642 pin->mux_mode, pin->config); 643 } 644 645 return 0; 646 } 647 648 static int imx_pinctrl_parse_functions(struct device_node *np, 649 struct imx_pinctrl *ipctl, 650 u32 index) 651 { 652 struct pinctrl_dev *pctl = ipctl->pctl; 653 struct imx_pinctrl_soc_info *info = ipctl->info; 654 struct device_node *child; 655 struct function_desc *func; 656 struct group_desc *grp; 657 u32 i = 0; 658 659 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 660 661 func = pinmux_generic_get_function(pctl, index); 662 if (!func) 663 return -EINVAL; 664 665 /* Initialise function */ 666 func->name = np->name; 667 func->num_group_names = of_get_child_count(np); 668 if (func->num_group_names == 0) { 669 dev_err(info->dev, "no groups defined in %s\n", np->full_name); 670 return -EINVAL; 671 } 672 func->group_names = devm_kcalloc(info->dev, func->num_group_names, 673 sizeof(char *), GFP_KERNEL); 674 if (!func->group_names) 675 return -ENOMEM; 676 677 for_each_child_of_node(np, child) { 678 func->group_names[i] = child->name; 679 680 grp = devm_kzalloc(info->dev, sizeof(struct group_desc), 681 GFP_KERNEL); 682 if (!grp) 683 return -ENOMEM; 684 685 mutex_lock(&info->mutex); 686 radix_tree_insert(&pctl->pin_group_tree, 687 info->group_index++, grp); 688 mutex_unlock(&info->mutex); 689 690 imx_pinctrl_parse_groups(child, grp, ipctl, i++); 691 } 692 693 return 0; 694 } 695 696 /* 697 * Check if the DT contains pins in the direct child nodes. This indicates the 698 * newer DT format to store pins. This function returns true if the first found 699 * fsl,pins property is in a child of np. Otherwise false is returned. 700 */ 701 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 702 { 703 struct device_node *function_np; 704 struct device_node *pinctrl_np; 705 706 for_each_child_of_node(np, function_np) { 707 if (of_property_read_bool(function_np, "fsl,pins")) 708 return true; 709 710 for_each_child_of_node(function_np, pinctrl_np) { 711 if (of_property_read_bool(pinctrl_np, "fsl,pins")) 712 return false; 713 } 714 } 715 716 return true; 717 } 718 719 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 720 struct imx_pinctrl *ipctl) 721 { 722 struct device_node *np = pdev->dev.of_node; 723 struct device_node *child; 724 struct pinctrl_dev *pctl = ipctl->pctl; 725 struct imx_pinctrl_soc_info *info = ipctl->info; 726 u32 nfuncs = 0; 727 u32 i = 0; 728 bool flat_funcs; 729 730 if (!np) 731 return -ENODEV; 732 733 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 734 if (flat_funcs) { 735 nfuncs = 1; 736 } else { 737 nfuncs = of_get_child_count(np); 738 if (nfuncs <= 0) { 739 dev_err(&pdev->dev, "no functions defined\n"); 740 return -EINVAL; 741 } 742 } 743 744 for (i = 0; i < nfuncs; i++) { 745 struct function_desc *function; 746 747 function = devm_kzalloc(&pdev->dev, sizeof(*function), 748 GFP_KERNEL); 749 if (!function) 750 return -ENOMEM; 751 752 mutex_lock(&info->mutex); 753 radix_tree_insert(&pctl->pin_function_tree, i, function); 754 mutex_unlock(&info->mutex); 755 } 756 pctl->num_functions = nfuncs; 757 758 info->group_index = 0; 759 if (flat_funcs) { 760 pctl->num_groups = of_get_child_count(np); 761 } else { 762 pctl->num_groups = 0; 763 for_each_child_of_node(np, child) 764 pctl->num_groups += of_get_child_count(child); 765 } 766 767 if (flat_funcs) { 768 imx_pinctrl_parse_functions(np, ipctl, 0); 769 } else { 770 i = 0; 771 for_each_child_of_node(np, child) 772 imx_pinctrl_parse_functions(child, ipctl, i++); 773 } 774 775 return 0; 776 } 777 778 /* 779 * imx_free_resources() - free memory used by this driver 780 * @info: info driver instance 781 */ 782 static void imx_free_resources(struct imx_pinctrl *ipctl) 783 { 784 if (ipctl->pctl) 785 pinctrl_unregister(ipctl->pctl); 786 } 787 788 int imx_pinctrl_probe(struct platform_device *pdev, 789 struct imx_pinctrl_soc_info *info) 790 { 791 struct regmap_config config = { .name = "gpr" }; 792 struct device_node *dev_np = pdev->dev.of_node; 793 struct pinctrl_desc *imx_pinctrl_desc; 794 struct device_node *np; 795 struct imx_pinctrl *ipctl; 796 struct resource *res; 797 struct regmap *gpr; 798 int ret, i; 799 800 if (!info || !info->pins || !info->npins) { 801 dev_err(&pdev->dev, "wrong pinctrl info\n"); 802 return -EINVAL; 803 } 804 info->dev = &pdev->dev; 805 806 if (info->gpr_compatible) { 807 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); 808 if (!IS_ERR(gpr)) 809 regmap_attach_dev(&pdev->dev, gpr, &config); 810 } 811 812 /* Create state holders etc for this driver */ 813 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 814 if (!ipctl) 815 return -ENOMEM; 816 817 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * 818 info->npins, GFP_KERNEL); 819 if (!info->pin_regs) 820 return -ENOMEM; 821 822 for (i = 0; i < info->npins; i++) { 823 info->pin_regs[i].mux_reg = -1; 824 info->pin_regs[i].conf_reg = -1; 825 } 826 827 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 828 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 829 if (IS_ERR(ipctl->base)) 830 return PTR_ERR(ipctl->base); 831 832 if (of_property_read_bool(dev_np, "fsl,input-sel")) { 833 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); 834 if (!np) { 835 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); 836 return -EINVAL; 837 } 838 839 ipctl->input_sel_base = of_iomap(np, 0); 840 of_node_put(np); 841 if (!ipctl->input_sel_base) { 842 dev_err(&pdev->dev, 843 "iomuxc input select base address not found\n"); 844 return -ENOMEM; 845 } 846 } 847 848 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), 849 GFP_KERNEL); 850 if (!imx_pinctrl_desc) 851 return -ENOMEM; 852 853 imx_pinctrl_desc->name = dev_name(&pdev->dev); 854 imx_pinctrl_desc->pins = info->pins; 855 imx_pinctrl_desc->npins = info->npins; 856 imx_pinctrl_desc->pctlops = &imx_pctrl_ops; 857 imx_pinctrl_desc->pmxops = &imx_pmx_ops; 858 imx_pinctrl_desc->confops = &imx_pinconf_ops; 859 imx_pinctrl_desc->owner = THIS_MODULE; 860 861 /* for generic pinconf */ 862 imx_pinctrl_desc->custom_params = info->custom_params; 863 imx_pinctrl_desc->num_custom_params = info->num_custom_params; 864 865 mutex_init(&info->mutex); 866 867 ipctl->info = info; 868 ipctl->dev = info->dev; 869 platform_set_drvdata(pdev, ipctl); 870 ret = devm_pinctrl_register_and_init(&pdev->dev, 871 imx_pinctrl_desc, ipctl, 872 &ipctl->pctl); 873 if (ret) { 874 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 875 goto free; 876 } 877 878 ret = imx_pinctrl_probe_dt(pdev, ipctl); 879 if (ret) { 880 dev_err(&pdev->dev, "fail to probe dt properties\n"); 881 goto free; 882 } 883 884 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 885 886 return pinctrl_enable(ipctl->pctl); 887 888 free: 889 imx_free_resources(ipctl); 890 891 return ret; 892 } 893