1 /* 2 * Core driver for the imx pin controller 3 * 4 * Copyright (C) 2012 Freescale Semiconductor, Inc. 5 * Copyright (C) 2012 Linaro Ltd. 6 * 7 * Author: Dong Aisheng <dong.aisheng@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/err.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_address.h> 22 #include <linux/pinctrl/machine.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/slab.h> 27 #include <linux/regmap.h> 28 29 #include "../core.h" 30 #include "../pinconf.h" 31 #include "../pinmux.h" 32 #include "pinctrl-imx.h" 33 34 /* The bits in CONFIG cell defined in binding doc*/ 35 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 36 #define IMX_PAD_SION 0x40000000 /* set SION */ 37 38 static inline const struct group_desc *imx_pinctrl_find_group_by_name( 39 struct pinctrl_dev *pctldev, 40 const char *name) 41 { 42 const struct group_desc *grp = NULL; 43 int i; 44 45 for (i = 0; i < pctldev->num_groups; i++) { 46 grp = pinctrl_generic_get_group(pctldev, i); 47 if (grp && !strcmp(grp->name, name)) 48 break; 49 } 50 51 return grp; 52 } 53 54 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 55 unsigned offset) 56 { 57 seq_printf(s, "%s", dev_name(pctldev->dev)); 58 } 59 60 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 61 struct device_node *np, 62 struct pinctrl_map **map, unsigned *num_maps) 63 { 64 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 65 struct imx_pinctrl_soc_info *info = ipctl->info; 66 const struct group_desc *grp; 67 struct pinctrl_map *new_map; 68 struct device_node *parent; 69 int map_num = 1; 70 int i, j; 71 72 /* 73 * first find the group of this node and check if we need create 74 * config maps for pins 75 */ 76 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); 77 if (!grp) { 78 dev_err(info->dev, "unable to find group for node %s\n", 79 np->name); 80 return -EINVAL; 81 } 82 83 for (i = 0; i < grp->num_pins; i++) { 84 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 85 86 if (!(pin->config & IMX_NO_PAD_CTL)) 87 map_num++; 88 } 89 90 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); 91 if (!new_map) 92 return -ENOMEM; 93 94 *map = new_map; 95 *num_maps = map_num; 96 97 /* create mux map */ 98 parent = of_get_parent(np); 99 if (!parent) { 100 kfree(new_map); 101 return -EINVAL; 102 } 103 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 104 new_map[0].data.mux.function = parent->name; 105 new_map[0].data.mux.group = np->name; 106 of_node_put(parent); 107 108 /* create config map */ 109 new_map++; 110 for (i = j = 0; i < grp->num_pins; i++) { 111 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 112 113 if (!(pin->config & IMX_NO_PAD_CTL)) { 114 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 115 new_map[j].data.configs.group_or_pin = 116 pin_get_name(pctldev, pin->pin); 117 new_map[j].data.configs.configs = &pin->config; 118 new_map[j].data.configs.num_configs = 1; 119 j++; 120 } 121 } 122 123 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 124 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 125 126 return 0; 127 } 128 129 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 130 struct pinctrl_map *map, unsigned num_maps) 131 { 132 kfree(map); 133 } 134 135 static const struct pinctrl_ops imx_pctrl_ops = { 136 .get_groups_count = pinctrl_generic_get_group_count, 137 .get_group_name = pinctrl_generic_get_group_name, 138 .get_group_pins = pinctrl_generic_get_group_pins, 139 .pin_dbg_show = imx_pin_dbg_show, 140 .dt_node_to_map = imx_dt_node_to_map, 141 .dt_free_map = imx_dt_free_map, 142 143 }; 144 145 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 146 unsigned group) 147 { 148 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 149 struct imx_pinctrl_soc_info *info = ipctl->info; 150 const struct imx_pin_reg *pin_reg; 151 unsigned int npins, pin_id; 152 int i; 153 struct group_desc *grp = NULL; 154 struct function_desc *func = NULL; 155 156 /* 157 * Configure the mux mode for each pin in the group for a specific 158 * function. 159 */ 160 grp = pinctrl_generic_get_group(pctldev, group); 161 if (!grp) 162 return -EINVAL; 163 164 func = pinmux_generic_get_function(pctldev, selector); 165 if (!func) 166 return -EINVAL; 167 168 npins = grp->num_pins; 169 170 dev_dbg(ipctl->dev, "enable function %s group %s\n", 171 func->name, grp->name); 172 173 for (i = 0; i < npins; i++) { 174 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 175 176 pin_id = pin->pin; 177 pin_reg = &info->pin_regs[pin_id]; 178 179 if (pin_reg->mux_reg == -1) { 180 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", 181 info->pins[pin_id].name); 182 continue; 183 } 184 185 if (info->flags & SHARE_MUX_CONF_REG) { 186 u32 reg; 187 reg = readl(ipctl->base + pin_reg->mux_reg); 188 reg &= ~info->mux_mask; 189 reg |= (pin->mux_mode << info->mux_shift); 190 writel(reg, ipctl->base + pin_reg->mux_reg); 191 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 192 pin_reg->mux_reg, reg); 193 } else { 194 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); 195 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 196 pin_reg->mux_reg, pin->mux_mode); 197 } 198 199 /* 200 * If the select input value begins with 0xff, it's a quirky 201 * select input and the value should be interpreted as below. 202 * 31 23 15 7 0 203 * | 0xff | shift | width | select | 204 * It's used to work around the problem that the select 205 * input for some pin is not implemented in the select 206 * input register but in some general purpose register. 207 * We encode the select input value, width and shift of 208 * the bit field into input_val cell of pin function ID 209 * in device tree, and then decode them here for setting 210 * up the select input bits in general purpose register. 211 */ 212 if (pin->input_val >> 24 == 0xff) { 213 u32 val = pin->input_val; 214 u8 select = val & 0xff; 215 u8 width = (val >> 8) & 0xff; 216 u8 shift = (val >> 16) & 0xff; 217 u32 mask = ((1 << width) - 1) << shift; 218 /* 219 * The input_reg[i] here is actually some IOMUXC general 220 * purpose register, not regular select input register. 221 */ 222 val = readl(ipctl->base + pin->input_reg); 223 val &= ~mask; 224 val |= select << shift; 225 writel(val, ipctl->base + pin->input_reg); 226 } else if (pin->input_reg) { 227 /* 228 * Regular select input register can never be at offset 229 * 0, and we only print register value for regular case. 230 */ 231 if (ipctl->input_sel_base) 232 writel(pin->input_val, ipctl->input_sel_base + 233 pin->input_reg); 234 else 235 writel(pin->input_val, ipctl->base + 236 pin->input_reg); 237 dev_dbg(ipctl->dev, 238 "==>select_input: offset 0x%x val 0x%x\n", 239 pin->input_reg, pin->input_val); 240 } 241 } 242 243 return 0; 244 } 245 246 struct pinmux_ops imx_pmx_ops = { 247 .get_functions_count = pinmux_generic_get_function_count, 248 .get_function_name = pinmux_generic_get_function_name, 249 .get_function_groups = pinmux_generic_get_function_groups, 250 .set_mux = imx_pmx_set, 251 }; 252 253 /* decode generic config into raw register values */ 254 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, 255 unsigned long *configs, 256 unsigned int num_configs) 257 { 258 struct imx_pinctrl_soc_info *info = ipctl->info; 259 struct imx_cfg_params_decode *decode; 260 enum pin_config_param param; 261 u32 raw_config = 0; 262 u32 param_val; 263 int i, j; 264 265 WARN_ON(num_configs > info->num_decodes); 266 267 for (i = 0; i < num_configs; i++) { 268 param = pinconf_to_config_param(configs[i]); 269 param_val = pinconf_to_config_argument(configs[i]); 270 decode = info->decodes; 271 for (j = 0; j < info->num_decodes; j++) { 272 if (param == decode->param) { 273 if (decode->invert) 274 param_val = !param_val; 275 raw_config |= (param_val << decode->shift) 276 & decode->mask; 277 break; 278 } 279 decode++; 280 } 281 } 282 283 if (info->fixup) 284 info->fixup(configs, num_configs, &raw_config); 285 286 return raw_config; 287 } 288 289 static u32 imx_pinconf_parse_generic_config(struct device_node *np, 290 struct imx_pinctrl *ipctl) 291 { 292 struct imx_pinctrl_soc_info *info = ipctl->info; 293 struct pinctrl_dev *pctl = ipctl->pctl; 294 unsigned int num_configs; 295 unsigned long *configs; 296 int ret; 297 298 if (!info->generic_pinconf) 299 return 0; 300 301 ret = pinconf_generic_parse_dt_config(np, pctl, &configs, 302 &num_configs); 303 if (ret) 304 return 0; 305 306 return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); 307 } 308 309 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 310 unsigned pin_id, unsigned long *config) 311 { 312 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 313 struct imx_pinctrl_soc_info *info = ipctl->info; 314 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 315 316 if (pin_reg->conf_reg == -1) { 317 dev_err(info->dev, "Pin(%s) does not support config function\n", 318 info->pins[pin_id].name); 319 return -EINVAL; 320 } 321 322 *config = readl(ipctl->base + pin_reg->conf_reg); 323 324 if (info->flags & SHARE_MUX_CONF_REG) 325 *config &= ~info->mux_mask; 326 327 return 0; 328 } 329 330 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 331 unsigned pin_id, unsigned long *configs, 332 unsigned num_configs) 333 { 334 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 335 struct imx_pinctrl_soc_info *info = ipctl->info; 336 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 337 int i; 338 339 if (pin_reg->conf_reg == -1) { 340 dev_err(info->dev, "Pin(%s) does not support config function\n", 341 info->pins[pin_id].name); 342 return -EINVAL; 343 } 344 345 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 346 info->pins[pin_id].name); 347 348 for (i = 0; i < num_configs; i++) { 349 if (info->flags & SHARE_MUX_CONF_REG) { 350 u32 reg; 351 reg = readl(ipctl->base + pin_reg->conf_reg); 352 reg &= info->mux_mask; 353 reg |= configs[i]; 354 writel(reg, ipctl->base + pin_reg->conf_reg); 355 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 356 pin_reg->conf_reg, reg); 357 } else { 358 writel(configs[i], ipctl->base + pin_reg->conf_reg); 359 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 360 pin_reg->conf_reg, configs[i]); 361 } 362 } /* for each config */ 363 364 return 0; 365 } 366 367 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 368 struct seq_file *s, unsigned pin_id) 369 { 370 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 371 struct imx_pinctrl_soc_info *info = ipctl->info; 372 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 373 unsigned long config; 374 375 if (!pin_reg || pin_reg->conf_reg == -1) { 376 seq_printf(s, "N/A"); 377 return; 378 } 379 380 config = readl(ipctl->base + pin_reg->conf_reg); 381 seq_printf(s, "0x%lx", config); 382 } 383 384 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 385 struct seq_file *s, unsigned group) 386 { 387 struct group_desc *grp; 388 unsigned long config; 389 const char *name; 390 int i, ret; 391 392 if (group > pctldev->num_groups) 393 return; 394 395 seq_printf(s, "\n"); 396 grp = pinctrl_generic_get_group(pctldev, group); 397 if (!grp) 398 return; 399 400 for (i = 0; i < grp->num_pins; i++) { 401 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 402 403 name = pin_get_name(pctldev, pin->pin); 404 ret = imx_pinconf_get(pctldev, pin->pin, &config); 405 if (ret) 406 return; 407 seq_printf(s, " %s: 0x%lx\n", name, config); 408 } 409 } 410 411 static const struct pinconf_ops imx_pinconf_ops = { 412 .pin_config_get = imx_pinconf_get, 413 .pin_config_set = imx_pinconf_set, 414 .pin_config_dbg_show = imx_pinconf_dbg_show, 415 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 416 }; 417 418 /* 419 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and 420 * 1 u32 CONFIG, so 24 types in total for each pin. 421 */ 422 #define FSL_PIN_SIZE 24 423 #define SHARE_FSL_PIN_SIZE 20 424 425 static int imx_pinctrl_parse_groups(struct device_node *np, 426 struct group_desc *grp, 427 struct imx_pinctrl *ipctl, 428 u32 index) 429 { 430 struct imx_pinctrl_soc_info *info = ipctl->info; 431 int size, pin_size; 432 const __be32 *list; 433 int i; 434 u32 config; 435 436 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 437 438 if (info->flags & SHARE_MUX_CONF_REG) 439 pin_size = SHARE_FSL_PIN_SIZE; 440 else 441 pin_size = FSL_PIN_SIZE; 442 443 if (info->generic_pinconf) 444 pin_size -= 4; 445 446 /* Initialise group */ 447 grp->name = np->name; 448 449 /* 450 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 451 * do sanity check and calculate pins number 452 * 453 * First try legacy 'fsl,pins' property, then fall back to the 454 * generic 'pinmux'. 455 * 456 * Note: for generic 'pinmux' case, there's no CONFIG part in 457 * the binding format. 458 */ 459 list = of_get_property(np, "fsl,pins", &size); 460 if (!list) { 461 list = of_get_property(np, "pinmux", &size); 462 if (!list) { 463 dev_err(info->dev, 464 "no fsl,pins and pins property in node %pOF\n", np); 465 return -EINVAL; 466 } 467 } 468 469 /* we do not check return since it's safe node passed down */ 470 if (!size || size % pin_size) { 471 dev_err(info->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); 472 return -EINVAL; 473 } 474 475 /* first try to parse the generic pin config */ 476 config = imx_pinconf_parse_generic_config(np, ipctl); 477 478 grp->num_pins = size / pin_size; 479 grp->data = devm_kzalloc(info->dev, grp->num_pins * 480 sizeof(struct imx_pin), GFP_KERNEL); 481 grp->pins = devm_kzalloc(info->dev, grp->num_pins * 482 sizeof(unsigned int), GFP_KERNEL); 483 if (!grp->pins || !grp->data) 484 return -ENOMEM; 485 486 for (i = 0; i < grp->num_pins; i++) { 487 u32 mux_reg = be32_to_cpu(*list++); 488 u32 conf_reg; 489 unsigned int pin_id; 490 struct imx_pin_reg *pin_reg; 491 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 492 493 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 494 mux_reg = -1; 495 496 if (info->flags & SHARE_MUX_CONF_REG) { 497 conf_reg = mux_reg; 498 } else { 499 conf_reg = be32_to_cpu(*list++); 500 if (!conf_reg) 501 conf_reg = -1; 502 } 503 504 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 505 pin_reg = &info->pin_regs[pin_id]; 506 pin->pin = pin_id; 507 grp->pins[i] = pin_id; 508 pin_reg->mux_reg = mux_reg; 509 pin_reg->conf_reg = conf_reg; 510 pin->input_reg = be32_to_cpu(*list++); 511 pin->mux_mode = be32_to_cpu(*list++); 512 pin->input_val = be32_to_cpu(*list++); 513 514 if (info->generic_pinconf) { 515 /* generic pin config decoded */ 516 pin->config = config; 517 } else { 518 /* legacy pin config read from devicetree */ 519 config = be32_to_cpu(*list++); 520 521 /* SION bit is in mux register */ 522 if (config & IMX_PAD_SION) 523 pin->mux_mode |= IOMUXC_CONFIG_SION; 524 pin->config = config & ~IMX_PAD_SION; 525 } 526 527 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, 528 pin->mux_mode, pin->config); 529 } 530 531 return 0; 532 } 533 534 static int imx_pinctrl_parse_functions(struct device_node *np, 535 struct imx_pinctrl *ipctl, 536 u32 index) 537 { 538 struct pinctrl_dev *pctl = ipctl->pctl; 539 struct imx_pinctrl_soc_info *info = ipctl->info; 540 struct device_node *child; 541 struct function_desc *func; 542 struct group_desc *grp; 543 u32 i = 0; 544 545 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 546 547 func = pinmux_generic_get_function(pctl, index); 548 if (!func) 549 return -EINVAL; 550 551 /* Initialise function */ 552 func->name = np->name; 553 func->num_group_names = of_get_child_count(np); 554 if (func->num_group_names == 0) { 555 dev_err(info->dev, "no groups defined in %pOF\n", np); 556 return -EINVAL; 557 } 558 func->group_names = devm_kcalloc(info->dev, func->num_group_names, 559 sizeof(char *), GFP_KERNEL); 560 if (!func->group_names) 561 return -ENOMEM; 562 563 for_each_child_of_node(np, child) { 564 func->group_names[i] = child->name; 565 566 grp = devm_kzalloc(info->dev, sizeof(struct group_desc), 567 GFP_KERNEL); 568 if (!grp) 569 return -ENOMEM; 570 571 mutex_lock(&info->mutex); 572 radix_tree_insert(&pctl->pin_group_tree, 573 info->group_index++, grp); 574 mutex_unlock(&info->mutex); 575 576 imx_pinctrl_parse_groups(child, grp, ipctl, i++); 577 } 578 579 return 0; 580 } 581 582 /* 583 * Check if the DT contains pins in the direct child nodes. This indicates the 584 * newer DT format to store pins. This function returns true if the first found 585 * fsl,pins property is in a child of np. Otherwise false is returned. 586 */ 587 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 588 { 589 struct device_node *function_np; 590 struct device_node *pinctrl_np; 591 592 for_each_child_of_node(np, function_np) { 593 if (of_property_read_bool(function_np, "fsl,pins")) 594 return true; 595 596 for_each_child_of_node(function_np, pinctrl_np) { 597 if (of_property_read_bool(pinctrl_np, "fsl,pins")) 598 return false; 599 } 600 } 601 602 return true; 603 } 604 605 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 606 struct imx_pinctrl *ipctl) 607 { 608 struct device_node *np = pdev->dev.of_node; 609 struct device_node *child; 610 struct pinctrl_dev *pctl = ipctl->pctl; 611 struct imx_pinctrl_soc_info *info = ipctl->info; 612 u32 nfuncs = 0; 613 u32 i = 0; 614 bool flat_funcs; 615 616 if (!np) 617 return -ENODEV; 618 619 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 620 if (flat_funcs) { 621 nfuncs = 1; 622 } else { 623 nfuncs = of_get_child_count(np); 624 if (nfuncs <= 0) { 625 dev_err(&pdev->dev, "no functions defined\n"); 626 return -EINVAL; 627 } 628 } 629 630 for (i = 0; i < nfuncs; i++) { 631 struct function_desc *function; 632 633 function = devm_kzalloc(&pdev->dev, sizeof(*function), 634 GFP_KERNEL); 635 if (!function) 636 return -ENOMEM; 637 638 mutex_lock(&info->mutex); 639 radix_tree_insert(&pctl->pin_function_tree, i, function); 640 mutex_unlock(&info->mutex); 641 } 642 pctl->num_functions = nfuncs; 643 644 info->group_index = 0; 645 if (flat_funcs) { 646 pctl->num_groups = of_get_child_count(np); 647 } else { 648 pctl->num_groups = 0; 649 for_each_child_of_node(np, child) 650 pctl->num_groups += of_get_child_count(child); 651 } 652 653 if (flat_funcs) { 654 imx_pinctrl_parse_functions(np, ipctl, 0); 655 } else { 656 i = 0; 657 for_each_child_of_node(np, child) 658 imx_pinctrl_parse_functions(child, ipctl, i++); 659 } 660 661 return 0; 662 } 663 664 /* 665 * imx_free_resources() - free memory used by this driver 666 * @info: info driver instance 667 */ 668 static void imx_free_resources(struct imx_pinctrl *ipctl) 669 { 670 if (ipctl->pctl) 671 pinctrl_unregister(ipctl->pctl); 672 } 673 674 int imx_pinctrl_probe(struct platform_device *pdev, 675 struct imx_pinctrl_soc_info *info) 676 { 677 struct regmap_config config = { .name = "gpr" }; 678 struct device_node *dev_np = pdev->dev.of_node; 679 struct pinctrl_desc *imx_pinctrl_desc; 680 struct device_node *np; 681 struct imx_pinctrl *ipctl; 682 struct resource *res; 683 struct regmap *gpr; 684 int ret, i; 685 686 if (!info || !info->pins || !info->npins) { 687 dev_err(&pdev->dev, "wrong pinctrl info\n"); 688 return -EINVAL; 689 } 690 info->dev = &pdev->dev; 691 692 if (info->gpr_compatible) { 693 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); 694 if (!IS_ERR(gpr)) 695 regmap_attach_dev(&pdev->dev, gpr, &config); 696 } 697 698 /* Create state holders etc for this driver */ 699 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 700 if (!ipctl) 701 return -ENOMEM; 702 703 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * 704 info->npins, GFP_KERNEL); 705 if (!info->pin_regs) 706 return -ENOMEM; 707 708 for (i = 0; i < info->npins; i++) { 709 info->pin_regs[i].mux_reg = -1; 710 info->pin_regs[i].conf_reg = -1; 711 } 712 713 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 714 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 715 if (IS_ERR(ipctl->base)) 716 return PTR_ERR(ipctl->base); 717 718 if (of_property_read_bool(dev_np, "fsl,input-sel")) { 719 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); 720 if (!np) { 721 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); 722 return -EINVAL; 723 } 724 725 ipctl->input_sel_base = of_iomap(np, 0); 726 of_node_put(np); 727 if (!ipctl->input_sel_base) { 728 dev_err(&pdev->dev, 729 "iomuxc input select base address not found\n"); 730 return -ENOMEM; 731 } 732 } 733 734 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), 735 GFP_KERNEL); 736 if (!imx_pinctrl_desc) 737 return -ENOMEM; 738 739 imx_pinctrl_desc->name = dev_name(&pdev->dev); 740 imx_pinctrl_desc->pins = info->pins; 741 imx_pinctrl_desc->npins = info->npins; 742 imx_pinctrl_desc->pctlops = &imx_pctrl_ops; 743 imx_pinctrl_desc->pmxops = &imx_pmx_ops; 744 imx_pinctrl_desc->confops = &imx_pinconf_ops; 745 imx_pinctrl_desc->owner = THIS_MODULE; 746 747 /* for generic pinconf */ 748 imx_pinctrl_desc->custom_params = info->custom_params; 749 imx_pinctrl_desc->num_custom_params = info->num_custom_params; 750 751 /* platform specific callback */ 752 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; 753 754 mutex_init(&info->mutex); 755 756 ipctl->info = info; 757 ipctl->dev = info->dev; 758 platform_set_drvdata(pdev, ipctl); 759 ret = devm_pinctrl_register_and_init(&pdev->dev, 760 imx_pinctrl_desc, ipctl, 761 &ipctl->pctl); 762 if (ret) { 763 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 764 goto free; 765 } 766 767 ret = imx_pinctrl_probe_dt(pdev, ipctl); 768 if (ret) { 769 dev_err(&pdev->dev, "fail to probe dt properties\n"); 770 goto free; 771 } 772 773 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 774 775 return pinctrl_enable(ipctl->pctl); 776 777 free: 778 imx_free_resources(ipctl); 779 780 return ret; 781 } 782