1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Core driver for the imx pin controller 4 // 5 // Copyright (C) 2012 Freescale Semiconductor, Inc. 6 // Copyright (C) 2012 Linaro Ltd. 7 // 8 // Author: Dong Aisheng <dong.aisheng@linaro.org> 9 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/pinctrl/machine.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinctrl.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/slab.h> 22 #include <linux/regmap.h> 23 24 #include "../core.h" 25 #include "../pinconf.h" 26 #include "../pinmux.h" 27 #include "pinctrl-imx.h" 28 29 /* The bits in CONFIG cell defined in binding doc*/ 30 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 31 #define IMX_PAD_SION 0x40000000 /* set SION */ 32 33 static inline const struct group_desc *imx_pinctrl_find_group_by_name( 34 struct pinctrl_dev *pctldev, 35 const char *name) 36 { 37 const struct group_desc *grp = NULL; 38 int i; 39 40 for (i = 0; i < pctldev->num_groups; i++) { 41 grp = pinctrl_generic_get_group(pctldev, i); 42 if (grp && !strcmp(grp->name, name)) 43 break; 44 } 45 46 return grp; 47 } 48 49 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 50 unsigned offset) 51 { 52 seq_printf(s, "%s", dev_name(pctldev->dev)); 53 } 54 55 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 56 struct device_node *np, 57 struct pinctrl_map **map, unsigned *num_maps) 58 { 59 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 60 const struct imx_pinctrl_soc_info *info = ipctl->info; 61 const struct group_desc *grp; 62 struct pinctrl_map *new_map; 63 struct device_node *parent; 64 struct imx_pin *pin; 65 int map_num = 1; 66 int i, j; 67 68 /* 69 * first find the group of this node and check if we need create 70 * config maps for pins 71 */ 72 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); 73 if (!grp) { 74 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); 75 return -EINVAL; 76 } 77 78 if (info->flags & IMX_USE_SCU) { 79 map_num += grp->num_pins; 80 } else { 81 for (i = 0; i < grp->num_pins; i++) { 82 pin = &((struct imx_pin *)(grp->data))[i]; 83 if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) 84 map_num++; 85 } 86 } 87 88 new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), 89 GFP_KERNEL); 90 if (!new_map) 91 return -ENOMEM; 92 93 *map = new_map; 94 *num_maps = map_num; 95 96 /* create mux map */ 97 parent = of_get_parent(np); 98 if (!parent) { 99 kfree(new_map); 100 return -EINVAL; 101 } 102 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 103 new_map[0].data.mux.function = parent->name; 104 new_map[0].data.mux.group = np->name; 105 of_node_put(parent); 106 107 /* create config map */ 108 new_map++; 109 for (i = j = 0; i < grp->num_pins; i++) { 110 pin = &((struct imx_pin *)(grp->data))[i]; 111 112 /* 113 * We only create config maps for SCU pads or MMIO pads that 114 * are not using the default config(a.k.a IMX_NO_PAD_CTL) 115 */ 116 if (!(info->flags & IMX_USE_SCU) && 117 (pin->conf.mmio.config & IMX_NO_PAD_CTL)) 118 continue; 119 120 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 121 new_map[j].data.configs.group_or_pin = 122 pin_get_name(pctldev, pin->pin); 123 124 if (info->flags & IMX_USE_SCU) { 125 /* 126 * For SCU case, we set mux and conf together 127 * in one IPC call 128 */ 129 new_map[j].data.configs.configs = 130 (unsigned long *)&pin->conf.scu; 131 new_map[j].data.configs.num_configs = 2; 132 } else { 133 new_map[j].data.configs.configs = 134 &pin->conf.mmio.config; 135 new_map[j].data.configs.num_configs = 1; 136 } 137 138 j++; 139 } 140 141 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 142 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 143 144 return 0; 145 } 146 147 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 148 struct pinctrl_map *map, unsigned num_maps) 149 { 150 kfree(map); 151 } 152 153 static const struct pinctrl_ops imx_pctrl_ops = { 154 .get_groups_count = pinctrl_generic_get_group_count, 155 .get_group_name = pinctrl_generic_get_group_name, 156 .get_group_pins = pinctrl_generic_get_group_pins, 157 .pin_dbg_show = imx_pin_dbg_show, 158 .dt_node_to_map = imx_dt_node_to_map, 159 .dt_free_map = imx_dt_free_map, 160 }; 161 162 static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, 163 struct imx_pin *pin) 164 { 165 const struct imx_pinctrl_soc_info *info = ipctl->info; 166 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 167 const struct imx_pin_reg *pin_reg; 168 unsigned int pin_id; 169 170 pin_id = pin->pin; 171 pin_reg = &ipctl->pin_regs[pin_id]; 172 173 if (pin_reg->mux_reg == -1) { 174 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", 175 info->pins[pin_id].name); 176 return 0; 177 } 178 179 if (info->flags & SHARE_MUX_CONF_REG) { 180 u32 reg; 181 182 reg = readl(ipctl->base + pin_reg->mux_reg); 183 reg &= ~info->mux_mask; 184 reg |= (pin_mmio->mux_mode << info->mux_shift); 185 writel(reg, ipctl->base + pin_reg->mux_reg); 186 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 187 pin_reg->mux_reg, reg); 188 } else { 189 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); 190 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 191 pin_reg->mux_reg, pin_mmio->mux_mode); 192 } 193 194 /* 195 * If the select input value begins with 0xff, it's a quirky 196 * select input and the value should be interpreted as below. 197 * 31 23 15 7 0 198 * | 0xff | shift | width | select | 199 * It's used to work around the problem that the select 200 * input for some pin is not implemented in the select 201 * input register but in some general purpose register. 202 * We encode the select input value, width and shift of 203 * the bit field into input_val cell of pin function ID 204 * in device tree, and then decode them here for setting 205 * up the select input bits in general purpose register. 206 */ 207 if (pin_mmio->input_val >> 24 == 0xff) { 208 u32 val = pin_mmio->input_val; 209 u8 select = val & 0xff; 210 u8 width = (val >> 8) & 0xff; 211 u8 shift = (val >> 16) & 0xff; 212 u32 mask = ((1 << width) - 1) << shift; 213 /* 214 * The input_reg[i] here is actually some IOMUXC general 215 * purpose register, not regular select input register. 216 */ 217 val = readl(ipctl->base + pin_mmio->input_reg); 218 val &= ~mask; 219 val |= select << shift; 220 writel(val, ipctl->base + pin_mmio->input_reg); 221 } else if (pin_mmio->input_reg) { 222 /* 223 * Regular select input register can never be at offset 224 * 0, and we only print register value for regular case. 225 */ 226 if (ipctl->input_sel_base) 227 writel(pin_mmio->input_val, ipctl->input_sel_base + 228 pin_mmio->input_reg); 229 else 230 writel(pin_mmio->input_val, ipctl->base + 231 pin_mmio->input_reg); 232 dev_dbg(ipctl->dev, 233 "==>select_input: offset 0x%x val 0x%x\n", 234 pin_mmio->input_reg, pin_mmio->input_val); 235 } 236 237 return 0; 238 } 239 240 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 241 unsigned group) 242 { 243 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 244 const struct imx_pinctrl_soc_info *info = ipctl->info; 245 struct function_desc *func; 246 struct group_desc *grp; 247 struct imx_pin *pin; 248 unsigned int npins; 249 int i, err; 250 251 /* 252 * Configure the mux mode for each pin in the group for a specific 253 * function. 254 */ 255 grp = pinctrl_generic_get_group(pctldev, group); 256 if (!grp) 257 return -EINVAL; 258 259 func = pinmux_generic_get_function(pctldev, selector); 260 if (!func) 261 return -EINVAL; 262 263 npins = grp->num_pins; 264 265 dev_dbg(ipctl->dev, "enable function %s group %s\n", 266 func->name, grp->name); 267 268 for (i = 0; i < npins; i++) { 269 /* 270 * For IMX_USE_SCU case, we postpone the mux setting 271 * until config is set as we can set them together 272 * in one IPC call 273 */ 274 pin = &((struct imx_pin *)(grp->data))[i]; 275 if (!(info->flags & IMX_USE_SCU)) { 276 err = imx_pmx_set_one_pin_mmio(ipctl, pin); 277 if (err) 278 return err; 279 } 280 } 281 282 return 0; 283 } 284 285 struct pinmux_ops imx_pmx_ops = { 286 .get_functions_count = pinmux_generic_get_function_count, 287 .get_function_name = pinmux_generic_get_function_name, 288 .get_function_groups = pinmux_generic_get_function_groups, 289 .set_mux = imx_pmx_set, 290 }; 291 292 /* decode generic config into raw register values */ 293 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, 294 unsigned long *configs, 295 unsigned int num_configs) 296 { 297 const struct imx_pinctrl_soc_info *info = ipctl->info; 298 const struct imx_cfg_params_decode *decode; 299 enum pin_config_param param; 300 u32 raw_config = 0; 301 u32 param_val; 302 int i, j; 303 304 WARN_ON(num_configs > info->num_decodes); 305 306 for (i = 0; i < num_configs; i++) { 307 param = pinconf_to_config_param(configs[i]); 308 param_val = pinconf_to_config_argument(configs[i]); 309 decode = info->decodes; 310 for (j = 0; j < info->num_decodes; j++) { 311 if (param == decode->param) { 312 if (decode->invert) 313 param_val = !param_val; 314 raw_config |= (param_val << decode->shift) 315 & decode->mask; 316 break; 317 } 318 decode++; 319 } 320 } 321 322 if (info->fixup) 323 info->fixup(configs, num_configs, &raw_config); 324 325 return raw_config; 326 } 327 328 static u32 imx_pinconf_parse_generic_config(struct device_node *np, 329 struct imx_pinctrl *ipctl) 330 { 331 const struct imx_pinctrl_soc_info *info = ipctl->info; 332 struct pinctrl_dev *pctl = ipctl->pctl; 333 unsigned int num_configs; 334 unsigned long *configs; 335 int ret; 336 337 if (!info->generic_pinconf) 338 return 0; 339 340 ret = pinconf_generic_parse_dt_config(np, pctl, &configs, 341 &num_configs); 342 if (ret) 343 return 0; 344 345 return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); 346 } 347 348 static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, 349 unsigned long *config) 350 { 351 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 352 const struct imx_pinctrl_soc_info *info = ipctl->info; 353 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 354 355 if (pin_reg->conf_reg == -1) { 356 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 357 info->pins[pin_id].name); 358 return -EINVAL; 359 } 360 361 *config = readl(ipctl->base + pin_reg->conf_reg); 362 363 if (info->flags & SHARE_MUX_CONF_REG) 364 *config &= ~info->mux_mask; 365 366 return 0; 367 } 368 369 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 370 unsigned pin_id, unsigned long *config) 371 { 372 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 373 const struct imx_pinctrl_soc_info *info = ipctl->info; 374 375 if (info->flags & IMX_USE_SCU) 376 return imx_pinconf_get_scu(pctldev, pin_id, config); 377 else 378 return imx_pinconf_get_mmio(pctldev, pin_id, config); 379 } 380 381 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, 382 unsigned pin_id, unsigned long *configs, 383 unsigned num_configs) 384 { 385 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 386 const struct imx_pinctrl_soc_info *info = ipctl->info; 387 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 388 int i; 389 390 if (pin_reg->conf_reg == -1) { 391 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 392 info->pins[pin_id].name); 393 return -EINVAL; 394 } 395 396 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 397 info->pins[pin_id].name); 398 399 for (i = 0; i < num_configs; i++) { 400 if (info->flags & SHARE_MUX_CONF_REG) { 401 u32 reg; 402 reg = readl(ipctl->base + pin_reg->conf_reg); 403 reg &= info->mux_mask; 404 reg |= configs[i]; 405 writel(reg, ipctl->base + pin_reg->conf_reg); 406 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 407 pin_reg->conf_reg, reg); 408 } else { 409 writel(configs[i], ipctl->base + pin_reg->conf_reg); 410 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 411 pin_reg->conf_reg, configs[i]); 412 } 413 } /* for each config */ 414 415 return 0; 416 } 417 418 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 419 unsigned pin_id, unsigned long *configs, 420 unsigned num_configs) 421 { 422 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 423 const struct imx_pinctrl_soc_info *info = ipctl->info; 424 425 if (info->flags & IMX_USE_SCU) 426 return imx_pinconf_set_scu(pctldev, pin_id, 427 configs, num_configs); 428 else 429 return imx_pinconf_set_mmio(pctldev, pin_id, 430 configs, num_configs); 431 } 432 433 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 434 struct seq_file *s, unsigned pin_id) 435 { 436 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 437 const struct imx_pinctrl_soc_info *info = ipctl->info; 438 const struct imx_pin_reg *pin_reg; 439 unsigned long config; 440 int ret; 441 442 if (info->flags & IMX_USE_SCU) { 443 ret = imx_pinconf_get_scu(pctldev, pin_id, &config); 444 if (ret) { 445 dev_err(ipctl->dev, "failed to get %s pinconf\n", 446 pin_get_name(pctldev, pin_id)); 447 seq_puts(s, "N/A"); 448 return; 449 } 450 } else { 451 pin_reg = &ipctl->pin_regs[pin_id]; 452 if (pin_reg->conf_reg == -1) { 453 seq_puts(s, "N/A"); 454 return; 455 } 456 457 config = readl(ipctl->base + pin_reg->conf_reg); 458 } 459 460 seq_printf(s, "0x%lx", config); 461 } 462 463 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 464 struct seq_file *s, unsigned group) 465 { 466 struct group_desc *grp; 467 unsigned long config; 468 const char *name; 469 int i, ret; 470 471 if (group >= pctldev->num_groups) 472 return; 473 474 seq_puts(s, "\n"); 475 grp = pinctrl_generic_get_group(pctldev, group); 476 if (!grp) 477 return; 478 479 for (i = 0; i < grp->num_pins; i++) { 480 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 481 482 name = pin_get_name(pctldev, pin->pin); 483 ret = imx_pinconf_get(pctldev, pin->pin, &config); 484 if (ret) 485 return; 486 seq_printf(s, " %s: 0x%lx\n", name, config); 487 } 488 } 489 490 static const struct pinconf_ops imx_pinconf_ops = { 491 .pin_config_get = imx_pinconf_get, 492 .pin_config_set = imx_pinconf_set, 493 .pin_config_dbg_show = imx_pinconf_dbg_show, 494 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 495 }; 496 497 /* 498 * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID 499 * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin. 500 * For generic_pinconf case, there's no extra u32 CONFIG. 501 * 502 * PIN_FUNC_ID format: 503 * Default: 504 * <mux_reg conf_reg input_reg mux_mode input_val> 505 * SHARE_MUX_CONF_REG: 506 * <mux_conf_reg input_reg mux_mode input_val> 507 * IMX_USE_SCU: 508 * <pin_id mux_mode> 509 */ 510 #define FSL_PIN_SIZE 24 511 #define FSL_PIN_SHARE_SIZE 20 512 #define FSL_SCU_PIN_SIZE 12 513 514 static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, 515 unsigned int *pin_id, struct imx_pin *pin, 516 const __be32 **list_p, 517 struct device_node *np) 518 { 519 const struct imx_pinctrl_soc_info *info = ipctl->info; 520 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 521 struct imx_pin_reg *pin_reg; 522 const __be32 *list = *list_p; 523 u32 mux_reg, conf_reg; 524 u32 config; 525 526 mux_reg = be32_to_cpu(*list++); 527 528 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 529 mux_reg = -1; 530 531 if (info->flags & SHARE_MUX_CONF_REG) { 532 conf_reg = mux_reg; 533 } else { 534 conf_reg = be32_to_cpu(*list++); 535 if (!conf_reg) 536 conf_reg = -1; 537 } 538 539 *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 540 pin_reg = &ipctl->pin_regs[*pin_id]; 541 pin->pin = *pin_id; 542 pin_reg->mux_reg = mux_reg; 543 pin_reg->conf_reg = conf_reg; 544 pin_mmio->input_reg = be32_to_cpu(*list++); 545 pin_mmio->mux_mode = be32_to_cpu(*list++); 546 pin_mmio->input_val = be32_to_cpu(*list++); 547 548 if (info->generic_pinconf) { 549 /* generic pin config decoded */ 550 pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl); 551 } else { 552 /* legacy pin config read from devicetree */ 553 config = be32_to_cpu(*list++); 554 555 /* SION bit is in mux register */ 556 if (config & IMX_PAD_SION) 557 pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; 558 pin_mmio->config = config & ~IMX_PAD_SION; 559 } 560 561 *list_p = list; 562 563 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, 564 pin_mmio->mux_mode, pin_mmio->config); 565 } 566 567 static int imx_pinctrl_parse_groups(struct device_node *np, 568 struct group_desc *grp, 569 struct imx_pinctrl *ipctl, 570 u32 index) 571 { 572 const struct imx_pinctrl_soc_info *info = ipctl->info; 573 struct imx_pin *pin; 574 int size, pin_size; 575 const __be32 *list; 576 int i; 577 578 dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np); 579 580 if (info->flags & IMX_USE_SCU) 581 pin_size = FSL_SCU_PIN_SIZE; 582 else if (info->flags & SHARE_MUX_CONF_REG) 583 pin_size = FSL_PIN_SHARE_SIZE; 584 else 585 pin_size = FSL_PIN_SIZE; 586 587 if (info->generic_pinconf) 588 pin_size -= 4; 589 590 /* Initialise group */ 591 grp->name = np->name; 592 593 /* 594 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 595 * do sanity check and calculate pins number 596 * 597 * First try legacy 'fsl,pins' property, then fall back to the 598 * generic 'pinmux'. 599 * 600 * Note: for generic 'pinmux' case, there's no CONFIG part in 601 * the binding format. 602 */ 603 list = of_get_property(np, "fsl,pins", &size); 604 if (!list) { 605 list = of_get_property(np, "pinmux", &size); 606 if (!list) { 607 dev_err(ipctl->dev, 608 "no fsl,pins and pins property in node %pOF\n", np); 609 return -EINVAL; 610 } 611 } 612 613 /* we do not check return since it's safe node passed down */ 614 if (!size || size % pin_size) { 615 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); 616 return -EINVAL; 617 } 618 619 grp->num_pins = size / pin_size; 620 grp->data = devm_kcalloc(ipctl->dev, 621 grp->num_pins, sizeof(struct imx_pin), 622 GFP_KERNEL); 623 grp->pins = devm_kcalloc(ipctl->dev, 624 grp->num_pins, sizeof(unsigned int), 625 GFP_KERNEL); 626 if (!grp->pins || !grp->data) 627 return -ENOMEM; 628 629 for (i = 0; i < grp->num_pins; i++) { 630 pin = &((struct imx_pin *)(grp->data))[i]; 631 if (info->flags & IMX_USE_SCU) 632 imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i], 633 pin, &list); 634 else 635 imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i], 636 pin, &list, np); 637 } 638 639 return 0; 640 } 641 642 static int imx_pinctrl_parse_functions(struct device_node *np, 643 struct imx_pinctrl *ipctl, 644 u32 index) 645 { 646 struct pinctrl_dev *pctl = ipctl->pctl; 647 struct device_node *child; 648 struct function_desc *func; 649 struct group_desc *grp; 650 u32 i = 0; 651 652 dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); 653 654 func = pinmux_generic_get_function(pctl, index); 655 if (!func) 656 return -EINVAL; 657 658 /* Initialise function */ 659 func->name = np->name; 660 func->num_group_names = of_get_child_count(np); 661 if (func->num_group_names == 0) { 662 dev_err(ipctl->dev, "no groups defined in %pOF\n", np); 663 return -EINVAL; 664 } 665 func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names, 666 sizeof(char *), GFP_KERNEL); 667 if (!func->group_names) 668 return -ENOMEM; 669 670 for_each_child_of_node(np, child) { 671 func->group_names[i] = child->name; 672 673 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), 674 GFP_KERNEL); 675 if (!grp) { 676 of_node_put(child); 677 return -ENOMEM; 678 } 679 680 mutex_lock(&ipctl->mutex); 681 radix_tree_insert(&pctl->pin_group_tree, 682 ipctl->group_index++, grp); 683 mutex_unlock(&ipctl->mutex); 684 685 imx_pinctrl_parse_groups(child, grp, ipctl, i++); 686 } 687 688 return 0; 689 } 690 691 /* 692 * Check if the DT contains pins in the direct child nodes. This indicates the 693 * newer DT format to store pins. This function returns true if the first found 694 * fsl,pins property is in a child of np. Otherwise false is returned. 695 */ 696 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 697 { 698 struct device_node *function_np; 699 struct device_node *pinctrl_np; 700 701 for_each_child_of_node(np, function_np) { 702 if (of_property_read_bool(function_np, "fsl,pins")) { 703 of_node_put(function_np); 704 return true; 705 } 706 707 for_each_child_of_node(function_np, pinctrl_np) { 708 if (of_property_read_bool(pinctrl_np, "fsl,pins")) { 709 of_node_put(pinctrl_np); 710 of_node_put(function_np); 711 return false; 712 } 713 } 714 } 715 716 return true; 717 } 718 719 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 720 struct imx_pinctrl *ipctl) 721 { 722 struct device_node *np = pdev->dev.of_node; 723 struct device_node *child; 724 struct pinctrl_dev *pctl = ipctl->pctl; 725 u32 nfuncs = 0; 726 u32 i = 0; 727 bool flat_funcs; 728 729 if (!np) 730 return -ENODEV; 731 732 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 733 if (flat_funcs) { 734 nfuncs = 1; 735 } else { 736 nfuncs = of_get_child_count(np); 737 if (nfuncs == 0) { 738 dev_err(&pdev->dev, "no functions defined\n"); 739 return -EINVAL; 740 } 741 } 742 743 for (i = 0; i < nfuncs; i++) { 744 struct function_desc *function; 745 746 function = devm_kzalloc(&pdev->dev, sizeof(*function), 747 GFP_KERNEL); 748 if (!function) 749 return -ENOMEM; 750 751 mutex_lock(&ipctl->mutex); 752 radix_tree_insert(&pctl->pin_function_tree, i, function); 753 mutex_unlock(&ipctl->mutex); 754 } 755 pctl->num_functions = nfuncs; 756 757 ipctl->group_index = 0; 758 if (flat_funcs) { 759 pctl->num_groups = of_get_child_count(np); 760 } else { 761 pctl->num_groups = 0; 762 for_each_child_of_node(np, child) 763 pctl->num_groups += of_get_child_count(child); 764 } 765 766 if (flat_funcs) { 767 imx_pinctrl_parse_functions(np, ipctl, 0); 768 } else { 769 i = 0; 770 for_each_child_of_node(np, child) 771 imx_pinctrl_parse_functions(child, ipctl, i++); 772 } 773 774 return 0; 775 } 776 777 int imx_pinctrl_probe(struct platform_device *pdev, 778 const struct imx_pinctrl_soc_info *info) 779 { 780 struct regmap_config config = { .name = "gpr" }; 781 struct device_node *dev_np = pdev->dev.of_node; 782 struct pinctrl_desc *imx_pinctrl_desc; 783 struct device_node *np; 784 struct imx_pinctrl *ipctl; 785 struct regmap *gpr; 786 int ret, i; 787 788 if (!info || !info->pins || !info->npins) { 789 dev_err(&pdev->dev, "wrong pinctrl info\n"); 790 return -EINVAL; 791 } 792 793 if (info->gpr_compatible) { 794 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); 795 if (!IS_ERR(gpr)) 796 regmap_attach_dev(&pdev->dev, gpr, &config); 797 } 798 799 /* Create state holders etc for this driver */ 800 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 801 if (!ipctl) 802 return -ENOMEM; 803 804 if (!(info->flags & IMX_USE_SCU)) { 805 ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, 806 sizeof(*ipctl->pin_regs), 807 GFP_KERNEL); 808 if (!ipctl->pin_regs) 809 return -ENOMEM; 810 811 for (i = 0; i < info->npins; i++) { 812 ipctl->pin_regs[i].mux_reg = -1; 813 ipctl->pin_regs[i].conf_reg = -1; 814 } 815 816 ipctl->base = devm_platform_ioremap_resource(pdev, 0); 817 if (IS_ERR(ipctl->base)) 818 return PTR_ERR(ipctl->base); 819 820 if (of_property_read_bool(dev_np, "fsl,input-sel")) { 821 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); 822 if (!np) { 823 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); 824 return -EINVAL; 825 } 826 827 ipctl->input_sel_base = of_iomap(np, 0); 828 of_node_put(np); 829 if (!ipctl->input_sel_base) { 830 dev_err(&pdev->dev, 831 "iomuxc input select base address not found\n"); 832 return -ENOMEM; 833 } 834 } 835 } 836 837 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), 838 GFP_KERNEL); 839 if (!imx_pinctrl_desc) 840 return -ENOMEM; 841 842 imx_pinctrl_desc->name = dev_name(&pdev->dev); 843 imx_pinctrl_desc->pins = info->pins; 844 imx_pinctrl_desc->npins = info->npins; 845 imx_pinctrl_desc->pctlops = &imx_pctrl_ops; 846 imx_pinctrl_desc->pmxops = &imx_pmx_ops; 847 imx_pinctrl_desc->confops = &imx_pinconf_ops; 848 imx_pinctrl_desc->owner = THIS_MODULE; 849 850 /* for generic pinconf */ 851 imx_pinctrl_desc->custom_params = info->custom_params; 852 imx_pinctrl_desc->num_custom_params = info->num_custom_params; 853 854 /* platform specific callback */ 855 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; 856 857 mutex_init(&ipctl->mutex); 858 859 ipctl->info = info; 860 ipctl->dev = &pdev->dev; 861 platform_set_drvdata(pdev, ipctl); 862 ret = devm_pinctrl_register_and_init(&pdev->dev, 863 imx_pinctrl_desc, ipctl, 864 &ipctl->pctl); 865 if (ret) { 866 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 867 return ret; 868 } 869 870 ret = imx_pinctrl_probe_dt(pdev, ipctl); 871 if (ret) { 872 dev_err(&pdev->dev, "fail to probe dt properties\n"); 873 return ret; 874 } 875 876 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 877 878 return pinctrl_enable(ipctl->pctl); 879 } 880 881 static int __maybe_unused imx_pinctrl_suspend(struct device *dev) 882 { 883 struct imx_pinctrl *ipctl = dev_get_drvdata(dev); 884 885 return pinctrl_force_sleep(ipctl->pctl); 886 } 887 888 static int __maybe_unused imx_pinctrl_resume(struct device *dev) 889 { 890 struct imx_pinctrl *ipctl = dev_get_drvdata(dev); 891 892 return pinctrl_force_default(ipctl->pctl); 893 } 894 895 const struct dev_pm_ops imx_pinctrl_pm_ops = { 896 SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, 897 imx_pinctrl_resume) 898 }; 899