1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Core driver for the imx pin controller
4 //
5 // Copyright (C) 2012 Freescale Semiconductor, Inc.
6 // Copyright (C) 2012 Linaro Ltd.
7 //
8 // Author: Dong Aisheng <dong.aisheng@linaro.org>
9 
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/of_address.h>
18 #include <linux/pinctrl/machine.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/slab.h>
23 #include <linux/regmap.h>
24 
25 #include "../core.h"
26 #include "../pinconf.h"
27 #include "../pinmux.h"
28 #include "pinctrl-imx.h"
29 
30 /* The bits in CONFIG cell defined in binding doc*/
31 #define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
32 #define IMX_PAD_SION 0x40000000		/* set SION */
33 
34 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
35 				struct pinctrl_dev *pctldev,
36 				const char *name)
37 {
38 	const struct group_desc *grp = NULL;
39 	int i;
40 
41 	for (i = 0; i < pctldev->num_groups; i++) {
42 		grp = pinctrl_generic_get_group(pctldev, i);
43 		if (grp && !strcmp(grp->name, name))
44 			break;
45 	}
46 
47 	return grp;
48 }
49 
50 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
51 		   unsigned offset)
52 {
53 	seq_printf(s, "%s", dev_name(pctldev->dev));
54 }
55 
56 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
57 			struct device_node *np,
58 			struct pinctrl_map **map, unsigned *num_maps)
59 {
60 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
61 	const struct imx_pinctrl_soc_info *info = ipctl->info;
62 	const struct group_desc *grp;
63 	struct pinctrl_map *new_map;
64 	struct device_node *parent;
65 	struct imx_pin *pin;
66 	int map_num = 1;
67 	int i, j;
68 
69 	/*
70 	 * first find the group of this node and check if we need create
71 	 * config maps for pins
72 	 */
73 	grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
74 	if (!grp) {
75 		dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
76 		return -EINVAL;
77 	}
78 
79 	if (info->flags & IMX_USE_SCU) {
80 		map_num += grp->num_pins;
81 	} else {
82 		for (i = 0; i < grp->num_pins; i++) {
83 			pin = &((struct imx_pin *)(grp->data))[i];
84 			if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
85 				map_num++;
86 		}
87 	}
88 
89 	new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
90 				GFP_KERNEL);
91 	if (!new_map)
92 		return -ENOMEM;
93 
94 	*map = new_map;
95 	*num_maps = map_num;
96 
97 	/* create mux map */
98 	parent = of_get_parent(np);
99 	if (!parent) {
100 		kfree(new_map);
101 		return -EINVAL;
102 	}
103 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
104 	new_map[0].data.mux.function = parent->name;
105 	new_map[0].data.mux.group = np->name;
106 	of_node_put(parent);
107 
108 	/* create config map */
109 	new_map++;
110 	for (i = j = 0; i < grp->num_pins; i++) {
111 		pin = &((struct imx_pin *)(grp->data))[i];
112 
113 		/*
114 		 * We only create config maps for SCU pads or MMIO pads that
115 		 * are not using the default config(a.k.a IMX_NO_PAD_CTL)
116 		 */
117 		if (!(info->flags & IMX_USE_SCU) &&
118 		    (pin->conf.mmio.config & IMX_NO_PAD_CTL))
119 			continue;
120 
121 		new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
122 		new_map[j].data.configs.group_or_pin =
123 					pin_get_name(pctldev, pin->pin);
124 
125 		if (info->flags & IMX_USE_SCU) {
126 			/*
127 			 * For SCU case, we set mux and conf together
128 			 * in one IPC call
129 			 */
130 			new_map[j].data.configs.configs =
131 					(unsigned long *)&pin->conf.scu;
132 			new_map[j].data.configs.num_configs = 2;
133 		} else {
134 			new_map[j].data.configs.configs =
135 					&pin->conf.mmio.config;
136 			new_map[j].data.configs.num_configs = 1;
137 		}
138 
139 		j++;
140 	}
141 
142 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
143 		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
144 
145 	return 0;
146 }
147 
148 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
149 				struct pinctrl_map *map, unsigned num_maps)
150 {
151 	kfree(map);
152 }
153 
154 static const struct pinctrl_ops imx_pctrl_ops = {
155 	.get_groups_count = pinctrl_generic_get_group_count,
156 	.get_group_name = pinctrl_generic_get_group_name,
157 	.get_group_pins = pinctrl_generic_get_group_pins,
158 	.pin_dbg_show = imx_pin_dbg_show,
159 	.dt_node_to_map = imx_dt_node_to_map,
160 	.dt_free_map = imx_dt_free_map,
161 };
162 
163 static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
164 				    struct imx_pin *pin)
165 {
166 	const struct imx_pinctrl_soc_info *info = ipctl->info;
167 	struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
168 	const struct imx_pin_reg *pin_reg;
169 	unsigned int pin_id;
170 
171 	pin_id = pin->pin;
172 	pin_reg = &ipctl->pin_regs[pin_id];
173 
174 	if (pin_reg->mux_reg == -1) {
175 		dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
176 			info->pins[pin_id].name);
177 		return 0;
178 	}
179 
180 	if (info->flags & SHARE_MUX_CONF_REG) {
181 		u32 reg;
182 
183 		reg = readl(ipctl->base + pin_reg->mux_reg);
184 		reg &= ~info->mux_mask;
185 		reg |= (pin_mmio->mux_mode << info->mux_shift);
186 		writel(reg, ipctl->base + pin_reg->mux_reg);
187 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
188 			pin_reg->mux_reg, reg);
189 	} else {
190 		writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
191 		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
192 			pin_reg->mux_reg, pin_mmio->mux_mode);
193 	}
194 
195 	/*
196 	 * If the select input value begins with 0xff, it's a quirky
197 	 * select input and the value should be interpreted as below.
198 	 *     31     23      15      7        0
199 	 *     | 0xff | shift | width | select |
200 	 * It's used to work around the problem that the select
201 	 * input for some pin is not implemented in the select
202 	 * input register but in some general purpose register.
203 	 * We encode the select input value, width and shift of
204 	 * the bit field into input_val cell of pin function ID
205 	 * in device tree, and then decode them here for setting
206 	 * up the select input bits in general purpose register.
207 	 */
208 	if (pin_mmio->input_val >> 24 == 0xff) {
209 		u32 val = pin_mmio->input_val;
210 		u8 select = val & 0xff;
211 		u8 width = (val >> 8) & 0xff;
212 		u8 shift = (val >> 16) & 0xff;
213 		u32 mask = ((1 << width) - 1) << shift;
214 		/*
215 		 * The input_reg[i] here is actually some IOMUXC general
216 		 * purpose register, not regular select input register.
217 		 */
218 		val = readl(ipctl->base + pin_mmio->input_reg);
219 		val &= ~mask;
220 		val |= select << shift;
221 		writel(val, ipctl->base + pin_mmio->input_reg);
222 	} else if (pin_mmio->input_reg) {
223 		/*
224 		 * Regular select input register can never be at offset
225 		 * 0, and we only print register value for regular case.
226 		 */
227 		if (ipctl->input_sel_base)
228 			writel(pin_mmio->input_val, ipctl->input_sel_base +
229 					pin_mmio->input_reg);
230 		else
231 			writel(pin_mmio->input_val, ipctl->base +
232 					pin_mmio->input_reg);
233 		dev_dbg(ipctl->dev,
234 			"==>select_input: offset 0x%x val 0x%x\n",
235 			pin_mmio->input_reg, pin_mmio->input_val);
236 	}
237 
238 	return 0;
239 }
240 
241 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
242 		       unsigned group)
243 {
244 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
245 	const struct imx_pinctrl_soc_info *info = ipctl->info;
246 	struct function_desc *func;
247 	struct group_desc *grp;
248 	struct imx_pin *pin;
249 	unsigned int npins;
250 	int i, err;
251 
252 	/*
253 	 * Configure the mux mode for each pin in the group for a specific
254 	 * function.
255 	 */
256 	grp = pinctrl_generic_get_group(pctldev, group);
257 	if (!grp)
258 		return -EINVAL;
259 
260 	func = pinmux_generic_get_function(pctldev, selector);
261 	if (!func)
262 		return -EINVAL;
263 
264 	npins = grp->num_pins;
265 
266 	dev_dbg(ipctl->dev, "enable function %s group %s\n",
267 		func->name, grp->name);
268 
269 	for (i = 0; i < npins; i++) {
270 		/*
271 		 * For IMX_USE_SCU case, we postpone the mux setting
272 		 * until config is set as we can set them together
273 		 * in one IPC call
274 		 */
275 		pin = &((struct imx_pin *)(grp->data))[i];
276 		if (!(info->flags & IMX_USE_SCU)) {
277 			err = imx_pmx_set_one_pin_mmio(ipctl, pin);
278 			if (err)
279 				return err;
280 		}
281 	}
282 
283 	return 0;
284 }
285 
286 struct pinmux_ops imx_pmx_ops = {
287 	.get_functions_count = pinmux_generic_get_function_count,
288 	.get_function_name = pinmux_generic_get_function_name,
289 	.get_function_groups = pinmux_generic_get_function_groups,
290 	.set_mux = imx_pmx_set,
291 };
292 
293 /* decode generic config into raw register values */
294 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
295 					      unsigned long *configs,
296 					      unsigned int num_configs)
297 {
298 	const struct imx_pinctrl_soc_info *info = ipctl->info;
299 	const struct imx_cfg_params_decode *decode;
300 	enum pin_config_param param;
301 	u32 raw_config = 0;
302 	u32 param_val;
303 	int i, j;
304 
305 	WARN_ON(num_configs > info->num_decodes);
306 
307 	for (i = 0; i < num_configs; i++) {
308 		param = pinconf_to_config_param(configs[i]);
309 		param_val = pinconf_to_config_argument(configs[i]);
310 		decode = info->decodes;
311 		for (j = 0; j < info->num_decodes; j++) {
312 			if (param == decode->param) {
313 				if (decode->invert)
314 					param_val = !param_val;
315 				raw_config |= (param_val << decode->shift)
316 					      & decode->mask;
317 				break;
318 			}
319 			decode++;
320 		}
321 	}
322 
323 	if (info->fixup)
324 		info->fixup(configs, num_configs, &raw_config);
325 
326 	return raw_config;
327 }
328 
329 static u32 imx_pinconf_parse_generic_config(struct device_node *np,
330 					    struct imx_pinctrl *ipctl)
331 {
332 	const struct imx_pinctrl_soc_info *info = ipctl->info;
333 	struct pinctrl_dev *pctl = ipctl->pctl;
334 	unsigned int num_configs;
335 	unsigned long *configs;
336 	int ret;
337 
338 	if (!info->generic_pinconf)
339 		return 0;
340 
341 	ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
342 					      &num_configs);
343 	if (ret)
344 		return 0;
345 
346 	return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
347 }
348 
349 static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
350 				unsigned long *config)
351 {
352 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
353 	const struct imx_pinctrl_soc_info *info = ipctl->info;
354 	const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
355 
356 	if (pin_reg->conf_reg == -1) {
357 		dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
358 			info->pins[pin_id].name);
359 		return -EINVAL;
360 	}
361 
362 	*config = readl(ipctl->base + pin_reg->conf_reg);
363 
364 	if (info->flags & SHARE_MUX_CONF_REG)
365 		*config &= ~info->mux_mask;
366 
367 	return 0;
368 }
369 
370 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
371 			   unsigned pin_id, unsigned long *config)
372 {
373 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
374 	const struct imx_pinctrl_soc_info *info = ipctl->info;
375 
376 	if (info->flags & IMX_USE_SCU)
377 		return info->imx_pinconf_get(pctldev, pin_id, config);
378 	else
379 		return imx_pinconf_get_mmio(pctldev, pin_id, config);
380 }
381 
382 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
383 				unsigned pin_id, unsigned long *configs,
384 				unsigned num_configs)
385 {
386 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
387 	const struct imx_pinctrl_soc_info *info = ipctl->info;
388 	const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
389 	int i;
390 
391 	if (pin_reg->conf_reg == -1) {
392 		dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
393 			info->pins[pin_id].name);
394 		return -EINVAL;
395 	}
396 
397 	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
398 		info->pins[pin_id].name);
399 
400 	for (i = 0; i < num_configs; i++) {
401 		if (info->flags & SHARE_MUX_CONF_REG) {
402 			u32 reg;
403 			reg = readl(ipctl->base + pin_reg->conf_reg);
404 			reg &= info->mux_mask;
405 			reg |= configs[i];
406 			writel(reg, ipctl->base + pin_reg->conf_reg);
407 			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
408 				pin_reg->conf_reg, reg);
409 		} else {
410 			writel(configs[i], ipctl->base + pin_reg->conf_reg);
411 			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
412 				pin_reg->conf_reg, configs[i]);
413 		}
414 	} /* for each config */
415 
416 	return 0;
417 }
418 
419 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
420 			   unsigned pin_id, unsigned long *configs,
421 			   unsigned num_configs)
422 {
423 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
424 	const struct imx_pinctrl_soc_info *info = ipctl->info;
425 
426 	if (info->flags & IMX_USE_SCU)
427 		return info->imx_pinconf_set(pctldev, pin_id,
428 					   configs, num_configs);
429 	else
430 		return imx_pinconf_set_mmio(pctldev, pin_id,
431 					    configs, num_configs);
432 }
433 
434 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
435 				   struct seq_file *s, unsigned pin_id)
436 {
437 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
438 	const struct imx_pinctrl_soc_info *info = ipctl->info;
439 	const struct imx_pin_reg *pin_reg;
440 	unsigned long config;
441 	int ret;
442 
443 	if (info->flags & IMX_USE_SCU) {
444 		ret = info->imx_pinconf_get(pctldev, pin_id, &config);
445 		if (ret) {
446 			dev_err(ipctl->dev, "failed to get %s pinconf\n",
447 				pin_get_name(pctldev, pin_id));
448 			seq_puts(s, "N/A");
449 			return;
450 		}
451 	} else {
452 		pin_reg = &ipctl->pin_regs[pin_id];
453 		if (pin_reg->conf_reg == -1) {
454 			seq_puts(s, "N/A");
455 			return;
456 		}
457 
458 		config = readl(ipctl->base + pin_reg->conf_reg);
459 	}
460 
461 	seq_printf(s, "0x%lx", config);
462 }
463 
464 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
465 					 struct seq_file *s, unsigned group)
466 {
467 	struct group_desc *grp;
468 	unsigned long config;
469 	const char *name;
470 	int i, ret;
471 
472 	if (group >= pctldev->num_groups)
473 		return;
474 
475 	seq_puts(s, "\n");
476 	grp = pinctrl_generic_get_group(pctldev, group);
477 	if (!grp)
478 		return;
479 
480 	for (i = 0; i < grp->num_pins; i++) {
481 		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
482 
483 		name = pin_get_name(pctldev, pin->pin);
484 		ret = imx_pinconf_get(pctldev, pin->pin, &config);
485 		if (ret)
486 			return;
487 		seq_printf(s, "  %s: 0x%lx\n", name, config);
488 	}
489 }
490 
491 static const struct pinconf_ops imx_pinconf_ops = {
492 	.pin_config_get = imx_pinconf_get,
493 	.pin_config_set = imx_pinconf_set,
494 	.pin_config_dbg_show = imx_pinconf_dbg_show,
495 	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
496 };
497 
498 /*
499  * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
500  * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
501  * For generic_pinconf case, there's no extra u32 CONFIG.
502  *
503  * PIN_FUNC_ID format:
504  * Default:
505  *     <mux_reg conf_reg input_reg mux_mode input_val>
506  * SHARE_MUX_CONF_REG:
507  *     <mux_conf_reg input_reg mux_mode input_val>
508  * IMX_USE_SCU:
509  *	<pin_id mux_mode>
510  */
511 #define FSL_PIN_SIZE 24
512 #define FSL_PIN_SHARE_SIZE 20
513 #define FSL_SCU_PIN_SIZE 12
514 
515 static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
516 				       unsigned int *pin_id, struct imx_pin *pin,
517 				       const __be32 **list_p,
518 				       struct device_node *np)
519 {
520 	const struct imx_pinctrl_soc_info *info = ipctl->info;
521 	struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
522 	struct imx_pin_reg *pin_reg;
523 	const __be32 *list = *list_p;
524 	u32 mux_reg, conf_reg;
525 	u32 config;
526 
527 	mux_reg = be32_to_cpu(*list++);
528 
529 	if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
530 		mux_reg = -1;
531 
532 	if (info->flags & SHARE_MUX_CONF_REG) {
533 		conf_reg = mux_reg;
534 	} else {
535 		conf_reg = be32_to_cpu(*list++);
536 		if (!conf_reg)
537 			conf_reg = -1;
538 	}
539 
540 	*pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
541 	pin_reg = &ipctl->pin_regs[*pin_id];
542 	pin->pin = *pin_id;
543 	pin_reg->mux_reg = mux_reg;
544 	pin_reg->conf_reg = conf_reg;
545 	pin_mmio->input_reg = be32_to_cpu(*list++);
546 	pin_mmio->mux_mode = be32_to_cpu(*list++);
547 	pin_mmio->input_val = be32_to_cpu(*list++);
548 
549 	if (info->generic_pinconf) {
550 		/* generic pin config decoded */
551 		pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
552 	} else {
553 		/* legacy pin config read from devicetree */
554 		config = be32_to_cpu(*list++);
555 
556 		/* SION bit is in mux register */
557 		if (config & IMX_PAD_SION)
558 			pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
559 		pin_mmio->config = config & ~IMX_PAD_SION;
560 	}
561 
562 	*list_p = list;
563 
564 	dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
565 			     pin_mmio->mux_mode, pin_mmio->config);
566 }
567 
568 static int imx_pinctrl_parse_groups(struct device_node *np,
569 				    struct group_desc *grp,
570 				    struct imx_pinctrl *ipctl,
571 				    u32 index)
572 {
573 	const struct imx_pinctrl_soc_info *info = ipctl->info;
574 	struct imx_pin *pin;
575 	int size, pin_size;
576 	const __be32 *list;
577 	int i;
578 
579 	dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
580 
581 	if (info->flags & IMX_USE_SCU)
582 		pin_size = FSL_SCU_PIN_SIZE;
583 	else if (info->flags & SHARE_MUX_CONF_REG)
584 		pin_size = FSL_PIN_SHARE_SIZE;
585 	else
586 		pin_size = FSL_PIN_SIZE;
587 
588 	if (info->generic_pinconf)
589 		pin_size -= 4;
590 
591 	/* Initialise group */
592 	grp->name = np->name;
593 
594 	/*
595 	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
596 	 * do sanity check and calculate pins number
597 	 *
598 	 * First try legacy 'fsl,pins' property, then fall back to the
599 	 * generic 'pinmux'.
600 	 *
601 	 * Note: for generic 'pinmux' case, there's no CONFIG part in
602 	 * the binding format.
603 	 */
604 	list = of_get_property(np, "fsl,pins", &size);
605 	if (!list) {
606 		list = of_get_property(np, "pinmux", &size);
607 		if (!list) {
608 			dev_err(ipctl->dev,
609 				"no fsl,pins and pins property in node %pOF\n", np);
610 			return -EINVAL;
611 		}
612 	}
613 
614 	/* we do not check return since it's safe node passed down */
615 	if (!size || size % pin_size) {
616 		dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
617 		return -EINVAL;
618 	}
619 
620 	grp->num_pins = size / pin_size;
621 	grp->data = devm_kcalloc(ipctl->dev,
622 				 grp->num_pins, sizeof(struct imx_pin),
623 				 GFP_KERNEL);
624 	grp->pins = devm_kcalloc(ipctl->dev,
625 				 grp->num_pins, sizeof(unsigned int),
626 				 GFP_KERNEL);
627 	if (!grp->pins || !grp->data)
628 		return -ENOMEM;
629 
630 	for (i = 0; i < grp->num_pins; i++) {
631 		pin = &((struct imx_pin *)(grp->data))[i];
632 		if (info->flags & IMX_USE_SCU)
633 			info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
634 						  pin, &list);
635 		else
636 			imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
637 						   pin, &list, np);
638 	}
639 
640 	return 0;
641 }
642 
643 static int imx_pinctrl_parse_functions(struct device_node *np,
644 				       struct imx_pinctrl *ipctl,
645 				       u32 index)
646 {
647 	struct pinctrl_dev *pctl = ipctl->pctl;
648 	struct device_node *child;
649 	struct function_desc *func;
650 	struct group_desc *grp;
651 	u32 i = 0;
652 
653 	dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
654 
655 	func = pinmux_generic_get_function(pctl, index);
656 	if (!func)
657 		return -EINVAL;
658 
659 	/* Initialise function */
660 	func->name = np->name;
661 	func->num_group_names = of_get_child_count(np);
662 	if (func->num_group_names == 0) {
663 		dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
664 		return -EINVAL;
665 	}
666 	func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
667 					 sizeof(char *), GFP_KERNEL);
668 	if (!func->group_names)
669 		return -ENOMEM;
670 
671 	for_each_child_of_node(np, child) {
672 		func->group_names[i] = child->name;
673 
674 		grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
675 				   GFP_KERNEL);
676 		if (!grp) {
677 			of_node_put(child);
678 			return -ENOMEM;
679 		}
680 
681 		mutex_lock(&ipctl->mutex);
682 		radix_tree_insert(&pctl->pin_group_tree,
683 				  ipctl->group_index++, grp);
684 		mutex_unlock(&ipctl->mutex);
685 
686 		imx_pinctrl_parse_groups(child, grp, ipctl, i++);
687 	}
688 
689 	return 0;
690 }
691 
692 /*
693  * Check if the DT contains pins in the direct child nodes. This indicates the
694  * newer DT format to store pins. This function returns true if the first found
695  * fsl,pins property is in a child of np. Otherwise false is returned.
696  */
697 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
698 {
699 	struct device_node *function_np;
700 	struct device_node *pinctrl_np;
701 
702 	for_each_child_of_node(np, function_np) {
703 		if (of_property_read_bool(function_np, "fsl,pins")) {
704 			of_node_put(function_np);
705 			return true;
706 		}
707 
708 		for_each_child_of_node(function_np, pinctrl_np) {
709 			if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
710 				of_node_put(pinctrl_np);
711 				of_node_put(function_np);
712 				return false;
713 			}
714 		}
715 	}
716 
717 	return true;
718 }
719 
720 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
721 				struct imx_pinctrl *ipctl)
722 {
723 	struct device_node *np = pdev->dev.of_node;
724 	struct device_node *child;
725 	struct pinctrl_dev *pctl = ipctl->pctl;
726 	u32 nfuncs = 0;
727 	u32 i = 0;
728 	bool flat_funcs;
729 
730 	if (!np)
731 		return -ENODEV;
732 
733 	flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
734 	if (flat_funcs) {
735 		nfuncs = 1;
736 	} else {
737 		nfuncs = of_get_child_count(np);
738 		if (nfuncs == 0) {
739 			dev_err(&pdev->dev, "no functions defined\n");
740 			return -EINVAL;
741 		}
742 	}
743 
744 	for (i = 0; i < nfuncs; i++) {
745 		struct function_desc *function;
746 
747 		function = devm_kzalloc(&pdev->dev, sizeof(*function),
748 					GFP_KERNEL);
749 		if (!function)
750 			return -ENOMEM;
751 
752 		mutex_lock(&ipctl->mutex);
753 		radix_tree_insert(&pctl->pin_function_tree, i, function);
754 		mutex_unlock(&ipctl->mutex);
755 	}
756 	pctl->num_functions = nfuncs;
757 
758 	ipctl->group_index = 0;
759 	if (flat_funcs) {
760 		pctl->num_groups = of_get_child_count(np);
761 	} else {
762 		pctl->num_groups = 0;
763 		for_each_child_of_node(np, child)
764 			pctl->num_groups += of_get_child_count(child);
765 	}
766 
767 	if (flat_funcs) {
768 		imx_pinctrl_parse_functions(np, ipctl, 0);
769 	} else {
770 		i = 0;
771 		for_each_child_of_node(np, child)
772 			imx_pinctrl_parse_functions(child, ipctl, i++);
773 	}
774 
775 	return 0;
776 }
777 
778 int imx_pinctrl_probe(struct platform_device *pdev,
779 		      const struct imx_pinctrl_soc_info *info)
780 {
781 	struct regmap_config config = { .name = "gpr" };
782 	struct device_node *dev_np = pdev->dev.of_node;
783 	struct pinctrl_desc *imx_pinctrl_desc;
784 	struct device_node *np;
785 	struct imx_pinctrl *ipctl;
786 	struct regmap *gpr;
787 	int ret, i;
788 
789 	if (!info || !info->pins || !info->npins) {
790 		dev_err(&pdev->dev, "wrong pinctrl info\n");
791 		return -EINVAL;
792 	}
793 
794 	if (info->gpr_compatible) {
795 		gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
796 		if (!IS_ERR(gpr))
797 			regmap_attach_dev(&pdev->dev, gpr, &config);
798 	}
799 
800 	/* Create state holders etc for this driver */
801 	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
802 	if (!ipctl)
803 		return -ENOMEM;
804 
805 	if (!(info->flags & IMX_USE_SCU)) {
806 		ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
807 						     sizeof(*ipctl->pin_regs),
808 						     GFP_KERNEL);
809 		if (!ipctl->pin_regs)
810 			return -ENOMEM;
811 
812 		for (i = 0; i < info->npins; i++) {
813 			ipctl->pin_regs[i].mux_reg = -1;
814 			ipctl->pin_regs[i].conf_reg = -1;
815 		}
816 
817 		ipctl->base = devm_platform_ioremap_resource(pdev, 0);
818 		if (IS_ERR(ipctl->base))
819 			return PTR_ERR(ipctl->base);
820 
821 		if (of_property_read_bool(dev_np, "fsl,input-sel")) {
822 			np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
823 			if (!np) {
824 				dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
825 				return -EINVAL;
826 			}
827 
828 			ipctl->input_sel_base = of_iomap(np, 0);
829 			of_node_put(np);
830 			if (!ipctl->input_sel_base) {
831 				dev_err(&pdev->dev,
832 					"iomuxc input select base address not found\n");
833 				return -ENOMEM;
834 			}
835 		}
836 	}
837 
838 	imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
839 					GFP_KERNEL);
840 	if (!imx_pinctrl_desc)
841 		return -ENOMEM;
842 
843 	imx_pinctrl_desc->name = dev_name(&pdev->dev);
844 	imx_pinctrl_desc->pins = info->pins;
845 	imx_pinctrl_desc->npins = info->npins;
846 	imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
847 	imx_pinctrl_desc->pmxops = &imx_pmx_ops;
848 	imx_pinctrl_desc->confops = &imx_pinconf_ops;
849 	imx_pinctrl_desc->owner = THIS_MODULE;
850 
851 	/* for generic pinconf */
852 	imx_pinctrl_desc->custom_params = info->custom_params;
853 	imx_pinctrl_desc->num_custom_params = info->num_custom_params;
854 
855 	/* platform specific callback */
856 	imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
857 
858 	mutex_init(&ipctl->mutex);
859 
860 	ipctl->info = info;
861 	ipctl->dev = &pdev->dev;
862 	platform_set_drvdata(pdev, ipctl);
863 	ret = devm_pinctrl_register_and_init(&pdev->dev,
864 					     imx_pinctrl_desc, ipctl,
865 					     &ipctl->pctl);
866 	if (ret) {
867 		dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
868 		return ret;
869 	}
870 
871 	ret = imx_pinctrl_probe_dt(pdev, ipctl);
872 	if (ret) {
873 		dev_err(&pdev->dev, "fail to probe dt properties\n");
874 		return ret;
875 	}
876 
877 	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
878 
879 	return pinctrl_enable(ipctl->pctl);
880 }
881 EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
882 
883 static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
884 {
885 	struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
886 
887 	return pinctrl_force_sleep(ipctl->pctl);
888 }
889 
890 static int __maybe_unused imx_pinctrl_resume(struct device *dev)
891 {
892 	struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
893 
894 	return pinctrl_force_default(ipctl->pctl);
895 }
896 
897 const struct dev_pm_ops imx_pinctrl_pm_ops = {
898 	SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
899 					imx_pinctrl_resume)
900 };
901 EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
902 
903 MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
904 MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
905 MODULE_LICENSE("GPL v2");
906