1 /* 2 * Core driver for the imx pin controller 3 * 4 * Copyright (C) 2012 Freescale Semiconductor, Inc. 5 * Copyright (C) 2012 Linaro Ltd. 6 * 7 * Author: Dong Aisheng <dong.aisheng@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/err.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_address.h> 22 #include <linux/pinctrl/machine.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 #include <linux/slab.h> 27 28 #include "../core.h" 29 #include "pinctrl-imx.h" 30 31 /* The bits in CONFIG cell defined in binding doc*/ 32 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 33 #define IMX_PAD_SION 0x40000000 /* set SION */ 34 35 /** 36 * @dev: a pointer back to containing device 37 * @base: the offset to the controller in virtual memory 38 */ 39 struct imx_pinctrl { 40 struct device *dev; 41 struct pinctrl_dev *pctl; 42 void __iomem *base; 43 void __iomem *input_sel_base; 44 const struct imx_pinctrl_soc_info *info; 45 }; 46 47 static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( 48 const struct imx_pinctrl_soc_info *info, 49 const char *name) 50 { 51 const struct imx_pin_group *grp = NULL; 52 int i; 53 54 for (i = 0; i < info->ngroups; i++) { 55 if (!strcmp(info->groups[i].name, name)) { 56 grp = &info->groups[i]; 57 break; 58 } 59 } 60 61 return grp; 62 } 63 64 static int imx_get_groups_count(struct pinctrl_dev *pctldev) 65 { 66 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 67 const struct imx_pinctrl_soc_info *info = ipctl->info; 68 69 return info->ngroups; 70 } 71 72 static const char *imx_get_group_name(struct pinctrl_dev *pctldev, 73 unsigned selector) 74 { 75 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 76 const struct imx_pinctrl_soc_info *info = ipctl->info; 77 78 return info->groups[selector].name; 79 } 80 81 static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 82 const unsigned **pins, 83 unsigned *npins) 84 { 85 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 86 const struct imx_pinctrl_soc_info *info = ipctl->info; 87 88 if (selector >= info->ngroups) 89 return -EINVAL; 90 91 *pins = info->groups[selector].pin_ids; 92 *npins = info->groups[selector].npins; 93 94 return 0; 95 } 96 97 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 98 unsigned offset) 99 { 100 seq_printf(s, "%s", dev_name(pctldev->dev)); 101 } 102 103 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 104 struct device_node *np, 105 struct pinctrl_map **map, unsigned *num_maps) 106 { 107 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 108 const struct imx_pinctrl_soc_info *info = ipctl->info; 109 const struct imx_pin_group *grp; 110 struct pinctrl_map *new_map; 111 struct device_node *parent; 112 int map_num = 1; 113 int i, j; 114 115 /* 116 * first find the group of this node and check if we need create 117 * config maps for pins 118 */ 119 grp = imx_pinctrl_find_group_by_name(info, np->name); 120 if (!grp) { 121 dev_err(info->dev, "unable to find group for node %s\n", 122 np->name); 123 return -EINVAL; 124 } 125 126 for (i = 0; i < grp->npins; i++) { 127 if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) 128 map_num++; 129 } 130 131 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); 132 if (!new_map) 133 return -ENOMEM; 134 135 *map = new_map; 136 *num_maps = map_num; 137 138 /* create mux map */ 139 parent = of_get_parent(np); 140 if (!parent) { 141 kfree(new_map); 142 return -EINVAL; 143 } 144 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 145 new_map[0].data.mux.function = parent->name; 146 new_map[0].data.mux.group = np->name; 147 of_node_put(parent); 148 149 /* create config map */ 150 new_map++; 151 for (i = j = 0; i < grp->npins; i++) { 152 if (!(grp->pins[i].config & IMX_NO_PAD_CTL)) { 153 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 154 new_map[j].data.configs.group_or_pin = 155 pin_get_name(pctldev, grp->pins[i].pin); 156 new_map[j].data.configs.configs = &grp->pins[i].config; 157 new_map[j].data.configs.num_configs = 1; 158 j++; 159 } 160 } 161 162 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 163 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 164 165 return 0; 166 } 167 168 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 169 struct pinctrl_map *map, unsigned num_maps) 170 { 171 kfree(map); 172 } 173 174 static const struct pinctrl_ops imx_pctrl_ops = { 175 .get_groups_count = imx_get_groups_count, 176 .get_group_name = imx_get_group_name, 177 .get_group_pins = imx_get_group_pins, 178 .pin_dbg_show = imx_pin_dbg_show, 179 .dt_node_to_map = imx_dt_node_to_map, 180 .dt_free_map = imx_dt_free_map, 181 182 }; 183 184 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 185 unsigned group) 186 { 187 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 188 const struct imx_pinctrl_soc_info *info = ipctl->info; 189 const struct imx_pin_reg *pin_reg; 190 unsigned int npins, pin_id; 191 int i; 192 struct imx_pin_group *grp; 193 194 /* 195 * Configure the mux mode for each pin in the group for a specific 196 * function. 197 */ 198 grp = &info->groups[group]; 199 npins = grp->npins; 200 201 dev_dbg(ipctl->dev, "enable function %s group %s\n", 202 info->functions[selector].name, grp->name); 203 204 for (i = 0; i < npins; i++) { 205 struct imx_pin *pin = &grp->pins[i]; 206 pin_id = pin->pin; 207 pin_reg = &info->pin_regs[pin_id]; 208 209 if (pin_reg->mux_reg == -1) { 210 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", 211 info->pins[pin_id].name); 212 return -EINVAL; 213 } 214 215 if (info->flags & SHARE_MUX_CONF_REG) { 216 u32 reg; 217 reg = readl(ipctl->base + pin_reg->mux_reg); 218 reg &= ~(0x7 << 20); 219 reg |= (pin->mux_mode << 20); 220 writel(reg, ipctl->base + pin_reg->mux_reg); 221 } else { 222 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); 223 } 224 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 225 pin_reg->mux_reg, pin->mux_mode); 226 227 /* 228 * If the select input value begins with 0xff, it's a quirky 229 * select input and the value should be interpreted as below. 230 * 31 23 15 7 0 231 * | 0xff | shift | width | select | 232 * It's used to work around the problem that the select 233 * input for some pin is not implemented in the select 234 * input register but in some general purpose register. 235 * We encode the select input value, width and shift of 236 * the bit field into input_val cell of pin function ID 237 * in device tree, and then decode them here for setting 238 * up the select input bits in general purpose register. 239 */ 240 if (pin->input_val >> 24 == 0xff) { 241 u32 val = pin->input_val; 242 u8 select = val & 0xff; 243 u8 width = (val >> 8) & 0xff; 244 u8 shift = (val >> 16) & 0xff; 245 u32 mask = ((1 << width) - 1) << shift; 246 /* 247 * The input_reg[i] here is actually some IOMUXC general 248 * purpose register, not regular select input register. 249 */ 250 val = readl(ipctl->base + pin->input_reg); 251 val &= ~mask; 252 val |= select << shift; 253 writel(val, ipctl->base + pin->input_reg); 254 } else if (pin->input_reg) { 255 /* 256 * Regular select input register can never be at offset 257 * 0, and we only print register value for regular case. 258 */ 259 if (ipctl->input_sel_base) 260 writel(pin->input_val, ipctl->input_sel_base + 261 pin->input_reg); 262 else 263 writel(pin->input_val, ipctl->base + 264 pin->input_reg); 265 dev_dbg(ipctl->dev, 266 "==>select_input: offset 0x%x val 0x%x\n", 267 pin->input_reg, pin->input_val); 268 } 269 } 270 271 return 0; 272 } 273 274 static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 275 { 276 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 277 const struct imx_pinctrl_soc_info *info = ipctl->info; 278 279 return info->nfunctions; 280 } 281 282 static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, 283 unsigned selector) 284 { 285 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 286 const struct imx_pinctrl_soc_info *info = ipctl->info; 287 288 return info->functions[selector].name; 289 } 290 291 static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 292 const char * const **groups, 293 unsigned * const num_groups) 294 { 295 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 296 const struct imx_pinctrl_soc_info *info = ipctl->info; 297 298 *groups = info->functions[selector].groups; 299 *num_groups = info->functions[selector].num_groups; 300 301 return 0; 302 } 303 304 static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 305 struct pinctrl_gpio_range *range, unsigned offset) 306 { 307 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 308 const struct imx_pinctrl_soc_info *info = ipctl->info; 309 const struct imx_pin_reg *pin_reg; 310 struct imx_pin_group *grp; 311 struct imx_pin *imx_pin; 312 unsigned int pin, group; 313 u32 reg; 314 315 /* Currently implementation only for shared mux/conf register */ 316 if (!(info->flags & SHARE_MUX_CONF_REG)) 317 return -EINVAL; 318 319 pin_reg = &info->pin_regs[offset]; 320 if (pin_reg->mux_reg == -1) 321 return -EINVAL; 322 323 /* Find the pinctrl config with GPIO mux mode for the requested pin */ 324 for (group = 0; group < info->ngroups; group++) { 325 grp = &info->groups[group]; 326 for (pin = 0; pin < grp->npins; pin++) { 327 imx_pin = &grp->pins[pin]; 328 if (imx_pin->pin == offset && !imx_pin->mux_mode) 329 goto mux_pin; 330 } 331 } 332 333 return -EINVAL; 334 335 mux_pin: 336 reg = readl(ipctl->base + pin_reg->mux_reg); 337 reg &= ~(0x7 << 20); 338 reg |= imx_pin->config; 339 writel(reg, ipctl->base + pin_reg->mux_reg); 340 341 return 0; 342 } 343 344 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 345 struct pinctrl_gpio_range *range, unsigned offset, bool input) 346 { 347 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 348 const struct imx_pinctrl_soc_info *info = ipctl->info; 349 const struct imx_pin_reg *pin_reg; 350 u32 reg; 351 352 /* 353 * Only Vybrid has the input/output buffer enable flags (IBE/OBE) 354 * They are part of the shared mux/conf register. 355 */ 356 if (!(info->flags & SHARE_MUX_CONF_REG)) 357 return -EINVAL; 358 359 pin_reg = &info->pin_regs[offset]; 360 if (pin_reg->mux_reg == -1) 361 return -EINVAL; 362 363 /* IBE always enabled allows us to read the value "on the wire" */ 364 reg = readl(ipctl->base + pin_reg->mux_reg); 365 if (input) 366 reg &= ~0x2; 367 else 368 reg |= 0x2; 369 writel(reg, ipctl->base + pin_reg->mux_reg); 370 371 return 0; 372 } 373 374 static const struct pinmux_ops imx_pmx_ops = { 375 .get_functions_count = imx_pmx_get_funcs_count, 376 .get_function_name = imx_pmx_get_func_name, 377 .get_function_groups = imx_pmx_get_groups, 378 .set_mux = imx_pmx_set, 379 .gpio_request_enable = imx_pmx_gpio_request_enable, 380 .gpio_set_direction = imx_pmx_gpio_set_direction, 381 }; 382 383 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 384 unsigned pin_id, unsigned long *config) 385 { 386 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 387 const struct imx_pinctrl_soc_info *info = ipctl->info; 388 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 389 390 if (pin_reg->conf_reg == -1) { 391 dev_err(info->dev, "Pin(%s) does not support config function\n", 392 info->pins[pin_id].name); 393 return -EINVAL; 394 } 395 396 *config = readl(ipctl->base + pin_reg->conf_reg); 397 398 if (info->flags & SHARE_MUX_CONF_REG) 399 *config &= 0xffff; 400 401 return 0; 402 } 403 404 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 405 unsigned pin_id, unsigned long *configs, 406 unsigned num_configs) 407 { 408 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 409 const struct imx_pinctrl_soc_info *info = ipctl->info; 410 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 411 int i; 412 413 if (pin_reg->conf_reg == -1) { 414 dev_err(info->dev, "Pin(%s) does not support config function\n", 415 info->pins[pin_id].name); 416 return -EINVAL; 417 } 418 419 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 420 info->pins[pin_id].name); 421 422 for (i = 0; i < num_configs; i++) { 423 if (info->flags & SHARE_MUX_CONF_REG) { 424 u32 reg; 425 reg = readl(ipctl->base + pin_reg->conf_reg); 426 reg &= ~0xffff; 427 reg |= configs[i]; 428 writel(reg, ipctl->base + pin_reg->conf_reg); 429 } else { 430 writel(configs[i], ipctl->base + pin_reg->conf_reg); 431 } 432 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 433 pin_reg->conf_reg, configs[i]); 434 } /* for each config */ 435 436 return 0; 437 } 438 439 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 440 struct seq_file *s, unsigned pin_id) 441 { 442 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 443 const struct imx_pinctrl_soc_info *info = ipctl->info; 444 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 445 unsigned long config; 446 447 if (!pin_reg || pin_reg->conf_reg == -1) { 448 seq_printf(s, "N/A"); 449 return; 450 } 451 452 config = readl(ipctl->base + pin_reg->conf_reg); 453 seq_printf(s, "0x%lx", config); 454 } 455 456 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 457 struct seq_file *s, unsigned group) 458 { 459 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 460 const struct imx_pinctrl_soc_info *info = ipctl->info; 461 struct imx_pin_group *grp; 462 unsigned long config; 463 const char *name; 464 int i, ret; 465 466 if (group > info->ngroups) 467 return; 468 469 seq_printf(s, "\n"); 470 grp = &info->groups[group]; 471 for (i = 0; i < grp->npins; i++) { 472 struct imx_pin *pin = &grp->pins[i]; 473 name = pin_get_name(pctldev, pin->pin); 474 ret = imx_pinconf_get(pctldev, pin->pin, &config); 475 if (ret) 476 return; 477 seq_printf(s, "%s: 0x%lx", name, config); 478 } 479 } 480 481 static const struct pinconf_ops imx_pinconf_ops = { 482 .pin_config_get = imx_pinconf_get, 483 .pin_config_set = imx_pinconf_set, 484 .pin_config_dbg_show = imx_pinconf_dbg_show, 485 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 486 }; 487 488 static struct pinctrl_desc imx_pinctrl_desc = { 489 .pctlops = &imx_pctrl_ops, 490 .pmxops = &imx_pmx_ops, 491 .confops = &imx_pinconf_ops, 492 .owner = THIS_MODULE, 493 }; 494 495 /* 496 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and 497 * 1 u32 CONFIG, so 24 types in total for each pin. 498 */ 499 #define FSL_PIN_SIZE 24 500 #define SHARE_FSL_PIN_SIZE 20 501 502 static int imx_pinctrl_parse_groups(struct device_node *np, 503 struct imx_pin_group *grp, 504 struct imx_pinctrl_soc_info *info, 505 u32 index) 506 { 507 int size, pin_size; 508 const __be32 *list; 509 int i; 510 u32 config; 511 512 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 513 514 if (info->flags & SHARE_MUX_CONF_REG) 515 pin_size = SHARE_FSL_PIN_SIZE; 516 else 517 pin_size = FSL_PIN_SIZE; 518 /* Initialise group */ 519 grp->name = np->name; 520 521 /* 522 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 523 * do sanity check and calculate pins number 524 */ 525 list = of_get_property(np, "fsl,pins", &size); 526 if (!list) { 527 dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); 528 return -EINVAL; 529 } 530 531 /* we do not check return since it's safe node passed down */ 532 if (!size || size % pin_size) { 533 dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); 534 return -EINVAL; 535 } 536 537 grp->npins = size / pin_size; 538 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(struct imx_pin), 539 GFP_KERNEL); 540 grp->pin_ids = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 541 GFP_KERNEL); 542 if (!grp->pins || ! grp->pin_ids) 543 return -ENOMEM; 544 545 for (i = 0; i < grp->npins; i++) { 546 u32 mux_reg = be32_to_cpu(*list++); 547 u32 conf_reg; 548 unsigned int pin_id; 549 struct imx_pin_reg *pin_reg; 550 struct imx_pin *pin = &grp->pins[i]; 551 552 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 553 mux_reg = -1; 554 555 if (info->flags & SHARE_MUX_CONF_REG) { 556 conf_reg = mux_reg; 557 } else { 558 conf_reg = be32_to_cpu(*list++); 559 if (!conf_reg) 560 conf_reg = -1; 561 } 562 563 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 564 pin_reg = &info->pin_regs[pin_id]; 565 pin->pin = pin_id; 566 grp->pin_ids[i] = pin_id; 567 pin_reg->mux_reg = mux_reg; 568 pin_reg->conf_reg = conf_reg; 569 pin->input_reg = be32_to_cpu(*list++); 570 pin->mux_mode = be32_to_cpu(*list++); 571 pin->input_val = be32_to_cpu(*list++); 572 573 /* SION bit is in mux register */ 574 config = be32_to_cpu(*list++); 575 if (config & IMX_PAD_SION) 576 pin->mux_mode |= IOMUXC_CONFIG_SION; 577 pin->config = config & ~IMX_PAD_SION; 578 579 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, 580 pin->mux_mode, pin->config); 581 } 582 583 return 0; 584 } 585 586 static int imx_pinctrl_parse_functions(struct device_node *np, 587 struct imx_pinctrl_soc_info *info, 588 u32 index) 589 { 590 struct device_node *child; 591 struct imx_pmx_func *func; 592 struct imx_pin_group *grp; 593 u32 i = 0; 594 595 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 596 597 func = &info->functions[index]; 598 599 /* Initialise function */ 600 func->name = np->name; 601 func->num_groups = of_get_child_count(np); 602 if (func->num_groups == 0) { 603 dev_err(info->dev, "no groups defined in %s\n", np->full_name); 604 return -EINVAL; 605 } 606 func->groups = devm_kzalloc(info->dev, 607 func->num_groups * sizeof(char *), GFP_KERNEL); 608 609 for_each_child_of_node(np, child) { 610 func->groups[i] = child->name; 611 grp = &info->groups[info->group_index++]; 612 imx_pinctrl_parse_groups(child, grp, info, i++); 613 } 614 615 return 0; 616 } 617 618 /* 619 * Check if the DT contains pins in the direct child nodes. This indicates the 620 * newer DT format to store pins. This function returns true if the first found 621 * fsl,pins property is in a child of np. Otherwise false is returned. 622 */ 623 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 624 { 625 struct device_node *function_np; 626 struct device_node *pinctrl_np; 627 628 for_each_child_of_node(np, function_np) { 629 if (of_property_read_bool(function_np, "fsl,pins")) 630 return true; 631 632 for_each_child_of_node(function_np, pinctrl_np) { 633 if (of_property_read_bool(pinctrl_np, "fsl,pins")) 634 return false; 635 } 636 } 637 638 return true; 639 } 640 641 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 642 struct imx_pinctrl_soc_info *info) 643 { 644 struct device_node *np = pdev->dev.of_node; 645 struct device_node *child; 646 u32 nfuncs = 0; 647 u32 i = 0; 648 bool flat_funcs; 649 650 if (!np) 651 return -ENODEV; 652 653 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 654 if (flat_funcs) { 655 nfuncs = 1; 656 } else { 657 nfuncs = of_get_child_count(np); 658 if (nfuncs <= 0) { 659 dev_err(&pdev->dev, "no functions defined\n"); 660 return -EINVAL; 661 } 662 } 663 664 info->nfunctions = nfuncs; 665 info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), 666 GFP_KERNEL); 667 if (!info->functions) 668 return -ENOMEM; 669 670 if (flat_funcs) { 671 info->ngroups = of_get_child_count(np); 672 } else { 673 info->ngroups = 0; 674 for_each_child_of_node(np, child) 675 info->ngroups += of_get_child_count(child); 676 } 677 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), 678 GFP_KERNEL); 679 if (!info->groups) 680 return -ENOMEM; 681 682 if (flat_funcs) { 683 imx_pinctrl_parse_functions(np, info, 0); 684 } else { 685 for_each_child_of_node(np, child) 686 imx_pinctrl_parse_functions(child, info, i++); 687 } 688 689 return 0; 690 } 691 692 int imx_pinctrl_probe(struct platform_device *pdev, 693 struct imx_pinctrl_soc_info *info) 694 { 695 struct device_node *dev_np = pdev->dev.of_node; 696 struct device_node *np; 697 struct imx_pinctrl *ipctl; 698 struct resource *res; 699 int ret, i; 700 701 if (!info || !info->pins || !info->npins) { 702 dev_err(&pdev->dev, "wrong pinctrl info\n"); 703 return -EINVAL; 704 } 705 info->dev = &pdev->dev; 706 707 /* Create state holders etc for this driver */ 708 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 709 if (!ipctl) 710 return -ENOMEM; 711 712 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) * 713 info->npins, GFP_KERNEL); 714 if (!info->pin_regs) 715 return -ENOMEM; 716 717 for (i = 0; i < info->npins; i++) { 718 info->pin_regs[i].mux_reg = -1; 719 info->pin_regs[i].conf_reg = -1; 720 } 721 722 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 723 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 724 if (IS_ERR(ipctl->base)) 725 return PTR_ERR(ipctl->base); 726 727 if (of_property_read_bool(dev_np, "fsl,input-sel")) { 728 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); 729 if (np) { 730 ipctl->input_sel_base = of_iomap(np, 0); 731 if (IS_ERR(ipctl->input_sel_base)) { 732 of_node_put(np); 733 dev_err(&pdev->dev, 734 "iomuxc input select base address not found\n"); 735 return PTR_ERR(ipctl->input_sel_base); 736 } 737 } else { 738 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); 739 return -EINVAL; 740 } 741 of_node_put(np); 742 } 743 744 imx_pinctrl_desc.name = dev_name(&pdev->dev); 745 imx_pinctrl_desc.pins = info->pins; 746 imx_pinctrl_desc.npins = info->npins; 747 748 ret = imx_pinctrl_probe_dt(pdev, info); 749 if (ret) { 750 dev_err(&pdev->dev, "fail to probe dt properties\n"); 751 return ret; 752 } 753 754 ipctl->info = info; 755 ipctl->dev = info->dev; 756 platform_set_drvdata(pdev, ipctl); 757 ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); 758 if (IS_ERR(ipctl->pctl)) { 759 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 760 return PTR_ERR(ipctl->pctl); 761 } 762 763 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 764 765 return 0; 766 } 767 768 int imx_pinctrl_remove(struct platform_device *pdev) 769 { 770 struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); 771 772 pinctrl_unregister(ipctl->pctl); 773 774 return 0; 775 } 776