1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Core driver for the imx pin controller 4 // 5 // Copyright (C) 2012 Freescale Semiconductor, Inc. 6 // Copyright (C) 2012 Linaro Ltd. 7 // 8 // Author: Dong Aisheng <dong.aisheng@linaro.org> 9 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/regmap.h> 19 #include <linux/seq_file.h> 20 #include <linux/slab.h> 21 22 #include <linux/pinctrl/machine.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include "../core.h" 28 #include "../pinconf.h" 29 #include "../pinmux.h" 30 #include "pinctrl-imx.h" 31 32 /* The bits in CONFIG cell defined in binding doc*/ 33 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ 34 #define IMX_PAD_SION 0x40000000 /* set SION */ 35 36 static inline const struct group_desc *imx_pinctrl_find_group_by_name( 37 struct pinctrl_dev *pctldev, 38 const char *name) 39 { 40 const struct group_desc *grp = NULL; 41 int i; 42 43 for (i = 0; i < pctldev->num_groups; i++) { 44 grp = pinctrl_generic_get_group(pctldev, i); 45 if (grp && !strcmp(grp->name, name)) 46 break; 47 } 48 49 return grp; 50 } 51 52 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 53 unsigned offset) 54 { 55 seq_printf(s, "%s", dev_name(pctldev->dev)); 56 } 57 58 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, 59 struct device_node *np, 60 struct pinctrl_map **map, unsigned *num_maps) 61 { 62 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 63 const struct imx_pinctrl_soc_info *info = ipctl->info; 64 const struct group_desc *grp; 65 struct pinctrl_map *new_map; 66 struct device_node *parent; 67 struct imx_pin *pin; 68 int map_num = 1; 69 int i, j; 70 71 /* 72 * first find the group of this node and check if we need create 73 * config maps for pins 74 */ 75 grp = imx_pinctrl_find_group_by_name(pctldev, np->name); 76 if (!grp) { 77 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); 78 return -EINVAL; 79 } 80 81 if (info->flags & IMX_USE_SCU) { 82 map_num += grp->num_pins; 83 } else { 84 for (i = 0; i < grp->num_pins; i++) { 85 pin = &((struct imx_pin *)(grp->data))[i]; 86 if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) 87 map_num++; 88 } 89 } 90 91 new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), 92 GFP_KERNEL); 93 if (!new_map) 94 return -ENOMEM; 95 96 *map = new_map; 97 *num_maps = map_num; 98 99 /* create mux map */ 100 parent = of_get_parent(np); 101 if (!parent) { 102 kfree(new_map); 103 return -EINVAL; 104 } 105 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 106 new_map[0].data.mux.function = parent->name; 107 new_map[0].data.mux.group = np->name; 108 of_node_put(parent); 109 110 /* create config map */ 111 new_map++; 112 for (i = j = 0; i < grp->num_pins; i++) { 113 pin = &((struct imx_pin *)(grp->data))[i]; 114 115 /* 116 * We only create config maps for SCU pads or MMIO pads that 117 * are not using the default config(a.k.a IMX_NO_PAD_CTL) 118 */ 119 if (!(info->flags & IMX_USE_SCU) && 120 (pin->conf.mmio.config & IMX_NO_PAD_CTL)) 121 continue; 122 123 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; 124 new_map[j].data.configs.group_or_pin = 125 pin_get_name(pctldev, pin->pin); 126 127 if (info->flags & IMX_USE_SCU) { 128 /* 129 * For SCU case, we set mux and conf together 130 * in one IPC call 131 */ 132 new_map[j].data.configs.configs = 133 (unsigned long *)&pin->conf.scu; 134 new_map[j].data.configs.num_configs = 2; 135 } else { 136 new_map[j].data.configs.configs = 137 &pin->conf.mmio.config; 138 new_map[j].data.configs.num_configs = 1; 139 } 140 141 j++; 142 } 143 144 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 145 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 146 147 return 0; 148 } 149 150 static void imx_dt_free_map(struct pinctrl_dev *pctldev, 151 struct pinctrl_map *map, unsigned num_maps) 152 { 153 kfree(map); 154 } 155 156 static const struct pinctrl_ops imx_pctrl_ops = { 157 .get_groups_count = pinctrl_generic_get_group_count, 158 .get_group_name = pinctrl_generic_get_group_name, 159 .get_group_pins = pinctrl_generic_get_group_pins, 160 .pin_dbg_show = imx_pin_dbg_show, 161 .dt_node_to_map = imx_dt_node_to_map, 162 .dt_free_map = imx_dt_free_map, 163 }; 164 165 static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, 166 struct imx_pin *pin) 167 { 168 const struct imx_pinctrl_soc_info *info = ipctl->info; 169 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 170 const struct imx_pin_reg *pin_reg; 171 unsigned int pin_id; 172 173 pin_id = pin->pin; 174 pin_reg = &ipctl->pin_regs[pin_id]; 175 176 if (pin_reg->mux_reg == -1) { 177 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", 178 info->pins[pin_id].name); 179 return 0; 180 } 181 182 if (info->flags & SHARE_MUX_CONF_REG) { 183 u32 reg; 184 185 reg = readl(ipctl->base + pin_reg->mux_reg); 186 reg &= ~info->mux_mask; 187 reg |= (pin_mmio->mux_mode << info->mux_shift); 188 writel(reg, ipctl->base + pin_reg->mux_reg); 189 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 190 pin_reg->mux_reg, reg); 191 } else { 192 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); 193 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 194 pin_reg->mux_reg, pin_mmio->mux_mode); 195 } 196 197 /* 198 * If the select input value begins with 0xff, it's a quirky 199 * select input and the value should be interpreted as below. 200 * 31 23 15 7 0 201 * | 0xff | shift | width | select | 202 * It's used to work around the problem that the select 203 * input for some pin is not implemented in the select 204 * input register but in some general purpose register. 205 * We encode the select input value, width and shift of 206 * the bit field into input_val cell of pin function ID 207 * in device tree, and then decode them here for setting 208 * up the select input bits in general purpose register. 209 */ 210 if (pin_mmio->input_val >> 24 == 0xff) { 211 u32 val = pin_mmio->input_val; 212 u8 select = val & 0xff; 213 u8 width = (val >> 8) & 0xff; 214 u8 shift = (val >> 16) & 0xff; 215 u32 mask = ((1 << width) - 1) << shift; 216 /* 217 * The input_reg[i] here is actually some IOMUXC general 218 * purpose register, not regular select input register. 219 */ 220 val = readl(ipctl->base + pin_mmio->input_reg); 221 val &= ~mask; 222 val |= select << shift; 223 writel(val, ipctl->base + pin_mmio->input_reg); 224 } else if (pin_mmio->input_reg) { 225 /* 226 * Regular select input register can never be at offset 227 * 0, and we only print register value for regular case. 228 */ 229 if (ipctl->input_sel_base) 230 writel(pin_mmio->input_val, ipctl->input_sel_base + 231 pin_mmio->input_reg); 232 else 233 writel(pin_mmio->input_val, ipctl->base + 234 pin_mmio->input_reg); 235 dev_dbg(ipctl->dev, 236 "==>select_input: offset 0x%x val 0x%x\n", 237 pin_mmio->input_reg, pin_mmio->input_val); 238 } 239 240 return 0; 241 } 242 243 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 244 unsigned group) 245 { 246 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 247 const struct imx_pinctrl_soc_info *info = ipctl->info; 248 struct function_desc *func; 249 struct group_desc *grp; 250 struct imx_pin *pin; 251 unsigned int npins; 252 int i, err; 253 254 /* 255 * Configure the mux mode for each pin in the group for a specific 256 * function. 257 */ 258 grp = pinctrl_generic_get_group(pctldev, group); 259 if (!grp) 260 return -EINVAL; 261 262 func = pinmux_generic_get_function(pctldev, selector); 263 if (!func) 264 return -EINVAL; 265 266 npins = grp->num_pins; 267 268 dev_dbg(ipctl->dev, "enable function %s group %s\n", 269 func->name, grp->name); 270 271 for (i = 0; i < npins; i++) { 272 /* 273 * For IMX_USE_SCU case, we postpone the mux setting 274 * until config is set as we can set them together 275 * in one IPC call 276 */ 277 pin = &((struct imx_pin *)(grp->data))[i]; 278 if (!(info->flags & IMX_USE_SCU)) { 279 err = imx_pmx_set_one_pin_mmio(ipctl, pin); 280 if (err) 281 return err; 282 } 283 } 284 285 return 0; 286 } 287 288 struct pinmux_ops imx_pmx_ops = { 289 .get_functions_count = pinmux_generic_get_function_count, 290 .get_function_name = pinmux_generic_get_function_name, 291 .get_function_groups = pinmux_generic_get_function_groups, 292 .set_mux = imx_pmx_set, 293 }; 294 295 /* decode generic config into raw register values */ 296 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, 297 unsigned long *configs, 298 unsigned int num_configs) 299 { 300 const struct imx_pinctrl_soc_info *info = ipctl->info; 301 const struct imx_cfg_params_decode *decode; 302 enum pin_config_param param; 303 u32 raw_config = 0; 304 u32 param_val; 305 int i, j; 306 307 WARN_ON(num_configs > info->num_decodes); 308 309 for (i = 0; i < num_configs; i++) { 310 param = pinconf_to_config_param(configs[i]); 311 param_val = pinconf_to_config_argument(configs[i]); 312 decode = info->decodes; 313 for (j = 0; j < info->num_decodes; j++) { 314 if (param == decode->param) { 315 if (decode->invert) 316 param_val = !param_val; 317 raw_config |= (param_val << decode->shift) 318 & decode->mask; 319 break; 320 } 321 decode++; 322 } 323 } 324 325 if (info->fixup) 326 info->fixup(configs, num_configs, &raw_config); 327 328 return raw_config; 329 } 330 331 static u32 imx_pinconf_parse_generic_config(struct device_node *np, 332 struct imx_pinctrl *ipctl) 333 { 334 const struct imx_pinctrl_soc_info *info = ipctl->info; 335 struct pinctrl_dev *pctl = ipctl->pctl; 336 unsigned int num_configs; 337 unsigned long *configs; 338 int ret; 339 340 if (!info->generic_pinconf) 341 return 0; 342 343 ret = pinconf_generic_parse_dt_config(np, pctl, &configs, 344 &num_configs); 345 if (ret) 346 return 0; 347 348 return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); 349 } 350 351 static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, 352 unsigned long *config) 353 { 354 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 355 const struct imx_pinctrl_soc_info *info = ipctl->info; 356 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 357 358 if (pin_reg->conf_reg == -1) { 359 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 360 info->pins[pin_id].name); 361 return -EINVAL; 362 } 363 364 *config = readl(ipctl->base + pin_reg->conf_reg); 365 366 if (info->flags & SHARE_MUX_CONF_REG) 367 *config &= ~info->mux_mask; 368 369 return 0; 370 } 371 372 static int imx_pinconf_get(struct pinctrl_dev *pctldev, 373 unsigned pin_id, unsigned long *config) 374 { 375 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 376 const struct imx_pinctrl_soc_info *info = ipctl->info; 377 378 if (info->flags & IMX_USE_SCU) 379 return info->imx_pinconf_get(pctldev, pin_id, config); 380 else 381 return imx_pinconf_get_mmio(pctldev, pin_id, config); 382 } 383 384 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, 385 unsigned pin_id, unsigned long *configs, 386 unsigned num_configs) 387 { 388 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 389 const struct imx_pinctrl_soc_info *info = ipctl->info; 390 const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; 391 int i; 392 393 if (pin_reg->conf_reg == -1) { 394 dev_err(ipctl->dev, "Pin(%s) does not support config function\n", 395 info->pins[pin_id].name); 396 return -EINVAL; 397 } 398 399 dev_dbg(ipctl->dev, "pinconf set pin %s\n", 400 info->pins[pin_id].name); 401 402 for (i = 0; i < num_configs; i++) { 403 if (info->flags & SHARE_MUX_CONF_REG) { 404 u32 reg; 405 reg = readl(ipctl->base + pin_reg->conf_reg); 406 reg &= info->mux_mask; 407 reg |= configs[i]; 408 writel(reg, ipctl->base + pin_reg->conf_reg); 409 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", 410 pin_reg->conf_reg, reg); 411 } else { 412 writel(configs[i], ipctl->base + pin_reg->conf_reg); 413 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", 414 pin_reg->conf_reg, configs[i]); 415 } 416 } /* for each config */ 417 418 return 0; 419 } 420 421 static int imx_pinconf_set(struct pinctrl_dev *pctldev, 422 unsigned pin_id, unsigned long *configs, 423 unsigned num_configs) 424 { 425 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 426 const struct imx_pinctrl_soc_info *info = ipctl->info; 427 428 if (info->flags & IMX_USE_SCU) 429 return info->imx_pinconf_set(pctldev, pin_id, 430 configs, num_configs); 431 else 432 return imx_pinconf_set_mmio(pctldev, pin_id, 433 configs, num_configs); 434 } 435 436 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 437 struct seq_file *s, unsigned pin_id) 438 { 439 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 440 const struct imx_pinctrl_soc_info *info = ipctl->info; 441 const struct imx_pin_reg *pin_reg; 442 unsigned long config; 443 int ret; 444 445 if (info->flags & IMX_USE_SCU) { 446 ret = info->imx_pinconf_get(pctldev, pin_id, &config); 447 if (ret) { 448 dev_err(ipctl->dev, "failed to get %s pinconf\n", 449 pin_get_name(pctldev, pin_id)); 450 seq_puts(s, "N/A"); 451 return; 452 } 453 } else { 454 pin_reg = &ipctl->pin_regs[pin_id]; 455 if (pin_reg->conf_reg == -1) { 456 seq_puts(s, "N/A"); 457 return; 458 } 459 460 config = readl(ipctl->base + pin_reg->conf_reg); 461 } 462 463 seq_printf(s, "0x%lx", config); 464 } 465 466 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 467 struct seq_file *s, unsigned group) 468 { 469 struct group_desc *grp; 470 unsigned long config; 471 const char *name; 472 int i, ret; 473 474 if (group >= pctldev->num_groups) 475 return; 476 477 seq_puts(s, "\n"); 478 grp = pinctrl_generic_get_group(pctldev, group); 479 if (!grp) 480 return; 481 482 for (i = 0; i < grp->num_pins; i++) { 483 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; 484 485 name = pin_get_name(pctldev, pin->pin); 486 ret = imx_pinconf_get(pctldev, pin->pin, &config); 487 if (ret) 488 return; 489 seq_printf(s, " %s: 0x%lx\n", name, config); 490 } 491 } 492 493 static const struct pinconf_ops imx_pinconf_ops = { 494 .pin_config_get = imx_pinconf_get, 495 .pin_config_set = imx_pinconf_set, 496 .pin_config_dbg_show = imx_pinconf_dbg_show, 497 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, 498 }; 499 500 /* 501 * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID 502 * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin. 503 * For generic_pinconf case, there's no extra u32 CONFIG. 504 * 505 * PIN_FUNC_ID format: 506 * Default: 507 * <mux_reg conf_reg input_reg mux_mode input_val> 508 * SHARE_MUX_CONF_REG: 509 * <mux_conf_reg input_reg mux_mode input_val> 510 * IMX_USE_SCU: 511 * <pin_id mux_mode> 512 */ 513 #define FSL_PIN_SIZE 24 514 #define FSL_PIN_SHARE_SIZE 20 515 #define FSL_SCU_PIN_SIZE 12 516 517 static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, 518 unsigned int *pin_id, struct imx_pin *pin, 519 const __be32 **list_p, 520 struct device_node *np) 521 { 522 const struct imx_pinctrl_soc_info *info = ipctl->info; 523 struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; 524 struct imx_pin_reg *pin_reg; 525 const __be32 *list = *list_p; 526 u32 mux_reg, conf_reg; 527 u32 config; 528 529 mux_reg = be32_to_cpu(*list++); 530 531 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) 532 mux_reg = -1; 533 534 if (info->flags & SHARE_MUX_CONF_REG) { 535 conf_reg = mux_reg; 536 } else { 537 conf_reg = be32_to_cpu(*list++); 538 if (!conf_reg) 539 conf_reg = -1; 540 } 541 542 *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; 543 pin_reg = &ipctl->pin_regs[*pin_id]; 544 pin->pin = *pin_id; 545 pin_reg->mux_reg = mux_reg; 546 pin_reg->conf_reg = conf_reg; 547 pin_mmio->input_reg = be32_to_cpu(*list++); 548 pin_mmio->mux_mode = be32_to_cpu(*list++); 549 pin_mmio->input_val = be32_to_cpu(*list++); 550 551 if (info->generic_pinconf) { 552 /* generic pin config decoded */ 553 pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl); 554 } else { 555 /* legacy pin config read from devicetree */ 556 config = be32_to_cpu(*list++); 557 558 /* SION bit is in mux register */ 559 if (config & IMX_PAD_SION) 560 pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; 561 pin_mmio->config = config & ~IMX_PAD_SION; 562 } 563 564 *list_p = list; 565 566 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, 567 pin_mmio->mux_mode, pin_mmio->config); 568 } 569 570 static int imx_pinctrl_parse_groups(struct device_node *np, 571 struct group_desc *grp, 572 struct imx_pinctrl *ipctl, 573 u32 index) 574 { 575 const struct imx_pinctrl_soc_info *info = ipctl->info; 576 struct imx_pin *pin; 577 int size, pin_size; 578 const __be32 *list; 579 int i; 580 581 dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np); 582 583 if (info->flags & IMX_USE_SCU) 584 pin_size = FSL_SCU_PIN_SIZE; 585 else if (info->flags & SHARE_MUX_CONF_REG) 586 pin_size = FSL_PIN_SHARE_SIZE; 587 else 588 pin_size = FSL_PIN_SIZE; 589 590 if (info->generic_pinconf) 591 pin_size -= 4; 592 593 /* Initialise group */ 594 grp->name = np->name; 595 596 /* 597 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, 598 * do sanity check and calculate pins number 599 * 600 * First try legacy 'fsl,pins' property, then fall back to the 601 * generic 'pinmux'. 602 * 603 * Note: for generic 'pinmux' case, there's no CONFIG part in 604 * the binding format. 605 */ 606 list = of_get_property(np, "fsl,pins", &size); 607 if (!list) { 608 list = of_get_property(np, "pinmux", &size); 609 if (!list) { 610 dev_err(ipctl->dev, 611 "no fsl,pins and pins property in node %pOF\n", np); 612 return -EINVAL; 613 } 614 } 615 616 /* we do not check return since it's safe node passed down */ 617 if (!size || size % pin_size) { 618 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); 619 return -EINVAL; 620 } 621 622 grp->num_pins = size / pin_size; 623 grp->data = devm_kcalloc(ipctl->dev, 624 grp->num_pins, sizeof(struct imx_pin), 625 GFP_KERNEL); 626 grp->pins = devm_kcalloc(ipctl->dev, 627 grp->num_pins, sizeof(unsigned int), 628 GFP_KERNEL); 629 if (!grp->pins || !grp->data) 630 return -ENOMEM; 631 632 for (i = 0; i < grp->num_pins; i++) { 633 pin = &((struct imx_pin *)(grp->data))[i]; 634 if (info->flags & IMX_USE_SCU) 635 info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i], 636 pin, &list); 637 else 638 imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i], 639 pin, &list, np); 640 } 641 642 return 0; 643 } 644 645 static int imx_pinctrl_parse_functions(struct device_node *np, 646 struct imx_pinctrl *ipctl, 647 u32 index) 648 { 649 struct pinctrl_dev *pctl = ipctl->pctl; 650 struct device_node *child; 651 struct function_desc *func; 652 struct group_desc *grp; 653 const char **group_names; 654 u32 i; 655 656 dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); 657 658 func = pinmux_generic_get_function(pctl, index); 659 if (!func) 660 return -EINVAL; 661 662 /* Initialise function */ 663 func->name = np->name; 664 func->num_group_names = of_get_child_count(np); 665 if (func->num_group_names == 0) { 666 dev_info(ipctl->dev, "no groups defined in %pOF\n", np); 667 return -EINVAL; 668 } 669 670 group_names = devm_kcalloc(ipctl->dev, func->num_group_names, 671 sizeof(char *), GFP_KERNEL); 672 if (!group_names) 673 return -ENOMEM; 674 i = 0; 675 for_each_child_of_node(np, child) 676 group_names[i++] = child->name; 677 func->group_names = group_names; 678 679 i = 0; 680 for_each_child_of_node(np, child) { 681 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), 682 GFP_KERNEL); 683 if (!grp) { 684 of_node_put(child); 685 return -ENOMEM; 686 } 687 688 mutex_lock(&ipctl->mutex); 689 radix_tree_insert(&pctl->pin_group_tree, 690 ipctl->group_index++, grp); 691 mutex_unlock(&ipctl->mutex); 692 693 imx_pinctrl_parse_groups(child, grp, ipctl, i++); 694 } 695 696 return 0; 697 } 698 699 /* 700 * Check if the DT contains pins in the direct child nodes. This indicates the 701 * newer DT format to store pins. This function returns true if the first found 702 * fsl,pins property is in a child of np. Otherwise false is returned. 703 */ 704 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) 705 { 706 struct device_node *function_np; 707 struct device_node *pinctrl_np; 708 709 for_each_child_of_node(np, function_np) { 710 if (of_property_read_bool(function_np, "fsl,pins")) { 711 of_node_put(function_np); 712 return true; 713 } 714 715 for_each_child_of_node(function_np, pinctrl_np) { 716 if (of_property_read_bool(pinctrl_np, "fsl,pins")) { 717 of_node_put(pinctrl_np); 718 of_node_put(function_np); 719 return false; 720 } 721 } 722 } 723 724 return true; 725 } 726 727 static int imx_pinctrl_probe_dt(struct platform_device *pdev, 728 struct imx_pinctrl *ipctl) 729 { 730 struct device_node *np = pdev->dev.of_node; 731 struct device_node *child; 732 struct pinctrl_dev *pctl = ipctl->pctl; 733 u32 nfuncs = 0; 734 u32 i = 0; 735 bool flat_funcs; 736 737 if (!np) 738 return -ENODEV; 739 740 flat_funcs = imx_pinctrl_dt_is_flat_functions(np); 741 if (flat_funcs) { 742 nfuncs = 1; 743 } else { 744 nfuncs = of_get_child_count(np); 745 if (nfuncs == 0) { 746 dev_err(&pdev->dev, "no functions defined\n"); 747 return -EINVAL; 748 } 749 } 750 751 for (i = 0; i < nfuncs; i++) { 752 struct function_desc *function; 753 754 function = devm_kzalloc(&pdev->dev, sizeof(*function), 755 GFP_KERNEL); 756 if (!function) 757 return -ENOMEM; 758 759 mutex_lock(&ipctl->mutex); 760 radix_tree_insert(&pctl->pin_function_tree, i, function); 761 mutex_unlock(&ipctl->mutex); 762 } 763 pctl->num_functions = nfuncs; 764 765 ipctl->group_index = 0; 766 if (flat_funcs) { 767 pctl->num_groups = of_get_child_count(np); 768 } else { 769 pctl->num_groups = 0; 770 for_each_child_of_node(np, child) 771 pctl->num_groups += of_get_child_count(child); 772 } 773 774 if (flat_funcs) { 775 imx_pinctrl_parse_functions(np, ipctl, 0); 776 } else { 777 i = 0; 778 for_each_child_of_node(np, child) 779 imx_pinctrl_parse_functions(child, ipctl, i++); 780 } 781 782 return 0; 783 } 784 785 int imx_pinctrl_probe(struct platform_device *pdev, 786 const struct imx_pinctrl_soc_info *info) 787 { 788 struct regmap_config config = { .name = "gpr" }; 789 struct device_node *dev_np = pdev->dev.of_node; 790 struct pinctrl_desc *imx_pinctrl_desc; 791 struct device_node *np; 792 struct imx_pinctrl *ipctl; 793 struct regmap *gpr; 794 int ret, i; 795 796 if (!info || !info->pins || !info->npins) { 797 dev_err(&pdev->dev, "wrong pinctrl info\n"); 798 return -EINVAL; 799 } 800 801 if (info->gpr_compatible) { 802 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); 803 if (!IS_ERR(gpr)) 804 regmap_attach_dev(&pdev->dev, gpr, &config); 805 } 806 807 /* Create state holders etc for this driver */ 808 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 809 if (!ipctl) 810 return -ENOMEM; 811 812 if (!(info->flags & IMX_USE_SCU)) { 813 ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, 814 sizeof(*ipctl->pin_regs), 815 GFP_KERNEL); 816 if (!ipctl->pin_regs) 817 return -ENOMEM; 818 819 for (i = 0; i < info->npins; i++) { 820 ipctl->pin_regs[i].mux_reg = -1; 821 ipctl->pin_regs[i].conf_reg = -1; 822 } 823 824 ipctl->base = devm_platform_ioremap_resource(pdev, 0); 825 if (IS_ERR(ipctl->base)) 826 return PTR_ERR(ipctl->base); 827 828 if (of_property_read_bool(dev_np, "fsl,input-sel")) { 829 np = of_parse_phandle(dev_np, "fsl,input-sel", 0); 830 if (!np) { 831 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); 832 return -EINVAL; 833 } 834 835 ipctl->input_sel_base = of_iomap(np, 0); 836 of_node_put(np); 837 if (!ipctl->input_sel_base) { 838 dev_err(&pdev->dev, 839 "iomuxc input select base address not found\n"); 840 return -ENOMEM; 841 } 842 } 843 } 844 845 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), 846 GFP_KERNEL); 847 if (!imx_pinctrl_desc) 848 return -ENOMEM; 849 850 imx_pinctrl_desc->name = dev_name(&pdev->dev); 851 imx_pinctrl_desc->pins = info->pins; 852 imx_pinctrl_desc->npins = info->npins; 853 imx_pinctrl_desc->pctlops = &imx_pctrl_ops; 854 imx_pinctrl_desc->pmxops = &imx_pmx_ops; 855 imx_pinctrl_desc->confops = &imx_pinconf_ops; 856 imx_pinctrl_desc->owner = THIS_MODULE; 857 858 /* for generic pinconf */ 859 imx_pinctrl_desc->custom_params = info->custom_params; 860 imx_pinctrl_desc->num_custom_params = info->num_custom_params; 861 862 /* platform specific callback */ 863 imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; 864 865 mutex_init(&ipctl->mutex); 866 867 ipctl->info = info; 868 ipctl->dev = &pdev->dev; 869 platform_set_drvdata(pdev, ipctl); 870 ret = devm_pinctrl_register_and_init(&pdev->dev, 871 imx_pinctrl_desc, ipctl, 872 &ipctl->pctl); 873 if (ret) { 874 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); 875 return ret; 876 } 877 878 ret = imx_pinctrl_probe_dt(pdev, ipctl); 879 if (ret) { 880 dev_err(&pdev->dev, "fail to probe dt properties\n"); 881 return ret; 882 } 883 884 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 885 886 return pinctrl_enable(ipctl->pctl); 887 } 888 EXPORT_SYMBOL_GPL(imx_pinctrl_probe); 889 890 static int __maybe_unused imx_pinctrl_suspend(struct device *dev) 891 { 892 struct imx_pinctrl *ipctl = dev_get_drvdata(dev); 893 894 return pinctrl_force_sleep(ipctl->pctl); 895 } 896 897 static int __maybe_unused imx_pinctrl_resume(struct device *dev) 898 { 899 struct imx_pinctrl *ipctl = dev_get_drvdata(dev); 900 901 return pinctrl_force_default(ipctl->pctl); 902 } 903 904 const struct dev_pm_ops imx_pinctrl_pm_ops = { 905 SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, 906 imx_pinctrl_resume) 907 }; 908 EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops); 909 910 MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>"); 911 MODULE_DESCRIPTION("NXP i.MX common pinctrl driver"); 912 MODULE_LICENSE("GPL v2"); 913