1 /* Copyright (C) 2015 Broadcom Corporation 2 * 3 * This program is free software; you can redistribute it and/or 4 * modify it under the terms of the GNU General Public License as 5 * published by the Free Software Foundation version 2. 6 * 7 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 8 * kind, whether express or implied; without even the implied warranty 9 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * This file contains the Northstar plus (NSP) IOMUX driver that supports 13 * group based PINMUX configuration. The Northstar plus IOMUX controller 14 * allows pins to be individually muxed to GPIO function. The NAND and MMC is 15 * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm. 16 * To select PWM, one need to enable the corresponding gpio_b as well. 17 * 18 * gpio_a (8 - 11) 19 * +---------- 20 * | 21 * gpio_a (8-11) | gpio_b (0 - 3) 22 * ------------------------+-------+---------- 23 * | 24 * | pwm (0 - 3) 25 * +---------- 26 */ 27 28 #include <linux/err.h> 29 #include <linux/io.h> 30 #include <linux/of.h> 31 #include <linux/pinctrl/pinconf.h> 32 #include <linux/pinctrl/pinconf-generic.h> 33 #include <linux/pinctrl/pinctrl.h> 34 #include <linux/pinctrl/pinmux.h> 35 #include <linux/platform_device.h> 36 #include <linux/slab.h> 37 38 #include "../core.h" 39 #include "../pinctrl-utils.h" 40 41 #define NSP_MUX_BASE0 0x00 42 #define NSP_MUX_BASE1 0x01 43 #define NSP_MUX_BASE2 0x02 44 /* 45 * nsp IOMUX register description 46 * 47 * @base: base 0 or base 1 48 * @shift: bit shift for mux configuration of a group 49 * @mask: bit mask of the function 50 * @alt: alternate function to set to 51 */ 52 struct nsp_mux { 53 unsigned int base; 54 unsigned int shift; 55 unsigned int mask; 56 unsigned int alt; 57 }; 58 59 /* 60 * Keep track of nsp IOMUX configuration and prevent double configuration 61 * 62 * @nsp_mux: nsp IOMUX register description 63 * @is_configured: flag to indicate whether a mux setting has already been 64 * configured 65 */ 66 struct nsp_mux_log { 67 struct nsp_mux mux; 68 bool is_configured; 69 }; 70 71 /* 72 * Group based IOMUX configuration 73 * 74 * @name: name of the group 75 * @pins: array of pins used by this group 76 * @num_pins: total number of pins used by this group 77 * @mux: nsp group based IOMUX configuration 78 */ 79 struct nsp_pin_group { 80 const char *name; 81 const unsigned int *pins; 82 const unsigned int num_pins; 83 const struct nsp_mux mux; 84 }; 85 86 /* 87 * nsp mux function and supported pin groups 88 * 89 * @name: name of the function 90 * @groups: array of groups that can be supported by this function 91 * @num_groups: total number of groups that can be supported by this function 92 */ 93 struct nsp_pin_function { 94 const char *name; 95 const char * const *groups; 96 const unsigned int num_groups; 97 }; 98 99 /* 100 * nsp IOMUX pinctrl core 101 * 102 * @pctl: pointer to pinctrl_dev 103 * @dev: pointer to device 104 * @base0: first mux register 105 * @base1: second mux register 106 * @base2: third mux register 107 * @groups: pointer to array of groups 108 * @num_groups: total number of groups 109 * @functions: pointer to array of functions 110 * @num_functions: total number of functions 111 * @mux_log: pointer to the array of mux logs 112 * @lock: lock to protect register access 113 */ 114 struct nsp_pinctrl { 115 struct pinctrl_dev *pctl; 116 struct device *dev; 117 void __iomem *base0; 118 void __iomem *base1; 119 void __iomem *base2; 120 const struct nsp_pin_group *groups; 121 unsigned int num_groups; 122 const struct nsp_pin_function *functions; 123 unsigned int num_functions; 124 struct nsp_mux_log *mux_log; 125 spinlock_t lock; 126 }; 127 128 /* 129 * Description of a pin in nsp 130 * 131 * @pin: pin number 132 * @name: pin name 133 * @gpio_select: reg data to select GPIO 134 */ 135 struct nsp_pin { 136 unsigned int pin; 137 char *name; 138 unsigned int gpio_select; 139 }; 140 141 #define NSP_PIN_DESC(p, n, g) \ 142 { \ 143 .pin = p, \ 144 .name = n, \ 145 .gpio_select = g, \ 146 } 147 148 /* 149 * List of muxable pins in nsp 150 */ 151 static struct nsp_pin nsp_pins[] = { 152 NSP_PIN_DESC(0, "spi_clk", 1), 153 NSP_PIN_DESC(1, "spi_ss", 1), 154 NSP_PIN_DESC(2, "spi_mosi", 1), 155 NSP_PIN_DESC(3, "spi_miso", 1), 156 NSP_PIN_DESC(4, "scl", 1), 157 NSP_PIN_DESC(5, "sda", 1), 158 NSP_PIN_DESC(6, "mdc", 1), 159 NSP_PIN_DESC(7, "mdio", 1), 160 NSP_PIN_DESC(8, "pwm0", 1), 161 NSP_PIN_DESC(9, "pwm1", 1), 162 NSP_PIN_DESC(10, "pwm2", 1), 163 NSP_PIN_DESC(11, "pwm3", 1), 164 NSP_PIN_DESC(12, "uart1_rx", 1), 165 NSP_PIN_DESC(13, "uart1_tx", 1), 166 NSP_PIN_DESC(14, "uart1_cts", 1), 167 NSP_PIN_DESC(15, "uart1_rts", 1), 168 NSP_PIN_DESC(16, "uart2_rx", 1), 169 NSP_PIN_DESC(17, "uart2_tx", 1), 170 NSP_PIN_DESC(18, "synce", 0), 171 NSP_PIN_DESC(19, "sata0_led", 0), 172 NSP_PIN_DESC(20, "sata1_led", 0), 173 NSP_PIN_DESC(21, "xtal_out", 1), 174 NSP_PIN_DESC(22, "sdio_pwr", 1), 175 NSP_PIN_DESC(23, "sdio_en_1p8v", 1), 176 NSP_PIN_DESC(24, "gpio_24", 1), 177 NSP_PIN_DESC(25, "gpio_25", 1), 178 NSP_PIN_DESC(26, "p5_led0", 0), 179 NSP_PIN_DESC(27, "p5_led1", 0), 180 NSP_PIN_DESC(28, "gpio_28", 1), 181 NSP_PIN_DESC(29, "gpio_29", 1), 182 NSP_PIN_DESC(30, "gpio_30", 1), 183 NSP_PIN_DESC(31, "gpio_31", 1), 184 NSP_PIN_DESC(32, "nand_ale", 0), 185 NSP_PIN_DESC(33, "nand_ce0", 0), 186 NSP_PIN_DESC(34, "nand_r/b", 0), 187 NSP_PIN_DESC(35, "nand_dq0", 0), 188 NSP_PIN_DESC(36, "nand_dq1", 0), 189 NSP_PIN_DESC(37, "nand_dq2", 0), 190 NSP_PIN_DESC(38, "nand_dq3", 0), 191 NSP_PIN_DESC(39, "nand_dq4", 0), 192 NSP_PIN_DESC(40, "nand_dq5", 0), 193 NSP_PIN_DESC(41, "nand_dq6", 0), 194 NSP_PIN_DESC(42, "nand_dq7", 0), 195 }; 196 197 /* 198 * List of groups of pins 199 */ 200 201 static const unsigned int spi_pins[] = {0, 1, 2, 3}; 202 static const unsigned int i2c_pins[] = {4, 5}; 203 static const unsigned int mdio_pins[] = {6, 7}; 204 static const unsigned int pwm0_pins[] = {8}; 205 static const unsigned int gpio_b_0_pins[] = {8}; 206 static const unsigned int pwm1_pins[] = {9}; 207 static const unsigned int gpio_b_1_pins[] = {9}; 208 static const unsigned int pwm2_pins[] = {10}; 209 static const unsigned int gpio_b_2_pins[] = {10}; 210 static const unsigned int pwm3_pins[] = {11}; 211 static const unsigned int gpio_b_3_pins[] = {11}; 212 static const unsigned int uart1_pins[] = {12, 13, 14, 15}; 213 static const unsigned int uart2_pins[] = {16, 17}; 214 static const unsigned int synce_pins[] = {18}; 215 static const unsigned int sata0_led_pins[] = {19}; 216 static const unsigned int sata1_led_pins[] = {20}; 217 static const unsigned int xtal_out_pins[] = {21}; 218 static const unsigned int sdio_pwr_pins[] = {22}; 219 static const unsigned int sdio_1p8v_pins[] = {23}; 220 static const unsigned int switch_p05_led0_pins[] = {26}; 221 static const unsigned int switch_p05_led1_pins[] = {27}; 222 static const unsigned int nand_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 223 40, 41, 42}; 224 static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 225 40, 41, 42}; 226 227 #define NSP_PIN_GROUP(group_name, ba, sh, ma, al) \ 228 { \ 229 .name = __stringify(group_name) "_grp", \ 230 .pins = group_name ## _pins, \ 231 .num_pins = ARRAY_SIZE(group_name ## _pins), \ 232 .mux = { \ 233 .base = ba, \ 234 .shift = sh, \ 235 .mask = ma, \ 236 .alt = al, \ 237 } \ 238 } 239 240 /* 241 * List of nsp pin groups 242 */ 243 static const struct nsp_pin_group nsp_pin_groups[] = { 244 NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00), 245 NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00), 246 NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00), 247 NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00), 248 NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01), 249 NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00), 250 NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01), 251 NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00), 252 NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01), 253 NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00), 254 NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01), 255 NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00), 256 NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00), 257 NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01), 258 NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01), 259 NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01), 260 NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00), 261 NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00), 262 NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00), 263 NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01), 264 NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01), 265 NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00), 266 NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01) 267 }; 268 269 /* 270 * List of groups supported by functions 271 */ 272 273 static const char * const spi_grps[] = {"spi_grp"}; 274 static const char * const i2c_grps[] = {"i2c_grp"}; 275 static const char * const mdio_grps[] = {"mdio_grp"}; 276 static const char * const pwm_grps[] = {"pwm0_grp", "pwm1_grp", "pwm2_grp" 277 , "pwm3_grp"}; 278 static const char * const gpio_b_grps[] = {"gpio_b_0_grp", "gpio_b_1_grp", 279 "gpio_b_2_grp", "gpio_b_3_grp"}; 280 static const char * const uart1_grps[] = {"uart1_grp"}; 281 static const char * const uart2_grps[] = {"uart2_grp"}; 282 static const char * const synce_grps[] = {"synce_grp"}; 283 static const char * const sata_led_grps[] = {"sata0_led_grp", "sata1_led_grp"}; 284 static const char * const xtal_out_grps[] = {"xtal_out_grp"}; 285 static const char * const sdio_grps[] = {"sdio_pwr_grp", "sdio_1p8v_grp"}; 286 static const char * const switch_led_grps[] = {"switch_p05_led0_grp", 287 "switch_p05_led1_grp"}; 288 static const char * const nand_grps[] = {"nand_grp"}; 289 static const char * const emmc_grps[] = {"emmc_grp"}; 290 291 #define NSP_PIN_FUNCTION(func) \ 292 { \ 293 .name = #func, \ 294 .groups = func ## _grps, \ 295 .num_groups = ARRAY_SIZE(func ## _grps), \ 296 } 297 298 /* 299 * List of supported functions in nsp 300 */ 301 static const struct nsp_pin_function nsp_pin_functions[] = { 302 NSP_PIN_FUNCTION(spi), 303 NSP_PIN_FUNCTION(i2c), 304 NSP_PIN_FUNCTION(mdio), 305 NSP_PIN_FUNCTION(pwm), 306 NSP_PIN_FUNCTION(gpio_b), 307 NSP_PIN_FUNCTION(uart1), 308 NSP_PIN_FUNCTION(uart2), 309 NSP_PIN_FUNCTION(synce), 310 NSP_PIN_FUNCTION(sata_led), 311 NSP_PIN_FUNCTION(xtal_out), 312 NSP_PIN_FUNCTION(sdio), 313 NSP_PIN_FUNCTION(switch_led), 314 NSP_PIN_FUNCTION(nand), 315 NSP_PIN_FUNCTION(emmc) 316 }; 317 318 static int nsp_get_groups_count(struct pinctrl_dev *pctrl_dev) 319 { 320 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 321 322 return pinctrl->num_groups; 323 } 324 325 static const char *nsp_get_group_name(struct pinctrl_dev *pctrl_dev, 326 unsigned int selector) 327 { 328 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 329 330 return pinctrl->groups[selector].name; 331 } 332 333 static int nsp_get_group_pins(struct pinctrl_dev *pctrl_dev, 334 unsigned int selector, const unsigned int **pins, 335 unsigned int *num_pins) 336 { 337 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 338 339 *pins = pinctrl->groups[selector].pins; 340 *num_pins = pinctrl->groups[selector].num_pins; 341 342 return 0; 343 } 344 345 static void nsp_pin_dbg_show(struct pinctrl_dev *pctrl_dev, 346 struct seq_file *s, unsigned int offset) 347 { 348 seq_printf(s, " %s", dev_name(pctrl_dev->dev)); 349 } 350 351 static struct pinctrl_ops nsp_pinctrl_ops = { 352 .get_groups_count = nsp_get_groups_count, 353 .get_group_name = nsp_get_group_name, 354 .get_group_pins = nsp_get_group_pins, 355 .pin_dbg_show = nsp_pin_dbg_show, 356 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 357 .dt_free_map = pinctrl_utils_free_map, 358 }; 359 360 static int nsp_get_functions_count(struct pinctrl_dev *pctrl_dev) 361 { 362 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 363 364 return pinctrl->num_functions; 365 } 366 367 static const char *nsp_get_function_name(struct pinctrl_dev *pctrl_dev, 368 unsigned int selector) 369 { 370 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 371 372 return pinctrl->functions[selector].name; 373 } 374 375 static int nsp_get_function_groups(struct pinctrl_dev *pctrl_dev, 376 unsigned int selector, 377 const char * const **groups, 378 unsigned * const num_groups) 379 { 380 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 381 382 *groups = pinctrl->functions[selector].groups; 383 *num_groups = pinctrl->functions[selector].num_groups; 384 385 return 0; 386 } 387 388 static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl, 389 const struct nsp_pin_function *func, 390 const struct nsp_pin_group *grp, 391 struct nsp_mux_log *mux_log) 392 { 393 const struct nsp_mux *mux = &grp->mux; 394 int i; 395 u32 val, mask; 396 unsigned long flags; 397 void __iomem *base_address; 398 399 for (i = 0; i < pinctrl->num_groups; i++) { 400 if ((mux->shift != mux_log[i].mux.shift) || 401 (mux->base != mux_log[i].mux.base)) 402 continue; 403 404 /* if this is a new configuration, just do it! */ 405 if (!mux_log[i].is_configured) 406 break; 407 408 /* 409 * IOMUX has been configured previously and one is trying to 410 * configure it to a different function 411 */ 412 if (mux_log[i].mux.alt != mux->alt) { 413 dev_err(pinctrl->dev, 414 "double configuration error detected!\n"); 415 dev_err(pinctrl->dev, "func:%s grp:%s\n", 416 func->name, grp->name); 417 return -EINVAL; 418 } 419 420 return 0; 421 } 422 if (i == pinctrl->num_groups) 423 return -EINVAL; 424 425 mask = mux->mask; 426 mux_log[i].mux.alt = mux->alt; 427 mux_log[i].is_configured = true; 428 429 switch (mux->base) { 430 case NSP_MUX_BASE0: 431 base_address = pinctrl->base0; 432 break; 433 434 case NSP_MUX_BASE1: 435 base_address = pinctrl->base1; 436 break; 437 438 case NSP_MUX_BASE2: 439 base_address = pinctrl->base2; 440 break; 441 442 default: 443 return -EINVAL; 444 } 445 446 spin_lock_irqsave(&pinctrl->lock, flags); 447 val = readl(base_address); 448 val &= ~(mask << grp->mux.shift); 449 val |= grp->mux.alt << grp->mux.shift; 450 writel(val, base_address); 451 spin_unlock_irqrestore(&pinctrl->lock, flags); 452 453 return 0; 454 } 455 456 static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev, 457 unsigned int func_select, unsigned int grp_select) 458 { 459 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 460 const struct nsp_pin_function *func; 461 const struct nsp_pin_group *grp; 462 463 if (grp_select > pinctrl->num_groups || 464 func_select > pinctrl->num_functions) 465 return -EINVAL; 466 467 func = &pinctrl->functions[func_select]; 468 grp = &pinctrl->groups[grp_select]; 469 470 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n", 471 func_select, func->name, grp_select, grp->name); 472 473 dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift, 474 grp->mux.alt); 475 476 return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log); 477 } 478 479 480 static int nsp_gpio_request_enable(struct pinctrl_dev *pctrl_dev, 481 struct pinctrl_gpio_range *range, 482 unsigned int pin) 483 { 484 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 485 u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data; 486 u32 val; 487 unsigned long flags; 488 489 spin_lock_irqsave(&pinctrl->lock, flags); 490 val = readl(pinctrl->base0); 491 if ((val & BIT(pin)) != (*gpio_select << pin)) { 492 val &= ~BIT(pin); 493 val |= *gpio_select << pin; 494 writel(val, pinctrl->base0); 495 } 496 spin_unlock_irqrestore(&pinctrl->lock, flags); 497 498 return 0; 499 } 500 501 static void nsp_gpio_disable_free(struct pinctrl_dev *pctrl_dev, 502 struct pinctrl_gpio_range *range, 503 unsigned int pin) 504 { 505 struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 506 u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data; 507 u32 val; 508 unsigned long flags; 509 510 spin_lock_irqsave(&pinctrl->lock, flags); 511 val = readl(pinctrl->base0); 512 if ((val & (1 << pin)) == (*gpio_select << pin)) { 513 val &= ~(1 << pin); 514 if (!(*gpio_select)) 515 val |= (1 << pin); 516 writel(val, pinctrl->base0); 517 } 518 spin_unlock_irqrestore(&pinctrl->lock, flags); 519 } 520 521 static struct pinmux_ops nsp_pinmux_ops = { 522 .get_functions_count = nsp_get_functions_count, 523 .get_function_name = nsp_get_function_name, 524 .get_function_groups = nsp_get_function_groups, 525 .set_mux = nsp_pinmux_enable, 526 .gpio_request_enable = nsp_gpio_request_enable, 527 .gpio_disable_free = nsp_gpio_disable_free, 528 }; 529 530 static struct pinctrl_desc nsp_pinctrl_desc = { 531 .name = "nsp-pinmux", 532 .pctlops = &nsp_pinctrl_ops, 533 .pmxops = &nsp_pinmux_ops, 534 }; 535 536 static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl) 537 { 538 struct nsp_mux_log *log; 539 unsigned int i; 540 u32 no_of_groups = ARRAY_SIZE(nsp_pin_groups); 541 542 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups, 543 sizeof(struct nsp_mux_log), 544 GFP_KERNEL); 545 if (!pinctrl->mux_log) 546 return -ENOMEM; 547 548 for (i = 0; i < no_of_groups; i++) { 549 log = &pinctrl->mux_log[i]; 550 log->mux.base = nsp_pin_groups[i].mux.base; 551 log->mux.shift = nsp_pin_groups[i].mux.shift; 552 log->mux.alt = 0; 553 log->is_configured = false; 554 } 555 556 return 0; 557 } 558 559 static int nsp_pinmux_probe(struct platform_device *pdev) 560 { 561 struct nsp_pinctrl *pinctrl; 562 struct resource *res; 563 int i, ret; 564 struct pinctrl_pin_desc *pins; 565 unsigned int num_pins = ARRAY_SIZE(nsp_pins); 566 567 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL); 568 if (!pinctrl) 569 return -ENOMEM; 570 pinctrl->dev = &pdev->dev; 571 platform_set_drvdata(pdev, pinctrl); 572 spin_lock_init(&pinctrl->lock); 573 574 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 575 pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res); 576 if (IS_ERR(pinctrl->base0)) 577 return PTR_ERR(pinctrl->base0); 578 579 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 580 pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start, 581 resource_size(res)); 582 if (!pinctrl->base1) { 583 dev_err(&pdev->dev, "unable to map I/O space\n"); 584 return -ENOMEM; 585 } 586 587 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 588 pinctrl->base2 = devm_ioremap_resource(&pdev->dev, res); 589 if (IS_ERR(pinctrl->base2)) 590 return PTR_ERR(pinctrl->base2); 591 592 ret = nsp_mux_log_init(pinctrl); 593 if (ret) { 594 dev_err(&pdev->dev, "unable to initialize IOMUX log\n"); 595 return ret; 596 } 597 598 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL); 599 if (!pins) 600 return -ENOMEM; 601 602 for (i = 0; i < num_pins; i++) { 603 pins[i].number = nsp_pins[i].pin; 604 pins[i].name = nsp_pins[i].name; 605 pins[i].drv_data = &nsp_pins[i].gpio_select; 606 } 607 608 pinctrl->groups = nsp_pin_groups; 609 pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups); 610 pinctrl->functions = nsp_pin_functions; 611 pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions); 612 nsp_pinctrl_desc.pins = pins; 613 nsp_pinctrl_desc.npins = num_pins; 614 615 pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc, 616 pinctrl); 617 if (IS_ERR(pinctrl->pctl)) { 618 dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n"); 619 return PTR_ERR(pinctrl->pctl); 620 } 621 622 return 0; 623 } 624 625 static const struct of_device_id nsp_pinmux_of_match[] = { 626 { .compatible = "brcm,nsp-pinmux" }, 627 { } 628 }; 629 630 static struct platform_driver nsp_pinmux_driver = { 631 .driver = { 632 .name = "nsp-pinmux", 633 .of_match_table = nsp_pinmux_of_match, 634 }, 635 .probe = nsp_pinmux_probe, 636 }; 637 638 static int __init nsp_pinmux_init(void) 639 { 640 return platform_driver_register(&nsp_pinmux_driver); 641 } 642 arch_initcall(nsp_pinmux_init); 643