1 /*
2  * Copyright (C) 2014-2017 Broadcom
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation version 2.
7  *
8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9  * kind, whether express or implied; without even the implied warranty
10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 /*
15  * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
16  * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
17  * pull up/down, slew and drive strength are also supported in this driver.
18  *
19  * Pins from the chipCommonA  GPIO can be individually muxed to GPIO function,
20  * through the interaction with the NSP IOMUX controller.
21  */
22 
23 #include <linux/gpio/driver.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/ioport.h>
27 #include <linux/kernel.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_irq.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/slab.h>
35 
36 #include "../pinctrl-utils.h"
37 
38 #define NSP_CHIP_A_INT_STATUS		0x00
39 #define NSP_CHIP_A_INT_MASK		0x04
40 #define NSP_GPIO_DATA_IN		0x40
41 #define NSP_GPIO_DATA_OUT		0x44
42 #define NSP_GPIO_OUT_EN			0x48
43 #define NSP_GPIO_INT_POLARITY		0x50
44 #define NSP_GPIO_INT_MASK		0x54
45 #define NSP_GPIO_EVENT			0x58
46 #define NSP_GPIO_EVENT_INT_MASK		0x5c
47 #define NSP_GPIO_EVENT_INT_POLARITY	0x64
48 #define NSP_CHIP_A_GPIO_INT_BIT		0x01
49 
50 /* I/O parameters offset for chipcommon A GPIO */
51 #define NSP_GPIO_DRV_CTRL		0x00
52 #define NSP_GPIO_HYSTERESIS_EN		0x10
53 #define NSP_GPIO_SLEW_RATE_EN		0x14
54 #define NSP_PULL_UP_EN			0x18
55 #define NSP_PULL_DOWN_EN		0x1c
56 #define GPIO_DRV_STRENGTH_BITS		0x03
57 
58 /*
59  * nsp GPIO core
60  *
61  * @dev: pointer to device
62  * @base: I/O register base for nsp GPIO controller
63  * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
64  * @gc: GPIO chip
65  * @pctl: pointer to pinctrl_dev
66  * @pctldesc: pinctrl descriptor
67  * @lock: lock to protect access to I/O registers
68  */
69 struct nsp_gpio {
70 	struct device *dev;
71 	void __iomem *base;
72 	void __iomem *io_ctrl;
73 	struct irq_chip irqchip;
74 	struct gpio_chip gc;
75 	struct pinctrl_dev *pctl;
76 	struct pinctrl_desc pctldesc;
77 	raw_spinlock_t lock;
78 };
79 
80 enum base_type {
81 	REG,
82 	IO_CTRL
83 };
84 
85 /*
86  * Mapping from PINCONF pins to GPIO pins is 1-to-1
87  */
88 static inline unsigned nsp_pin_to_gpio(unsigned pin)
89 {
90 	return pin;
91 }
92 
93 /*
94  *  nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
95  *  nsp GPIO register
96  *
97  *  @nsp_gpio: nsp GPIO device
98  *  @base_type: reg base to modify
99  *  @reg: register offset
100  *  @gpio: GPIO pin
101  *  @set: set or clear
102  */
103 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
104 			       unsigned int reg, unsigned gpio, bool set)
105 {
106 	u32 val;
107 	void __iomem *base_address;
108 
109 	if (address == IO_CTRL)
110 		base_address = chip->io_ctrl;
111 	else
112 		base_address = chip->base;
113 
114 	val = readl(base_address + reg);
115 	if (set)
116 		val |= BIT(gpio);
117 	else
118 		val &= ~BIT(gpio);
119 
120 	writel(val, base_address + reg);
121 }
122 
123 /*
124  *  nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
125  *  nsp GPIO register
126  */
127 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
128 			       unsigned int reg, unsigned gpio)
129 {
130 	if (address == IO_CTRL)
131 		return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
132 	else
133 		return !!(readl(chip->base + reg) & BIT(gpio));
134 }
135 
136 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
137 {
138 	struct gpio_chip *gc = (struct gpio_chip *)data;
139 	struct nsp_gpio *chip = gpiochip_get_data(gc);
140 	int bit;
141 	unsigned long int_bits = 0;
142 	u32 int_status;
143 
144 	/* go through the entire GPIOs and handle all interrupts */
145 	int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
146 	if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
147 		unsigned int event, level;
148 
149 		/* Get level and edge interrupts */
150 		event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
151 			      readl(chip->base + NSP_GPIO_EVENT);
152 		level = readl(chip->base + NSP_GPIO_DATA_IN) ^
153 			      readl(chip->base + NSP_GPIO_INT_POLARITY);
154 		level &= readl(chip->base + NSP_GPIO_INT_MASK);
155 		int_bits = level | event;
156 
157 		for_each_set_bit(bit, &int_bits, gc->ngpio) {
158 			/*
159 			 * Clear the interrupt before invoking the
160 			 * handler, so we do not leave any window
161 			 */
162 			writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
163 			generic_handle_irq(
164 				irq_linear_revmap(gc->irq.domain, bit));
165 		}
166 	}
167 
168 	return  int_bits ? IRQ_HANDLED : IRQ_NONE;
169 }
170 
171 static void nsp_gpio_irq_ack(struct irq_data *d)
172 {
173 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
174 	struct nsp_gpio *chip = gpiochip_get_data(gc);
175 	unsigned gpio = d->hwirq;
176 	u32 val = BIT(gpio);
177 	u32 trigger_type;
178 
179 	trigger_type = irq_get_trigger_type(d->irq);
180 	if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
181 		nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
182 }
183 
184 /*
185  *  nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
186  *
187  *  @d: IRQ chip data
188  *  @unmask: mask/unmask GPIO interrupt
189  */
190 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
191 {
192 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
193 	struct nsp_gpio *chip = gpiochip_get_data(gc);
194 	unsigned gpio = d->hwirq;
195 	u32 trigger_type;
196 
197 	trigger_type = irq_get_trigger_type(d->irq);
198 	if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
199 		nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
200 	else
201 		nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
202 }
203 
204 static void nsp_gpio_irq_mask(struct irq_data *d)
205 {
206 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
207 	struct nsp_gpio *chip = gpiochip_get_data(gc);
208 	unsigned long flags;
209 
210 	raw_spin_lock_irqsave(&chip->lock, flags);
211 	nsp_gpio_irq_set_mask(d, false);
212 	raw_spin_unlock_irqrestore(&chip->lock, flags);
213 }
214 
215 static void nsp_gpio_irq_unmask(struct irq_data *d)
216 {
217 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
218 	struct nsp_gpio *chip = gpiochip_get_data(gc);
219 	unsigned long flags;
220 
221 	raw_spin_lock_irqsave(&chip->lock, flags);
222 	nsp_gpio_irq_set_mask(d, true);
223 	raw_spin_unlock_irqrestore(&chip->lock, flags);
224 }
225 
226 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
227 {
228 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
229 	struct nsp_gpio *chip = gpiochip_get_data(gc);
230 	unsigned gpio = d->hwirq;
231 	bool level_low;
232 	bool falling;
233 	unsigned long flags;
234 
235 	raw_spin_lock_irqsave(&chip->lock, flags);
236 	falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
237 	level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
238 
239 	switch (type & IRQ_TYPE_SENSE_MASK) {
240 	case IRQ_TYPE_EDGE_RISING:
241 		falling = false;
242 		break;
243 
244 	case IRQ_TYPE_EDGE_FALLING:
245 		falling = true;
246 		break;
247 
248 	case IRQ_TYPE_LEVEL_HIGH:
249 		level_low = false;
250 		break;
251 
252 	case IRQ_TYPE_LEVEL_LOW:
253 		level_low = true;
254 		break;
255 
256 	default:
257 		dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
258 			type);
259 		raw_spin_unlock_irqrestore(&chip->lock, flags);
260 		return -EINVAL;
261 	}
262 
263 	nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
264 	nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
265 	raw_spin_unlock_irqrestore(&chip->lock, flags);
266 
267 	dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
268 		level_low ? "true" : "false", falling ? "true" : "false");
269 	return 0;
270 }
271 
272 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
273 {
274 	struct nsp_gpio *chip = gpiochip_get_data(gc);
275 	unsigned long flags;
276 
277 	raw_spin_lock_irqsave(&chip->lock, flags);
278 	nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
279 	raw_spin_unlock_irqrestore(&chip->lock, flags);
280 
281 	dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
282 	return 0;
283 }
284 
285 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
286 				     int val)
287 {
288 	struct nsp_gpio *chip = gpiochip_get_data(gc);
289 	unsigned long flags;
290 
291 	raw_spin_lock_irqsave(&chip->lock, flags);
292 	nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
293 	nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
294 	raw_spin_unlock_irqrestore(&chip->lock, flags);
295 
296 	dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
297 	return 0;
298 }
299 
300 static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
301 {
302 	struct nsp_gpio *chip = gpiochip_get_data(gc);
303 	unsigned long flags;
304 	int val;
305 
306 	raw_spin_lock_irqsave(&chip->lock, flags);
307 	val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
308 	raw_spin_unlock_irqrestore(&chip->lock, flags);
309 
310 	return !val;
311 }
312 
313 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
314 {
315 	struct nsp_gpio *chip = gpiochip_get_data(gc);
316 	unsigned long flags;
317 
318 	raw_spin_lock_irqsave(&chip->lock, flags);
319 	nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
320 	raw_spin_unlock_irqrestore(&chip->lock, flags);
321 
322 	dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
323 }
324 
325 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
326 {
327 	struct nsp_gpio *chip = gpiochip_get_data(gc);
328 
329 	return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
330 }
331 
332 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
333 {
334 	return 1;
335 }
336 
337 /*
338  * Only one group: "gpio_grp", since this local pinctrl device only performs
339  * GPIO specific PINCONF configurations
340  */
341 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
342 				      unsigned selector)
343 {
344 	return "gpio_grp";
345 }
346 
347 static const struct pinctrl_ops nsp_pctrl_ops = {
348 	.get_groups_count = nsp_get_groups_count,
349 	.get_group_name = nsp_get_group_name,
350 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
351 	.dt_free_map = pinctrl_utils_free_map,
352 };
353 
354 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
355 {
356 	if (slew)
357 		nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
358 	else
359 		nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
360 
361 	return 0;
362 }
363 
364 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
365 			     bool pull_up, bool pull_down)
366 {
367 	unsigned long flags;
368 
369 	raw_spin_lock_irqsave(&chip->lock, flags);
370 	nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
371 	nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
372 	raw_spin_unlock_irqrestore(&chip->lock, flags);
373 
374 	dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
375 		gpio, pull_up, pull_down);
376 	return 0;
377 }
378 
379 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
380 			      bool *pull_up, bool *pull_down)
381 {
382 	unsigned long flags;
383 
384 	raw_spin_lock_irqsave(&chip->lock, flags);
385 	*pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
386 	*pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
387 	raw_spin_unlock_irqrestore(&chip->lock, flags);
388 }
389 
390 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
391 				 u32 strength)
392 {
393 	u32 offset, shift, i;
394 	u32 val;
395 	unsigned long flags;
396 
397 	/* make sure drive strength is supported */
398 	if (strength < 2 || strength > 16 || (strength % 2))
399 		return -ENOTSUPP;
400 
401 	shift = gpio;
402 	offset = NSP_GPIO_DRV_CTRL;
403 	dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
404 		strength);
405 	raw_spin_lock_irqsave(&chip->lock, flags);
406 	strength = (strength / 2) - 1;
407 	for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
408 		val = readl(chip->io_ctrl + offset);
409 		val &= ~BIT(shift);
410 		val |= ((strength >> (i-1)) & 0x1) << shift;
411 		writel(val, chip->io_ctrl + offset);
412 		offset += 4;
413 	}
414 	raw_spin_unlock_irqrestore(&chip->lock, flags);
415 
416 	return 0;
417 }
418 
419 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
420 				 u16 *strength)
421 {
422 	unsigned int offset, shift;
423 	u32 val;
424 	unsigned long flags;
425 	int i;
426 
427 	offset = NSP_GPIO_DRV_CTRL;
428 	shift = gpio;
429 
430 	raw_spin_lock_irqsave(&chip->lock, flags);
431 	*strength = 0;
432 	for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
433 		val = readl(chip->io_ctrl + offset) & BIT(shift);
434 		val >>= shift;
435 		*strength += (val << i);
436 		offset += 4;
437 	}
438 
439 	/* convert to mA */
440 	*strength = (*strength + 1) * 2;
441 	raw_spin_unlock_irqrestore(&chip->lock, flags);
442 
443 	return 0;
444 }
445 
446 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
447 				    unsigned selector,
448 			     unsigned long *config)
449 {
450 	return 0;
451 }
452 
453 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
454 				    unsigned selector,
455 			     unsigned long *configs, unsigned num_configs)
456 {
457 	return 0;
458 }
459 
460 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
461 			      unsigned long *config)
462 {
463 	struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
464 	enum pin_config_param param = pinconf_to_config_param(*config);
465 	unsigned int gpio;
466 	u16 arg = 0;
467 	bool pull_up, pull_down;
468 	int ret;
469 
470 	gpio = nsp_pin_to_gpio(pin);
471 	switch (param) {
472 	case PIN_CONFIG_BIAS_DISABLE:
473 		nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
474 		if ((pull_up == false) && (pull_down == false))
475 			return 0;
476 		else
477 			return -EINVAL;
478 
479 	case PIN_CONFIG_BIAS_PULL_UP:
480 		nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
481 		if (pull_up)
482 			return 0;
483 		else
484 			return -EINVAL;
485 
486 	case PIN_CONFIG_BIAS_PULL_DOWN:
487 		nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
488 		if (pull_down)
489 			return 0;
490 		else
491 			return -EINVAL;
492 
493 	case PIN_CONFIG_DRIVE_STRENGTH:
494 		ret = nsp_gpio_get_strength(chip, gpio, &arg);
495 		if (ret)
496 			return ret;
497 		*config = pinconf_to_config_packed(param, arg);
498 		return 0;
499 
500 	default:
501 		return -ENOTSUPP;
502 	}
503 }
504 
505 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
506 			      unsigned long *configs, unsigned num_configs)
507 {
508 	struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
509 	enum pin_config_param param;
510 	u32 arg;
511 	unsigned int i, gpio;
512 	int ret = -ENOTSUPP;
513 
514 	gpio = nsp_pin_to_gpio(pin);
515 	for (i = 0; i < num_configs; i++) {
516 		param = pinconf_to_config_param(configs[i]);
517 		arg = pinconf_to_config_argument(configs[i]);
518 
519 		switch (param) {
520 		case PIN_CONFIG_BIAS_DISABLE:
521 			ret = nsp_gpio_set_pull(chip, gpio, false, false);
522 			if (ret < 0)
523 				goto out;
524 			break;
525 
526 		case PIN_CONFIG_BIAS_PULL_UP:
527 			ret = nsp_gpio_set_pull(chip, gpio, true, false);
528 			if (ret < 0)
529 				goto out;
530 			break;
531 
532 		case PIN_CONFIG_BIAS_PULL_DOWN:
533 			ret = nsp_gpio_set_pull(chip, gpio, false, true);
534 			if (ret < 0)
535 				goto out;
536 			break;
537 
538 		case PIN_CONFIG_DRIVE_STRENGTH:
539 			ret = nsp_gpio_set_strength(chip, gpio, arg);
540 			if (ret < 0)
541 				goto out;
542 			break;
543 
544 		case PIN_CONFIG_SLEW_RATE:
545 			ret = nsp_gpio_set_slew(chip, gpio, arg);
546 			if (ret < 0)
547 				goto out;
548 			break;
549 
550 		default:
551 			dev_err(chip->dev, "invalid configuration\n");
552 			return -ENOTSUPP;
553 		}
554 	}
555 
556 out:
557 	return ret;
558 }
559 
560 static const struct pinconf_ops nsp_pconf_ops = {
561 	.is_generic = true,
562 	.pin_config_get = nsp_pin_config_get,
563 	.pin_config_set = nsp_pin_config_set,
564 	.pin_config_group_get = nsp_pin_config_group_get,
565 	.pin_config_group_set = nsp_pin_config_group_set,
566 };
567 
568 /*
569  * NSP GPIO controller supports some PINCONF related configurations such as
570  * pull up, pull down, slew and drive strength, when the pin is configured
571  * to GPIO.
572  *
573  * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
574  * local GPIO pins
575  */
576 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
577 {
578 	struct pinctrl_desc *pctldesc = &chip->pctldesc;
579 	struct pinctrl_pin_desc *pins;
580 	struct gpio_chip *gc = &chip->gc;
581 	int i;
582 
583 	pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
584 	if (!pins)
585 		return -ENOMEM;
586 	for (i = 0; i < gc->ngpio; i++) {
587 		pins[i].number = i;
588 		pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
589 					      "gpio-%d", i);
590 		if (!pins[i].name)
591 			return -ENOMEM;
592 	}
593 	pctldesc->name = dev_name(chip->dev);
594 	pctldesc->pctlops = &nsp_pctrl_ops;
595 	pctldesc->pins = pins;
596 	pctldesc->npins = gc->ngpio;
597 	pctldesc->confops = &nsp_pconf_ops;
598 
599 	chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
600 	if (IS_ERR(chip->pctl)) {
601 		dev_err(chip->dev, "unable to register pinctrl device\n");
602 		return PTR_ERR(chip->pctl);
603 	}
604 
605 	return 0;
606 }
607 
608 static const struct of_device_id nsp_gpio_of_match[] = {
609 	{.compatible = "brcm,nsp-gpio-a",},
610 	{}
611 };
612 
613 static int nsp_gpio_probe(struct platform_device *pdev)
614 {
615 	struct device *dev = &pdev->dev;
616 	struct nsp_gpio *chip;
617 	struct gpio_chip *gc;
618 	u32 val;
619 	int irq, ret;
620 
621 	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
622 		dev_err(&pdev->dev, "Missing ngpios OF property\n");
623 		return -ENODEV;
624 	}
625 
626 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
627 	if (!chip)
628 		return -ENOMEM;
629 
630 	chip->dev = dev;
631 	platform_set_drvdata(pdev, chip);
632 
633 	chip->base = devm_platform_ioremap_resource(pdev, 0);
634 	if (IS_ERR(chip->base)) {
635 		dev_err(dev, "unable to map I/O memory\n");
636 		return PTR_ERR(chip->base);
637 	}
638 
639 	chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
640 	if (IS_ERR(chip->io_ctrl)) {
641 		dev_err(dev, "unable to map I/O memory\n");
642 		return PTR_ERR(chip->io_ctrl);
643 	}
644 
645 	raw_spin_lock_init(&chip->lock);
646 	gc = &chip->gc;
647 	gc->base = -1;
648 	gc->can_sleep = false;
649 	gc->ngpio = val;
650 	gc->label = dev_name(dev);
651 	gc->parent = dev;
652 	gc->of_node = dev->of_node;
653 	gc->request = gpiochip_generic_request;
654 	gc->free = gpiochip_generic_free;
655 	gc->direction_input = nsp_gpio_direction_input;
656 	gc->direction_output = nsp_gpio_direction_output;
657 	gc->get_direction = nsp_gpio_get_direction;
658 	gc->set = nsp_gpio_set;
659 	gc->get = nsp_gpio_get;
660 
661 	/* optional GPIO interrupt support */
662 	irq = platform_get_irq(pdev, 0);
663 	if (irq > 0) {
664 		struct gpio_irq_chip *girq;
665 		struct irq_chip *irqc;
666 
667 		irqc = &chip->irqchip;
668 		irqc->name = "gpio-a";
669 		irqc->irq_ack = nsp_gpio_irq_ack;
670 		irqc->irq_mask = nsp_gpio_irq_mask;
671 		irqc->irq_unmask = nsp_gpio_irq_unmask;
672 		irqc->irq_set_type = nsp_gpio_irq_set_type;
673 
674 		val = readl(chip->base + NSP_CHIP_A_INT_MASK);
675 		val = val | NSP_CHIP_A_GPIO_INT_BIT;
676 		writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
677 
678 		/* Install ISR for this GPIO controller. */
679 		ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
680 				       IRQF_SHARED, "gpio-a", &chip->gc);
681 		if (ret) {
682 			dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
683 				irq, ret);
684 			return ret;
685 		}
686 
687 		girq = &chip->gc.irq;
688 		girq->chip = irqc;
689 		/* This will let us handle the parent IRQ in the driver */
690 		girq->parent_handler = NULL;
691 		girq->num_parents = 0;
692 		girq->parents = NULL;
693 		girq->default_type = IRQ_TYPE_NONE;
694 		girq->handler = handle_simple_irq;
695 	}
696 
697 	ret = devm_gpiochip_add_data(dev, gc, chip);
698 	if (ret < 0) {
699 		dev_err(dev, "unable to add GPIO chip\n");
700 		return ret;
701 	}
702 
703 	ret = nsp_gpio_register_pinconf(chip);
704 	if (ret) {
705 		dev_err(dev, "unable to register pinconf\n");
706 		return ret;
707 	}
708 
709 	return 0;
710 }
711 
712 static struct platform_driver nsp_gpio_driver = {
713 	.driver = {
714 		.name = "nsp-gpio-a",
715 		.of_match_table = nsp_gpio_of_match,
716 	},
717 	.probe = nsp_gpio_probe,
718 };
719 
720 static int __init nsp_gpio_init(void)
721 {
722 	return platform_driver_register(&nsp_gpio_driver);
723 }
724 arch_initcall_sync(nsp_gpio_init);
725