1 /* 2 * Copyright (C) 2014-2017 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 /* 15 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that 16 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias, 17 * pull up/down, slew and drive strength are also supported in this driver. 18 * 19 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function, 20 * through the interaction with the NSP IOMUX controller. 21 */ 22 23 #include <linux/gpio/driver.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/ioport.h> 27 #include <linux/kernel.h> 28 #include <linux/of_address.h> 29 #include <linux/of_device.h> 30 #include <linux/of_irq.h> 31 #include <linux/pinctrl/pinconf.h> 32 #include <linux/pinctrl/pinconf-generic.h> 33 #include <linux/pinctrl/pinctrl.h> 34 #include <linux/slab.h> 35 36 #include "../pinctrl-utils.h" 37 38 #define NSP_CHIP_A_INT_STATUS 0x00 39 #define NSP_CHIP_A_INT_MASK 0x04 40 #define NSP_GPIO_DATA_IN 0x40 41 #define NSP_GPIO_DATA_OUT 0x44 42 #define NSP_GPIO_OUT_EN 0x48 43 #define NSP_GPIO_INT_POLARITY 0x50 44 #define NSP_GPIO_INT_MASK 0x54 45 #define NSP_GPIO_EVENT 0x58 46 #define NSP_GPIO_EVENT_INT_MASK 0x5c 47 #define NSP_GPIO_EVENT_INT_POLARITY 0x64 48 #define NSP_CHIP_A_GPIO_INT_BIT 0x01 49 50 /* I/O parameters offset for chipcommon A GPIO */ 51 #define NSP_GPIO_DRV_CTRL 0x00 52 #define NSP_GPIO_HYSTERESIS_EN 0x10 53 #define NSP_GPIO_SLEW_RATE_EN 0x14 54 #define NSP_PULL_UP_EN 0x18 55 #define NSP_PULL_DOWN_EN 0x1c 56 #define GPIO_DRV_STRENGTH_BITS 0x03 57 58 /* 59 * nsp GPIO core 60 * 61 * @dev: pointer to device 62 * @base: I/O register base for nsp GPIO controller 63 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block 64 * @gc: GPIO chip 65 * @pctl: pointer to pinctrl_dev 66 * @pctldesc: pinctrl descriptor 67 * @irq_domain: pointer to irq domain 68 * @lock: lock to protect access to I/O registers 69 */ 70 struct nsp_gpio { 71 struct device *dev; 72 void __iomem *base; 73 void __iomem *io_ctrl; 74 struct gpio_chip gc; 75 struct pinctrl_dev *pctl; 76 struct pinctrl_desc pctldesc; 77 struct irq_domain *irq_domain; 78 raw_spinlock_t lock; 79 }; 80 81 enum base_type { 82 REG, 83 IO_CTRL 84 }; 85 86 /* 87 * Mapping from PINCONF pins to GPIO pins is 1-to-1 88 */ 89 static inline unsigned nsp_pin_to_gpio(unsigned pin) 90 { 91 return pin; 92 } 93 94 /* 95 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a 96 * nsp GPIO register 97 * 98 * @nsp_gpio: nsp GPIO device 99 * @base_type: reg base to modify 100 * @reg: register offset 101 * @gpio: GPIO pin 102 * @set: set or clear 103 */ 104 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address, 105 unsigned int reg, unsigned gpio, bool set) 106 { 107 u32 val; 108 void __iomem *base_address; 109 110 if (address == IO_CTRL) 111 base_address = chip->io_ctrl; 112 else 113 base_address = chip->base; 114 115 val = readl(base_address + reg); 116 if (set) 117 val |= BIT(gpio); 118 else 119 val &= ~BIT(gpio); 120 121 writel(val, base_address + reg); 122 } 123 124 /* 125 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a 126 * nsp GPIO register 127 */ 128 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address, 129 unsigned int reg, unsigned gpio) 130 { 131 if (address == IO_CTRL) 132 return !!(readl(chip->io_ctrl + reg) & BIT(gpio)); 133 else 134 return !!(readl(chip->base + reg) & BIT(gpio)); 135 } 136 137 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) 138 { 139 struct nsp_gpio *chip = (struct nsp_gpio *)data; 140 struct gpio_chip gc = chip->gc; 141 int bit; 142 unsigned long int_bits = 0; 143 u32 int_status; 144 145 /* go through the entire GPIOs and handle all interrupts */ 146 int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS); 147 if (int_status & NSP_CHIP_A_GPIO_INT_BIT) { 148 unsigned int event, level; 149 150 /* Get level and edge interrupts */ 151 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) & 152 readl(chip->base + NSP_GPIO_EVENT); 153 level = readl(chip->base + NSP_GPIO_DATA_IN) ^ 154 readl(chip->base + NSP_GPIO_INT_POLARITY); 155 level &= readl(chip->base + NSP_GPIO_INT_MASK); 156 int_bits = level | event; 157 158 for_each_set_bit(bit, &int_bits, gc.ngpio) { 159 /* 160 * Clear the interrupt before invoking the 161 * handler, so we do not leave any window 162 */ 163 writel(BIT(bit), chip->base + NSP_GPIO_EVENT); 164 generic_handle_irq( 165 irq_linear_revmap(chip->irq_domain, bit)); 166 } 167 } 168 169 return int_bits ? IRQ_HANDLED : IRQ_NONE; 170 } 171 172 static void nsp_gpio_irq_ack(struct irq_data *d) 173 { 174 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 175 unsigned gpio = d->hwirq; 176 u32 val = BIT(gpio); 177 u32 trigger_type; 178 179 trigger_type = irq_get_trigger_type(d->irq); 180 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 181 nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val); 182 } 183 184 /* 185 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt 186 * 187 * @d: IRQ chip data 188 * @unmask: mask/unmask GPIO interrupt 189 */ 190 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) 191 { 192 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 193 unsigned gpio = d->hwirq; 194 u32 trigger_type; 195 196 trigger_type = irq_get_trigger_type(d->irq); 197 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 198 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); 199 else 200 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); 201 } 202 203 static void nsp_gpio_irq_mask(struct irq_data *d) 204 { 205 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 206 unsigned long flags; 207 208 raw_spin_lock_irqsave(&chip->lock, flags); 209 nsp_gpio_irq_set_mask(d, false); 210 raw_spin_unlock_irqrestore(&chip->lock, flags); 211 } 212 213 static void nsp_gpio_irq_unmask(struct irq_data *d) 214 { 215 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 216 unsigned long flags; 217 218 raw_spin_lock_irqsave(&chip->lock, flags); 219 nsp_gpio_irq_set_mask(d, true); 220 raw_spin_unlock_irqrestore(&chip->lock, flags); 221 } 222 223 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type) 224 { 225 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 226 unsigned gpio = d->hwirq; 227 bool level_low; 228 bool falling; 229 unsigned long flags; 230 231 raw_spin_lock_irqsave(&chip->lock, flags); 232 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio); 233 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio); 234 235 switch (type & IRQ_TYPE_SENSE_MASK) { 236 case IRQ_TYPE_EDGE_RISING: 237 falling = false; 238 break; 239 240 case IRQ_TYPE_EDGE_FALLING: 241 falling = true; 242 break; 243 244 case IRQ_TYPE_LEVEL_HIGH: 245 level_low = false; 246 break; 247 248 case IRQ_TYPE_LEVEL_LOW: 249 level_low = true; 250 break; 251 252 default: 253 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", 254 type); 255 raw_spin_unlock_irqrestore(&chip->lock, flags); 256 return -EINVAL; 257 } 258 259 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling); 260 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low); 261 raw_spin_unlock_irqrestore(&chip->lock, flags); 262 263 dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio, 264 level_low ? "true" : "false", falling ? "true" : "false"); 265 return 0; 266 } 267 268 static struct irq_chip nsp_gpio_irq_chip = { 269 .name = "gpio-a", 270 .irq_enable = nsp_gpio_irq_unmask, 271 .irq_disable = nsp_gpio_irq_mask, 272 .irq_ack = nsp_gpio_irq_ack, 273 .irq_mask = nsp_gpio_irq_mask, 274 .irq_unmask = nsp_gpio_irq_unmask, 275 .irq_set_type = nsp_gpio_irq_set_type, 276 }; 277 278 /* 279 * Request the nsp IOMUX pinmux controller to mux individual pins to GPIO 280 */ 281 static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset) 282 { 283 unsigned gpio = gc->base + offset; 284 285 return pinctrl_request_gpio(gpio); 286 } 287 288 static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset) 289 { 290 unsigned gpio = gc->base + offset; 291 292 pinctrl_free_gpio(gpio); 293 } 294 295 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 296 { 297 struct nsp_gpio *chip = gpiochip_get_data(gc); 298 unsigned long flags; 299 300 raw_spin_lock_irqsave(&chip->lock, flags); 301 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false); 302 raw_spin_unlock_irqrestore(&chip->lock, flags); 303 304 dev_dbg(chip->dev, "gpio:%u set input\n", gpio); 305 return 0; 306 } 307 308 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, 309 int val) 310 { 311 struct nsp_gpio *chip = gpiochip_get_data(gc); 312 unsigned long flags; 313 314 raw_spin_lock_irqsave(&chip->lock, flags); 315 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); 316 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); 317 raw_spin_unlock_irqrestore(&chip->lock, flags); 318 319 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); 320 return 0; 321 } 322 323 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) 324 { 325 struct nsp_gpio *chip = gpiochip_get_data(gc); 326 unsigned long flags; 327 328 raw_spin_lock_irqsave(&chip->lock, flags); 329 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); 330 raw_spin_unlock_irqrestore(&chip->lock, flags); 331 332 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); 333 } 334 335 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio) 336 { 337 struct nsp_gpio *chip = gpiochip_get_data(gc); 338 339 return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio)); 340 } 341 342 static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 343 { 344 struct nsp_gpio *chip = gpiochip_get_data(gc); 345 346 return irq_linear_revmap(chip->irq_domain, offset); 347 } 348 349 static int nsp_get_groups_count(struct pinctrl_dev *pctldev) 350 { 351 return 1; 352 } 353 354 /* 355 * Only one group: "gpio_grp", since this local pinctrl device only performs 356 * GPIO specific PINCONF configurations 357 */ 358 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev, 359 unsigned selector) 360 { 361 return "gpio_grp"; 362 } 363 364 static const struct pinctrl_ops nsp_pctrl_ops = { 365 .get_groups_count = nsp_get_groups_count, 366 .get_group_name = nsp_get_group_name, 367 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 368 .dt_free_map = pinctrl_utils_free_map, 369 }; 370 371 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew) 372 { 373 if (slew) 374 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true); 375 else 376 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false); 377 378 return 0; 379 } 380 381 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio, 382 bool pull_up, bool pull_down) 383 { 384 unsigned long flags; 385 386 raw_spin_lock_irqsave(&chip->lock, flags); 387 nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down); 388 nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up); 389 raw_spin_unlock_irqrestore(&chip->lock, flags); 390 391 dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n", 392 gpio, pull_up, pull_down); 393 return 0; 394 } 395 396 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio, 397 bool *pull_up, bool *pull_down) 398 { 399 unsigned long flags; 400 401 raw_spin_lock_irqsave(&chip->lock, flags); 402 *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio); 403 *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio); 404 raw_spin_unlock_irqrestore(&chip->lock, flags); 405 } 406 407 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio, 408 u32 strength) 409 { 410 u32 offset, shift, i; 411 u32 val; 412 unsigned long flags; 413 414 /* make sure drive strength is supported */ 415 if (strength < 2 || strength > 16 || (strength % 2)) 416 return -ENOTSUPP; 417 418 shift = gpio; 419 offset = NSP_GPIO_DRV_CTRL; 420 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, 421 strength); 422 raw_spin_lock_irqsave(&chip->lock, flags); 423 strength = (strength / 2) - 1; 424 for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) { 425 val = readl(chip->io_ctrl + offset); 426 val &= ~BIT(shift); 427 val |= ((strength >> (i-1)) & 0x1) << shift; 428 writel(val, chip->io_ctrl + offset); 429 offset += 4; 430 } 431 raw_spin_unlock_irqrestore(&chip->lock, flags); 432 433 return 0; 434 } 435 436 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio, 437 u16 *strength) 438 { 439 unsigned int offset, shift; 440 u32 val; 441 unsigned long flags; 442 int i; 443 444 offset = NSP_GPIO_DRV_CTRL; 445 shift = gpio; 446 447 raw_spin_lock_irqsave(&chip->lock, flags); 448 *strength = 0; 449 for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) { 450 val = readl(chip->io_ctrl + offset) & BIT(shift); 451 val >>= shift; 452 *strength += (val << i); 453 offset += 4; 454 } 455 456 /* convert to mA */ 457 *strength = (*strength + 1) * 2; 458 raw_spin_unlock_irqrestore(&chip->lock, flags); 459 460 return 0; 461 } 462 463 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, 464 unsigned selector, 465 unsigned long *config) 466 { 467 return 0; 468 } 469 470 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, 471 unsigned selector, 472 unsigned long *configs, unsigned num_configs) 473 { 474 return 0; 475 } 476 477 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 478 unsigned long *config) 479 { 480 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 481 enum pin_config_param param = pinconf_to_config_param(*config); 482 unsigned int gpio; 483 u16 arg = 0; 484 bool pull_up, pull_down; 485 int ret; 486 487 gpio = nsp_pin_to_gpio(pin); 488 switch (param) { 489 case PIN_CONFIG_BIAS_DISABLE: 490 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 491 if ((pull_up == false) && (pull_down == false)) 492 return 0; 493 else 494 return -EINVAL; 495 496 case PIN_CONFIG_BIAS_PULL_UP: 497 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 498 if (pull_up) 499 return 0; 500 else 501 return -EINVAL; 502 503 case PIN_CONFIG_BIAS_PULL_DOWN: 504 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 505 if (pull_down) 506 return 0; 507 else 508 return -EINVAL; 509 510 case PIN_CONFIG_DRIVE_STRENGTH: 511 ret = nsp_gpio_get_strength(chip, gpio, &arg); 512 if (ret) 513 return ret; 514 *config = pinconf_to_config_packed(param, arg); 515 return 0; 516 517 default: 518 return -ENOTSUPP; 519 } 520 } 521 522 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 523 unsigned long *configs, unsigned num_configs) 524 { 525 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 526 enum pin_config_param param; 527 u32 arg; 528 unsigned int i, gpio; 529 int ret = -ENOTSUPP; 530 531 gpio = nsp_pin_to_gpio(pin); 532 for (i = 0; i < num_configs; i++) { 533 param = pinconf_to_config_param(configs[i]); 534 arg = pinconf_to_config_argument(configs[i]); 535 536 switch (param) { 537 case PIN_CONFIG_BIAS_DISABLE: 538 ret = nsp_gpio_set_pull(chip, gpio, false, false); 539 if (ret < 0) 540 goto out; 541 break; 542 543 case PIN_CONFIG_BIAS_PULL_UP: 544 ret = nsp_gpio_set_pull(chip, gpio, true, false); 545 if (ret < 0) 546 goto out; 547 break; 548 549 case PIN_CONFIG_BIAS_PULL_DOWN: 550 ret = nsp_gpio_set_pull(chip, gpio, false, true); 551 if (ret < 0) 552 goto out; 553 break; 554 555 case PIN_CONFIG_DRIVE_STRENGTH: 556 ret = nsp_gpio_set_strength(chip, gpio, arg); 557 if (ret < 0) 558 goto out; 559 break; 560 561 case PIN_CONFIG_SLEW_RATE: 562 ret = nsp_gpio_set_slew(chip, gpio, arg); 563 if (ret < 0) 564 goto out; 565 break; 566 567 default: 568 dev_err(chip->dev, "invalid configuration\n"); 569 return -ENOTSUPP; 570 } 571 } 572 573 out: 574 return ret; 575 } 576 577 static const struct pinconf_ops nsp_pconf_ops = { 578 .is_generic = true, 579 .pin_config_get = nsp_pin_config_get, 580 .pin_config_set = nsp_pin_config_set, 581 .pin_config_group_get = nsp_pin_config_group_get, 582 .pin_config_group_set = nsp_pin_config_group_set, 583 }; 584 585 /* 586 * NSP GPIO controller supports some PINCONF related configurations such as 587 * pull up, pull down, slew and drive strength, when the pin is configured 588 * to GPIO. 589 * 590 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the 591 * local GPIO pins 592 */ 593 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip) 594 { 595 struct pinctrl_desc *pctldesc = &chip->pctldesc; 596 struct pinctrl_pin_desc *pins; 597 struct gpio_chip *gc = &chip->gc; 598 int i; 599 600 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); 601 if (!pins) 602 return -ENOMEM; 603 for (i = 0; i < gc->ngpio; i++) { 604 pins[i].number = i; 605 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, 606 "gpio-%d", i); 607 if (!pins[i].name) 608 return -ENOMEM; 609 } 610 pctldesc->name = dev_name(chip->dev); 611 pctldesc->pctlops = &nsp_pctrl_ops; 612 pctldesc->pins = pins; 613 pctldesc->npins = gc->ngpio; 614 pctldesc->confops = &nsp_pconf_ops; 615 616 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip); 617 if (IS_ERR(chip->pctl)) { 618 dev_err(chip->dev, "unable to register pinctrl device\n"); 619 return PTR_ERR(chip->pctl); 620 } 621 622 return 0; 623 } 624 625 static const struct of_device_id nsp_gpio_of_match[] = { 626 {.compatible = "brcm,nsp-gpio-a",}, 627 {} 628 }; 629 630 static int nsp_gpio_probe(struct platform_device *pdev) 631 { 632 struct device *dev = &pdev->dev; 633 struct resource *res; 634 struct nsp_gpio *chip; 635 struct gpio_chip *gc; 636 u32 val, count; 637 int irq, ret; 638 639 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) { 640 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 641 return -ENODEV; 642 } 643 644 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 645 if (!chip) 646 return -ENOMEM; 647 648 chip->dev = dev; 649 platform_set_drvdata(pdev, chip); 650 651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 652 chip->base = devm_ioremap_resource(dev, res); 653 if (IS_ERR(chip->base)) { 654 dev_err(dev, "unable to map I/O memory\n"); 655 return PTR_ERR(chip->base); 656 } 657 658 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 659 chip->io_ctrl = devm_ioremap_resource(dev, res); 660 if (IS_ERR(chip->io_ctrl)) { 661 dev_err(dev, "unable to map I/O memory\n"); 662 return PTR_ERR(chip->io_ctrl); 663 } 664 665 raw_spin_lock_init(&chip->lock); 666 gc = &chip->gc; 667 gc->base = -1; 668 gc->can_sleep = false; 669 gc->ngpio = val; 670 gc->label = dev_name(dev); 671 gc->parent = dev; 672 gc->of_node = dev->of_node; 673 gc->request = nsp_gpio_request; 674 gc->free = nsp_gpio_free; 675 gc->direction_input = nsp_gpio_direction_input; 676 gc->direction_output = nsp_gpio_direction_output; 677 gc->set = nsp_gpio_set; 678 gc->get = nsp_gpio_get; 679 gc->to_irq = nsp_gpio_to_irq; 680 681 /* optional GPIO interrupt support */ 682 irq = platform_get_irq(pdev, 0); 683 if (irq > 0) { 684 /* Create irq domain so that each pin can be assigned an IRQ.*/ 685 chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio, 686 &irq_domain_simple_ops, 687 chip); 688 if (!chip->irq_domain) { 689 dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n"); 690 return -ENXIO; 691 } 692 693 /* Map each gpio to an IRQ and set the handler for gpiolib. */ 694 for (count = 0; count < gc->ngpio; count++) { 695 int irq = irq_create_mapping(chip->irq_domain, count); 696 697 irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip, 698 handle_simple_irq); 699 irq_set_chip_data(irq, chip); 700 } 701 702 /* Install ISR for this GPIO controller. */ 703 ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler, 704 IRQF_SHARED, "gpio-a", chip); 705 if (ret) { 706 dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n", 707 irq, ret); 708 goto err_rm_gpiochip; 709 } 710 711 val = readl(chip->base + NSP_CHIP_A_INT_MASK); 712 val = val | NSP_CHIP_A_GPIO_INT_BIT; 713 writel(val, (chip->base + NSP_CHIP_A_INT_MASK)); 714 } 715 716 ret = gpiochip_add_data(gc, chip); 717 if (ret < 0) { 718 dev_err(dev, "unable to add GPIO chip\n"); 719 return ret; 720 } 721 722 ret = nsp_gpio_register_pinconf(chip); 723 if (ret) { 724 dev_err(dev, "unable to register pinconf\n"); 725 goto err_rm_gpiochip; 726 } 727 728 return 0; 729 730 err_rm_gpiochip: 731 gpiochip_remove(gc); 732 733 return ret; 734 } 735 736 static struct platform_driver nsp_gpio_driver = { 737 .driver = { 738 .name = "nsp-gpio-a", 739 .of_match_table = nsp_gpio_of_match, 740 }, 741 .probe = nsp_gpio_probe, 742 }; 743 744 static int __init nsp_gpio_init(void) 745 { 746 return platform_driver_register(&nsp_gpio_driver); 747 } 748 arch_initcall_sync(nsp_gpio_init); 749