1 /* 2 * Copyright (C) 2015 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that 14 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias, 15 * pull up/down, slew and drive strength are also supported in this driver. 16 * 17 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function, 18 * through the interaction with the NSP IOMUX controller. 19 */ 20 21 #include <linux/gpio.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/ioport.h> 25 #include <linux/kernel.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinconf-generic.h> 31 #include <linux/pinctrl/pinctrl.h> 32 #include <linux/slab.h> 33 34 #include "../pinctrl-utils.h" 35 36 #define NSP_CHIP_A_INT_STATUS 0x00 37 #define NSP_CHIP_A_INT_MASK 0x04 38 #define NSP_GPIO_DATA_IN 0x40 39 #define NSP_GPIO_DATA_OUT 0x44 40 #define NSP_GPIO_OUT_EN 0x48 41 #define NSP_GPIO_INT_POLARITY 0x50 42 #define NSP_GPIO_INT_MASK 0x54 43 #define NSP_GPIO_EVENT 0x58 44 #define NSP_GPIO_EVENT_INT_MASK 0x5c 45 #define NSP_GPIO_EVENT_INT_POLARITY 0x64 46 #define NSP_CHIP_A_GPIO_INT_BIT 0x01 47 48 /* I/O parameters offset for chipcommon A GPIO */ 49 #define NSP_GPIO_DRV_CTRL 0x00 50 #define NSP_GPIO_HYSTERESIS_EN 0x10 51 #define NSP_GPIO_SLEW_RATE_EN 0x14 52 #define NSP_PULL_UP_EN 0x18 53 #define NSP_PULL_DOWN_EN 0x1c 54 #define GPIO_DRV_STRENGTH_BITS 0x03 55 56 /* 57 * nsp GPIO core 58 * 59 * @dev: pointer to device 60 * @base: I/O register base for nsp GPIO controller 61 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block 62 * @gc: GPIO chip 63 * @pctl: pointer to pinctrl_dev 64 * @pctldesc: pinctrl descriptor 65 * @irq_domain: pointer to irq domain 66 * @lock: lock to protect access to I/O registers 67 */ 68 struct nsp_gpio { 69 struct device *dev; 70 void __iomem *base; 71 void __iomem *io_ctrl; 72 struct gpio_chip gc; 73 struct pinctrl_dev *pctl; 74 struct pinctrl_desc pctldesc; 75 struct irq_domain *irq_domain; 76 spinlock_t lock; 77 }; 78 79 enum base_type { 80 REG, 81 IO_CTRL 82 }; 83 84 static inline struct nsp_gpio *to_nsp_gpio(struct gpio_chip *gc) 85 { 86 return container_of(gc, struct nsp_gpio, gc); 87 } 88 89 /* 90 * Mapping from PINCONF pins to GPIO pins is 1-to-1 91 */ 92 static inline unsigned nsp_pin_to_gpio(unsigned pin) 93 { 94 return pin; 95 } 96 97 /* 98 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a 99 * nsp GPIO register 100 * 101 * @nsp_gpio: nsp GPIO device 102 * @base_type: reg base to modify 103 * @reg: register offset 104 * @gpio: GPIO pin 105 * @set: set or clear 106 */ 107 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address, 108 unsigned int reg, unsigned gpio, bool set) 109 { 110 u32 val; 111 void __iomem *base_address; 112 113 if (address == IO_CTRL) 114 base_address = chip->io_ctrl; 115 else 116 base_address = chip->base; 117 118 val = readl(base_address + reg); 119 if (set) 120 val |= BIT(gpio); 121 else 122 val &= ~BIT(gpio); 123 124 writel(val, base_address + reg); 125 } 126 127 /* 128 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a 129 * nsp GPIO register 130 */ 131 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address, 132 unsigned int reg, unsigned gpio) 133 { 134 if (address == IO_CTRL) 135 return !!(readl(chip->io_ctrl + reg) & BIT(gpio)); 136 else 137 return !!(readl(chip->base + reg) & BIT(gpio)); 138 } 139 140 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) 141 { 142 struct nsp_gpio *chip = (struct nsp_gpio *)data; 143 struct gpio_chip gc = chip->gc; 144 int bit; 145 unsigned long int_bits = 0; 146 u32 int_status; 147 148 /* go through the entire GPIOs and handle all interrupts */ 149 int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS); 150 if (int_status & NSP_CHIP_A_GPIO_INT_BIT) { 151 unsigned int event, level; 152 153 /* Get level and edge interrupts */ 154 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) & 155 readl(chip->base + NSP_GPIO_EVENT); 156 level = readl(chip->base + NSP_GPIO_DATA_IN) ^ 157 readl(chip->base + NSP_GPIO_INT_POLARITY); 158 level &= readl(chip->base + NSP_GPIO_INT_MASK); 159 int_bits = level | event; 160 161 for_each_set_bit(bit, &int_bits, gc.ngpio) { 162 /* 163 * Clear the interrupt before invoking the 164 * handler, so we do not leave any window 165 */ 166 writel(BIT(bit), chip->base + NSP_GPIO_EVENT); 167 generic_handle_irq( 168 irq_linear_revmap(chip->irq_domain, bit)); 169 } 170 } 171 172 return int_bits ? IRQ_HANDLED : IRQ_NONE; 173 } 174 175 static void nsp_gpio_irq_ack(struct irq_data *d) 176 { 177 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 178 unsigned gpio = d->hwirq; 179 u32 val = BIT(gpio); 180 u32 trigger_type; 181 182 trigger_type = irq_get_trigger_type(d->irq); 183 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 184 nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val); 185 } 186 187 /* 188 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt 189 * 190 * @d: IRQ chip data 191 * @unmask: mask/unmask GPIO interrupt 192 */ 193 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) 194 { 195 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 196 unsigned gpio = d->hwirq; 197 u32 trigger_type; 198 199 trigger_type = irq_get_trigger_type(d->irq); 200 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 201 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); 202 else 203 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); 204 } 205 206 static void nsp_gpio_irq_mask(struct irq_data *d) 207 { 208 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 209 unsigned long flags; 210 211 spin_lock_irqsave(&chip->lock, flags); 212 nsp_gpio_irq_set_mask(d, false); 213 spin_unlock_irqrestore(&chip->lock, flags); 214 } 215 216 static void nsp_gpio_irq_unmask(struct irq_data *d) 217 { 218 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 219 unsigned long flags; 220 221 spin_lock_irqsave(&chip->lock, flags); 222 nsp_gpio_irq_set_mask(d, true); 223 spin_unlock_irqrestore(&chip->lock, flags); 224 } 225 226 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type) 227 { 228 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d); 229 unsigned gpio = d->hwirq; 230 bool level_low; 231 bool falling; 232 unsigned long flags; 233 234 spin_lock_irqsave(&chip->lock, flags); 235 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio); 236 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio); 237 238 switch (type & IRQ_TYPE_SENSE_MASK) { 239 case IRQ_TYPE_EDGE_RISING: 240 falling = false; 241 break; 242 243 case IRQ_TYPE_EDGE_FALLING: 244 falling = true; 245 break; 246 247 case IRQ_TYPE_LEVEL_HIGH: 248 level_low = false; 249 break; 250 251 case IRQ_TYPE_LEVEL_LOW: 252 level_low = true; 253 break; 254 255 default: 256 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", 257 type); 258 spin_unlock_irqrestore(&chip->lock, flags); 259 return -EINVAL; 260 } 261 262 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling); 263 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low); 264 spin_unlock_irqrestore(&chip->lock, flags); 265 266 dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio, 267 level_low ? "true" : "false", falling ? "true" : "false"); 268 return 0; 269 } 270 271 static struct irq_chip nsp_gpio_irq_chip = { 272 .name = "gpio-a", 273 .irq_enable = nsp_gpio_irq_unmask, 274 .irq_disable = nsp_gpio_irq_mask, 275 .irq_ack = nsp_gpio_irq_ack, 276 .irq_mask = nsp_gpio_irq_mask, 277 .irq_unmask = nsp_gpio_irq_unmask, 278 .irq_set_type = nsp_gpio_irq_set_type, 279 }; 280 281 /* 282 * Request the nsp IOMUX pinmux controller to mux individual pins to GPIO 283 */ 284 static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset) 285 { 286 unsigned gpio = gc->base + offset; 287 288 return pinctrl_request_gpio(gpio); 289 } 290 291 static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset) 292 { 293 unsigned gpio = gc->base + offset; 294 295 pinctrl_free_gpio(gpio); 296 } 297 298 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 299 { 300 struct nsp_gpio *chip = to_nsp_gpio(gc); 301 unsigned long flags; 302 303 spin_lock_irqsave(&chip->lock, flags); 304 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false); 305 spin_unlock_irqrestore(&chip->lock, flags); 306 307 dev_dbg(chip->dev, "gpio:%u set input\n", gpio); 308 return 0; 309 } 310 311 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, 312 int val) 313 { 314 struct nsp_gpio *chip = to_nsp_gpio(gc); 315 unsigned long flags; 316 317 spin_lock_irqsave(&chip->lock, flags); 318 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); 319 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); 320 spin_unlock_irqrestore(&chip->lock, flags); 321 322 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); 323 return 0; 324 } 325 326 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) 327 { 328 struct nsp_gpio *chip = to_nsp_gpio(gc); 329 unsigned long flags; 330 331 spin_lock_irqsave(&chip->lock, flags); 332 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); 333 spin_unlock_irqrestore(&chip->lock, flags); 334 335 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); 336 } 337 338 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio) 339 { 340 struct nsp_gpio *chip = to_nsp_gpio(gc); 341 342 return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio)); 343 } 344 345 static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 346 { 347 struct nsp_gpio *chip = to_nsp_gpio(gc); 348 349 return irq_linear_revmap(chip->irq_domain, offset); 350 } 351 352 static int nsp_get_groups_count(struct pinctrl_dev *pctldev) 353 { 354 return 1; 355 } 356 357 /* 358 * Only one group: "gpio_grp", since this local pinctrl device only performs 359 * GPIO specific PINCONF configurations 360 */ 361 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev, 362 unsigned selector) 363 { 364 return "gpio_grp"; 365 } 366 367 static const struct pinctrl_ops nsp_pctrl_ops = { 368 .get_groups_count = nsp_get_groups_count, 369 .get_group_name = nsp_get_group_name, 370 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 371 .dt_free_map = pinctrl_utils_dt_free_map, 372 }; 373 374 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u16 slew) 375 { 376 if (slew) 377 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true); 378 else 379 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false); 380 381 return 0; 382 } 383 384 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio, 385 bool pull_up, bool pull_down) 386 { 387 unsigned long flags; 388 389 spin_lock_irqsave(&chip->lock, flags); 390 nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down); 391 nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up); 392 spin_unlock_irqrestore(&chip->lock, flags); 393 394 dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n", 395 gpio, pull_up, pull_down); 396 return 0; 397 } 398 399 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio, 400 bool *pull_up, bool *pull_down) 401 { 402 unsigned long flags; 403 404 spin_lock_irqsave(&chip->lock, flags); 405 *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio); 406 *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio); 407 spin_unlock_irqrestore(&chip->lock, flags); 408 } 409 410 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio, 411 u16 strength) 412 { 413 u32 offset, shift, i; 414 u32 val; 415 unsigned long flags; 416 417 /* make sure drive strength is supported */ 418 if (strength < 2 || strength > 16 || (strength % 2)) 419 return -ENOTSUPP; 420 421 shift = gpio; 422 offset = NSP_GPIO_DRV_CTRL; 423 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, 424 strength); 425 spin_lock_irqsave(&chip->lock, flags); 426 strength = (strength / 2) - 1; 427 for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) { 428 val = readl(chip->io_ctrl + offset); 429 val &= ~BIT(shift); 430 val |= ((strength >> (i-1)) & 0x1) << shift; 431 writel(val, chip->io_ctrl + offset); 432 offset += 4; 433 } 434 spin_unlock_irqrestore(&chip->lock, flags); 435 436 return 0; 437 } 438 439 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio, 440 u16 *strength) 441 { 442 unsigned int i, offset, shift; 443 u32 val; 444 unsigned long flags; 445 446 offset = NSP_GPIO_DRV_CTRL; 447 shift = gpio; 448 449 spin_lock_irqsave(&chip->lock, flags); 450 *strength = 0; 451 for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) { 452 val = readl(chip->io_ctrl + offset) & BIT(shift); 453 val >>= shift; 454 *strength += (val << i); 455 offset += 4; 456 } 457 458 /* convert to mA */ 459 *strength = (*strength + 1) * 2; 460 spin_unlock_irqrestore(&chip->lock, flags); 461 462 return 0; 463 } 464 465 int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned selector, 466 unsigned long *config) 467 { 468 return 0; 469 } 470 471 int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned selector, 472 unsigned long *configs, unsigned num_configs) 473 { 474 return 0; 475 } 476 477 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 478 unsigned long *config) 479 { 480 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 481 enum pin_config_param param = pinconf_to_config_param(*config); 482 unsigned int gpio; 483 u16 arg = 0; 484 bool pull_up, pull_down; 485 int ret; 486 487 gpio = nsp_pin_to_gpio(pin); 488 switch (param) { 489 case PIN_CONFIG_BIAS_DISABLE: 490 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 491 if ((pull_up == false) && (pull_down == false)) 492 return 0; 493 else 494 return -EINVAL; 495 496 case PIN_CONFIG_BIAS_PULL_UP: 497 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 498 if (pull_up) 499 return 0; 500 else 501 return -EINVAL; 502 503 case PIN_CONFIG_BIAS_PULL_DOWN: 504 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down); 505 if (pull_down) 506 return 0; 507 else 508 return -EINVAL; 509 510 case PIN_CONFIG_DRIVE_STRENGTH: 511 ret = nsp_gpio_get_strength(chip, gpio, &arg); 512 if (ret) 513 return ret; 514 *config = pinconf_to_config_packed(param, arg); 515 return 0; 516 517 default: 518 return -ENOTSUPP; 519 } 520 } 521 522 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 523 unsigned long *configs, unsigned num_configs) 524 { 525 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 526 enum pin_config_param param; 527 u16 arg; 528 unsigned int i, gpio; 529 int ret = -ENOTSUPP; 530 531 gpio = nsp_pin_to_gpio(pin); 532 for (i = 0; i < num_configs; i++) { 533 param = pinconf_to_config_param(configs[i]); 534 arg = pinconf_to_config_argument(configs[i]); 535 536 switch (param) { 537 case PIN_CONFIG_BIAS_DISABLE: 538 ret = nsp_gpio_set_pull(chip, gpio, false, false); 539 if (ret < 0) 540 goto out; 541 break; 542 543 case PIN_CONFIG_BIAS_PULL_UP: 544 ret = nsp_gpio_set_pull(chip, gpio, true, false); 545 if (ret < 0) 546 goto out; 547 break; 548 549 case PIN_CONFIG_BIAS_PULL_DOWN: 550 ret = nsp_gpio_set_pull(chip, gpio, false, true); 551 if (ret < 0) 552 goto out; 553 break; 554 555 case PIN_CONFIG_DRIVE_STRENGTH: 556 ret = nsp_gpio_set_strength(chip, gpio, arg); 557 if (ret < 0) 558 goto out; 559 break; 560 561 case PIN_CONFIG_SLEW_RATE: 562 ret = nsp_gpio_set_slew(chip, gpio, arg); 563 if (ret < 0) 564 goto out; 565 break; 566 567 default: 568 dev_err(chip->dev, "invalid configuration\n"); 569 return -ENOTSUPP; 570 } 571 } 572 573 out: 574 return ret; 575 } 576 577 static const struct pinconf_ops nsp_pconf_ops = { 578 .is_generic = true, 579 .pin_config_get = nsp_pin_config_get, 580 .pin_config_set = nsp_pin_config_set, 581 .pin_config_group_get = nsp_pin_config_group_get, 582 .pin_config_group_set = nsp_pin_config_group_set, 583 }; 584 585 /* 586 * NSP GPIO controller supports some PINCONF related configurations such as 587 * pull up, pull down, slew and drive strength, when the pin is configured 588 * to GPIO. 589 * 590 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the 591 * local GPIO pins 592 */ 593 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip) 594 { 595 struct pinctrl_desc *pctldesc = &chip->pctldesc; 596 struct pinctrl_pin_desc *pins; 597 struct gpio_chip *gc = &chip->gc; 598 int i; 599 600 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); 601 if (!pins) 602 return -ENOMEM; 603 for (i = 0; i < gc->ngpio; i++) { 604 pins[i].number = i; 605 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, 606 "gpio-%d", i); 607 if (!pins[i].name) 608 return -ENOMEM; 609 } 610 pctldesc->name = dev_name(chip->dev); 611 pctldesc->pctlops = &nsp_pctrl_ops; 612 pctldesc->pins = pins; 613 pctldesc->npins = gc->ngpio; 614 pctldesc->confops = &nsp_pconf_ops; 615 616 chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); 617 if (IS_ERR(chip->pctl)) { 618 dev_err(chip->dev, "unable to register pinctrl device\n"); 619 return PTR_ERR(chip->pctl); 620 } 621 622 return 0; 623 } 624 625 static const struct of_device_id nsp_gpio_of_match[] = { 626 {.compatible = "brcm,nsp-gpio-a",}, 627 {} 628 }; 629 630 static int nsp_gpio_probe(struct platform_device *pdev) 631 { 632 struct device *dev = &pdev->dev; 633 struct resource *res; 634 struct nsp_gpio *chip; 635 struct gpio_chip *gc; 636 u32 val, count; 637 int irq, ret; 638 639 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) { 640 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 641 return -ENODEV; 642 } 643 644 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 645 if (!chip) 646 return -ENOMEM; 647 648 chip->dev = dev; 649 platform_set_drvdata(pdev, chip); 650 651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 652 chip->base = devm_ioremap_resource(dev, res); 653 if (IS_ERR(chip->base)) { 654 dev_err(dev, "unable to map I/O memory\n"); 655 return PTR_ERR(chip->base); 656 } 657 658 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 659 chip->io_ctrl = devm_ioremap_resource(dev, res); 660 if (IS_ERR(chip->io_ctrl)) { 661 dev_err(dev, "unable to map I/O memory\n"); 662 return PTR_ERR(chip->io_ctrl); 663 } 664 665 spin_lock_init(&chip->lock); 666 gc = &chip->gc; 667 gc->base = -1; 668 gc->can_sleep = false; 669 gc->ngpio = val; 670 gc->label = dev_name(dev); 671 gc->parent = dev; 672 gc->of_node = dev->of_node; 673 gc->request = nsp_gpio_request; 674 gc->free = nsp_gpio_free; 675 gc->direction_input = nsp_gpio_direction_input; 676 gc->direction_output = nsp_gpio_direction_output; 677 gc->set = nsp_gpio_set; 678 gc->get = nsp_gpio_get; 679 gc->to_irq = nsp_gpio_to_irq; 680 681 /* optional GPIO interrupt support */ 682 irq = platform_get_irq(pdev, 0); 683 if (irq > 0) { 684 /* Create irq domain so that each pin can be assigned an IRQ.*/ 685 chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio, 686 &irq_domain_simple_ops, 687 chip); 688 if (!chip->irq_domain) { 689 dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n"); 690 return -ENXIO; 691 } 692 693 /* Map each gpio to an IRQ and set the handler for gpiolib. */ 694 for (count = 0; count < gc->ngpio; count++) { 695 int irq = irq_create_mapping(chip->irq_domain, count); 696 697 irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip, 698 handle_simple_irq); 699 irq_set_chip_data(irq, chip); 700 } 701 702 /* Install ISR for this GPIO controller. */ 703 ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler, 704 IRQF_SHARED, "gpio-a", chip); 705 if (ret) { 706 dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n", 707 irq, ret); 708 goto err_rm_gpiochip; 709 } 710 711 val = readl(chip->base + NSP_CHIP_A_INT_MASK); 712 val = val | NSP_CHIP_A_GPIO_INT_BIT; 713 writel(val, (chip->base + NSP_CHIP_A_INT_MASK)); 714 } 715 716 ret = gpiochip_add(gc); 717 if (ret < 0) { 718 dev_err(dev, "unable to add GPIO chip\n"); 719 return ret; 720 } 721 722 ret = nsp_gpio_register_pinconf(chip); 723 if (ret) { 724 dev_err(dev, "unable to register pinconf\n"); 725 goto err_rm_gpiochip; 726 } 727 728 return 0; 729 730 err_rm_gpiochip: 731 gpiochip_remove(gc); 732 733 return ret; 734 } 735 736 static struct platform_driver nsp_gpio_driver = { 737 .driver = { 738 .name = "nsp-gpio-a", 739 .of_match_table = nsp_gpio_of_match, 740 }, 741 .probe = nsp_gpio_probe, 742 }; 743 744 static int __init nsp_gpio_init(void) 745 { 746 return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe); 747 } 748 arch_initcall_sync(nsp_gpio_init); 749