1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2014-2017 Broadcom
4  */
5 
6 /*
7  * This file contains the Broadcom Iproc GPIO driver that supports 3
8  * GPIO controllers on Iproc including the ASIU GPIO controller, the
9  * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
10  * PINCONF such as bias pull up/down, and drive strength are also supported
11  * in this driver.
12  *
13  * It provides the functionality where pins from the GPIO can be
14  * individually muxed to GPIO function, if individual pad
15  * configuration is supported, through the interaction with respective
16  * SoCs IOMUX controller.
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/ioport.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 
31 #include "../pinctrl-utils.h"
32 
33 #define IPROC_GPIO_DATA_IN_OFFSET   0x00
34 #define IPROC_GPIO_DATA_OUT_OFFSET  0x04
35 #define IPROC_GPIO_OUT_EN_OFFSET    0x08
36 #define IPROC_GPIO_INT_TYPE_OFFSET  0x0c
37 #define IPROC_GPIO_INT_DE_OFFSET    0x10
38 #define IPROC_GPIO_INT_EDGE_OFFSET  0x14
39 #define IPROC_GPIO_INT_MSK_OFFSET   0x18
40 #define IPROC_GPIO_INT_STAT_OFFSET  0x1c
41 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
42 #define IPROC_GPIO_INT_CLR_OFFSET   0x24
43 #define IPROC_GPIO_PAD_RES_OFFSET   0x34
44 #define IPROC_GPIO_RES_EN_OFFSET    0x38
45 
46 /* drive strength control for ASIU GPIO */
47 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
48 
49 /* pinconf for CCM GPIO */
50 #define IPROC_GPIO_PULL_DN_OFFSET   0x10
51 #define IPROC_GPIO_PULL_UP_OFFSET   0x14
52 
53 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
54 #define IPROC_GPIO_DRV_CTRL_OFFSET  0x00
55 
56 #define GPIO_BANK_SIZE 0x200
57 #define NGPIOS_PER_BANK 32
58 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
59 
60 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
61 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
62 
63 #define GPIO_DRV_STRENGTH_BIT_SHIFT  20
64 #define GPIO_DRV_STRENGTH_BITS       3
65 #define GPIO_DRV_STRENGTH_BIT_MASK   ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
66 
67 enum iproc_pinconf_param {
68 	IPROC_PINCONF_DRIVE_STRENGTH = 0,
69 	IPROC_PINCONF_BIAS_DISABLE,
70 	IPROC_PINCONF_BIAS_PULL_UP,
71 	IPROC_PINCONF_BIAS_PULL_DOWN,
72 	IPROC_PINCON_MAX,
73 };
74 
75 enum iproc_pinconf_ctrl_type {
76 	IOCTRL_TYPE_AON = 1,
77 	IOCTRL_TYPE_CDRU,
78 	IOCTRL_TYPE_INVALID,
79 };
80 
81 /*
82  * Iproc GPIO core
83  *
84  * @dev: pointer to device
85  * @base: I/O register base for Iproc GPIO controller
86  * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
87  * has the PINCONF support implemented outside of the GPIO block
88  * @lock: lock to protect access to I/O registers
89  * @gc: GPIO chip
90  * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
91  * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
92  * that can be individually muxed to GPIO
93  * @pinconf_disable: contains a list of PINCONF parameters that need to be
94  * disabled
95  * @nr_pinconf_disable: total number of PINCONF parameters that need to be
96  * disabled
97  * @pctl: pointer to pinctrl_dev
98  * @pctldesc: pinctrl descriptor
99  */
100 struct iproc_gpio {
101 	struct device *dev;
102 
103 	void __iomem *base;
104 	void __iomem *io_ctrl;
105 	enum iproc_pinconf_ctrl_type io_ctrl_type;
106 
107 	raw_spinlock_t lock;
108 
109 	struct irq_chip irqchip;
110 	struct gpio_chip gc;
111 	unsigned num_banks;
112 
113 	bool pinmux_is_supported;
114 
115 	enum pin_config_param *pinconf_disable;
116 	unsigned int nr_pinconf_disable;
117 
118 	struct pinctrl_dev *pctl;
119 	struct pinctrl_desc pctldesc;
120 };
121 
122 /*
123  * Mapping from PINCONF pins to GPIO pins is 1-to-1
124  */
125 static inline unsigned iproc_pin_to_gpio(unsigned pin)
126 {
127 	return pin;
128 }
129 
130 /**
131  *  iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
132  *  Iproc GPIO register
133  *
134  *  @iproc_gpio: Iproc GPIO device
135  *  @reg: register offset
136  *  @gpio: GPIO pin
137  *  @set: set or clear
138  */
139 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
140 				  unsigned gpio, bool set)
141 {
142 	unsigned int offset = IPROC_GPIO_REG(gpio, reg);
143 	unsigned int shift = IPROC_GPIO_SHIFT(gpio);
144 	u32 val;
145 
146 	val = readl(chip->base + offset);
147 	if (set)
148 		val |= BIT(shift);
149 	else
150 		val &= ~BIT(shift);
151 	writel(val, chip->base + offset);
152 }
153 
154 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
155 				  unsigned gpio)
156 {
157 	unsigned int offset = IPROC_GPIO_REG(gpio, reg);
158 	unsigned int shift = IPROC_GPIO_SHIFT(gpio);
159 
160 	return !!(readl(chip->base + offset) & BIT(shift));
161 }
162 
163 static void iproc_gpio_irq_handler(struct irq_desc *desc)
164 {
165 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
166 	struct iproc_gpio *chip = gpiochip_get_data(gc);
167 	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
168 	int i, bit;
169 
170 	chained_irq_enter(irq_chip, desc);
171 
172 	/* go through the entire GPIO banks and handle all interrupts */
173 	for (i = 0; i < chip->num_banks; i++) {
174 		unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
175 					  IPROC_GPIO_INT_MSTAT_OFFSET);
176 
177 		for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
178 			unsigned pin = NGPIOS_PER_BANK * i + bit;
179 			int child_irq = irq_find_mapping(gc->irq.domain, pin);
180 
181 			/*
182 			 * Clear the interrupt before invoking the
183 			 * handler, so we do not leave any window
184 			 */
185 			writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
186 			       IPROC_GPIO_INT_CLR_OFFSET);
187 
188 			generic_handle_irq(child_irq);
189 		}
190 	}
191 
192 	chained_irq_exit(irq_chip, desc);
193 }
194 
195 
196 static void iproc_gpio_irq_ack(struct irq_data *d)
197 {
198 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
199 	struct iproc_gpio *chip = gpiochip_get_data(gc);
200 	unsigned gpio = d->hwirq;
201 	unsigned int offset = IPROC_GPIO_REG(gpio,
202 			IPROC_GPIO_INT_CLR_OFFSET);
203 	unsigned int shift = IPROC_GPIO_SHIFT(gpio);
204 	u32 val = BIT(shift);
205 
206 	writel(val, chip->base + offset);
207 }
208 
209 /**
210  *  iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
211  *
212  *  @d: IRQ chip data
213  *  @unmask: mask/unmask GPIO interrupt
214  */
215 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
216 {
217 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
218 	struct iproc_gpio *chip = gpiochip_get_data(gc);
219 	unsigned gpio = d->hwirq;
220 
221 	iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
222 }
223 
224 static void iproc_gpio_irq_mask(struct irq_data *d)
225 {
226 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
227 	struct iproc_gpio *chip = gpiochip_get_data(gc);
228 	unsigned long flags;
229 
230 	raw_spin_lock_irqsave(&chip->lock, flags);
231 	iproc_gpio_irq_set_mask(d, false);
232 	raw_spin_unlock_irqrestore(&chip->lock, flags);
233 }
234 
235 static void iproc_gpio_irq_unmask(struct irq_data *d)
236 {
237 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
238 	struct iproc_gpio *chip = gpiochip_get_data(gc);
239 	unsigned long flags;
240 
241 	raw_spin_lock_irqsave(&chip->lock, flags);
242 	iproc_gpio_irq_set_mask(d, true);
243 	raw_spin_unlock_irqrestore(&chip->lock, flags);
244 }
245 
246 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
247 {
248 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
249 	struct iproc_gpio *chip = gpiochip_get_data(gc);
250 	unsigned gpio = d->hwirq;
251 	bool level_triggered = false;
252 	bool dual_edge = false;
253 	bool rising_or_high = false;
254 	unsigned long flags;
255 
256 	switch (type & IRQ_TYPE_SENSE_MASK) {
257 	case IRQ_TYPE_EDGE_RISING:
258 		rising_or_high = true;
259 		break;
260 
261 	case IRQ_TYPE_EDGE_FALLING:
262 		break;
263 
264 	case IRQ_TYPE_EDGE_BOTH:
265 		dual_edge = true;
266 		break;
267 
268 	case IRQ_TYPE_LEVEL_HIGH:
269 		level_triggered = true;
270 		rising_or_high = true;
271 		break;
272 
273 	case IRQ_TYPE_LEVEL_LOW:
274 		level_triggered = true;
275 		break;
276 
277 	default:
278 		dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
279 			type);
280 		return -EINVAL;
281 	}
282 
283 	raw_spin_lock_irqsave(&chip->lock, flags);
284 	iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
285 		       level_triggered);
286 	iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
287 	iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
288 		       rising_or_high);
289 	raw_spin_unlock_irqrestore(&chip->lock, flags);
290 
291 	dev_dbg(chip->dev,
292 		"gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
293 		gpio, level_triggered, dual_edge, rising_or_high);
294 
295 	return 0;
296 }
297 
298 /*
299  * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
300  */
301 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
302 {
303 	struct iproc_gpio *chip = gpiochip_get_data(gc);
304 	unsigned gpio = gc->base + offset;
305 
306 	/* not all Iproc GPIO pins can be muxed individually */
307 	if (!chip->pinmux_is_supported)
308 		return 0;
309 
310 	return pinctrl_gpio_request(gpio);
311 }
312 
313 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
314 {
315 	struct iproc_gpio *chip = gpiochip_get_data(gc);
316 	unsigned gpio = gc->base + offset;
317 
318 	if (!chip->pinmux_is_supported)
319 		return;
320 
321 	pinctrl_gpio_free(gpio);
322 }
323 
324 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
325 {
326 	struct iproc_gpio *chip = gpiochip_get_data(gc);
327 	unsigned long flags;
328 
329 	raw_spin_lock_irqsave(&chip->lock, flags);
330 	iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
331 	raw_spin_unlock_irqrestore(&chip->lock, flags);
332 
333 	dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
334 
335 	return 0;
336 }
337 
338 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
339 					int val)
340 {
341 	struct iproc_gpio *chip = gpiochip_get_data(gc);
342 	unsigned long flags;
343 
344 	raw_spin_lock_irqsave(&chip->lock, flags);
345 	iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
346 	iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
347 	raw_spin_unlock_irqrestore(&chip->lock, flags);
348 
349 	dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
350 
351 	return 0;
352 }
353 
354 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
355 {
356 	struct iproc_gpio *chip = gpiochip_get_data(gc);
357 	unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
358 	unsigned int shift = IPROC_GPIO_SHIFT(gpio);
359 
360 	return !(readl(chip->base + offset) & BIT(shift));
361 }
362 
363 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
364 {
365 	struct iproc_gpio *chip = gpiochip_get_data(gc);
366 	unsigned long flags;
367 
368 	raw_spin_lock_irqsave(&chip->lock, flags);
369 	iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
370 	raw_spin_unlock_irqrestore(&chip->lock, flags);
371 
372 	dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
373 }
374 
375 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
376 {
377 	struct iproc_gpio *chip = gpiochip_get_data(gc);
378 	unsigned int offset = IPROC_GPIO_REG(gpio,
379 					      IPROC_GPIO_DATA_IN_OFFSET);
380 	unsigned int shift = IPROC_GPIO_SHIFT(gpio);
381 
382 	return !!(readl(chip->base + offset) & BIT(shift));
383 }
384 
385 /*
386  * Mapping of the iProc PINCONF parameters to the generic pin configuration
387  * parameters
388  */
389 static const enum pin_config_param iproc_pinconf_disable_map[] = {
390 	[IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
391 	[IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
392 	[IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
393 	[IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
394 };
395 
396 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
397 					    enum pin_config_param param)
398 {
399 	unsigned int i;
400 
401 	if (!chip->nr_pinconf_disable)
402 		return false;
403 
404 	for (i = 0; i < chip->nr_pinconf_disable; i++)
405 		if (chip->pinconf_disable[i] == param)
406 			return true;
407 
408 	return false;
409 }
410 
411 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
412 					    unsigned long disable_mask)
413 {
414 	unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
415 	unsigned int bit, nbits = 0;
416 
417 	/* figure out total number of PINCONF parameters to disable */
418 	for_each_set_bit(bit, &disable_mask, map_size)
419 		nbits++;
420 
421 	if (!nbits)
422 		return 0;
423 
424 	/*
425 	 * Allocate an array to store PINCONF parameters that need to be
426 	 * disabled
427 	 */
428 	chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
429 					     sizeof(*chip->pinconf_disable),
430 					     GFP_KERNEL);
431 	if (!chip->pinconf_disable)
432 		return -ENOMEM;
433 
434 	chip->nr_pinconf_disable = nbits;
435 
436 	/* now store these parameters */
437 	nbits = 0;
438 	for_each_set_bit(bit, &disable_mask, map_size)
439 		chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
440 
441 	return 0;
442 }
443 
444 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
445 {
446 	return 1;
447 }
448 
449 /*
450  * Only one group: "gpio_grp", since this local pinctrl device only performs
451  * GPIO specific PINCONF configurations
452  */
453 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
454 					 unsigned selector)
455 {
456 	return "gpio_grp";
457 }
458 
459 static const struct pinctrl_ops iproc_pctrl_ops = {
460 	.get_groups_count = iproc_get_groups_count,
461 	.get_group_name = iproc_get_group_name,
462 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
463 	.dt_free_map = pinctrl_utils_free_map,
464 };
465 
466 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
467 				bool disable, bool pull_up)
468 {
469 	void __iomem *base;
470 	unsigned long flags;
471 	unsigned int shift;
472 	u32 val_1, val_2;
473 
474 	raw_spin_lock_irqsave(&chip->lock, flags);
475 	if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
476 		base = chip->io_ctrl;
477 		shift = IPROC_GPIO_SHIFT(gpio);
478 
479 		val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
480 		val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
481 		if (disable) {
482 			/* no pull-up or pull-down */
483 			val_1 &= ~BIT(shift);
484 			val_2 &= ~BIT(shift);
485 		} else if (pull_up) {
486 			val_1 |= BIT(shift);
487 			val_2 &= ~BIT(shift);
488 		} else {
489 			val_1 &= ~BIT(shift);
490 			val_2 |= BIT(shift);
491 		}
492 		writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
493 		writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
494 	} else {
495 		if (disable) {
496 			iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
497 				      false);
498 		} else {
499 			iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
500 				      pull_up);
501 			iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
502 				      true);
503 		}
504 	}
505 
506 	raw_spin_unlock_irqrestore(&chip->lock, flags);
507 	dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
508 
509 	return 0;
510 }
511 
512 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
513 				 bool *disable, bool *pull_up)
514 {
515 	void __iomem *base;
516 	unsigned long flags;
517 	unsigned int shift;
518 	u32 val_1, val_2;
519 
520 	raw_spin_lock_irqsave(&chip->lock, flags);
521 	if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
522 		base = chip->io_ctrl;
523 		shift = IPROC_GPIO_SHIFT(gpio);
524 
525 		val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
526 		val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
527 
528 		*pull_up = val_1 ? true : false;
529 		*disable = (val_1 | val_2) ? false : true;
530 
531 	} else {
532 		*disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
533 		*pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
534 	}
535 	raw_spin_unlock_irqrestore(&chip->lock, flags);
536 }
537 
538 #define DRV_STRENGTH_OFFSET(gpio, bit, type)  ((type) == IOCTRL_TYPE_AON ? \
539 	((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
540 	((type) == IOCTRL_TYPE_CDRU) ? \
541 	((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
542 	((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
543 
544 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
545 				    unsigned strength)
546 {
547 	void __iomem *base;
548 	unsigned int i, offset, shift;
549 	u32 val;
550 	unsigned long flags;
551 
552 	/* make sure drive strength is supported */
553 	if (strength < 2 ||  strength > 16 || (strength % 2))
554 		return -ENOTSUPP;
555 
556 	if (chip->io_ctrl) {
557 		base = chip->io_ctrl;
558 	} else {
559 		base = chip->base;
560 	}
561 
562 	shift = IPROC_GPIO_SHIFT(gpio);
563 
564 	dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
565 		strength);
566 
567 	raw_spin_lock_irqsave(&chip->lock, flags);
568 	strength = (strength / 2) - 1;
569 	for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
570 		offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
571 		val = readl(base + offset);
572 		val &= ~BIT(shift);
573 		val |= ((strength >> i) & 0x1) << shift;
574 		writel(val, base + offset);
575 	}
576 	raw_spin_unlock_irqrestore(&chip->lock, flags);
577 
578 	return 0;
579 }
580 
581 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
582 				    u16 *strength)
583 {
584 	void __iomem *base;
585 	unsigned int i, offset, shift;
586 	u32 val;
587 	unsigned long flags;
588 
589 	if (chip->io_ctrl) {
590 		base = chip->io_ctrl;
591 	} else {
592 		base = chip->base;
593 	}
594 
595 	shift = IPROC_GPIO_SHIFT(gpio);
596 
597 	raw_spin_lock_irqsave(&chip->lock, flags);
598 	*strength = 0;
599 	for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
600 		offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
601 		val = readl(base + offset) & BIT(shift);
602 		val >>= shift;
603 		*strength += (val << i);
604 	}
605 
606 	/* convert to mA */
607 	*strength = (*strength + 1) * 2;
608 	raw_spin_unlock_irqrestore(&chip->lock, flags);
609 
610 	return 0;
611 }
612 
613 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
614 				 unsigned long *config)
615 {
616 	struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
617 	enum pin_config_param param = pinconf_to_config_param(*config);
618 	unsigned gpio = iproc_pin_to_gpio(pin);
619 	u16 arg;
620 	bool disable, pull_up;
621 	int ret;
622 
623 	if (iproc_pinconf_param_is_disabled(chip, param))
624 		return -ENOTSUPP;
625 
626 	switch (param) {
627 	case PIN_CONFIG_BIAS_DISABLE:
628 		iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
629 		if (disable)
630 			return 0;
631 		else
632 			return -EINVAL;
633 
634 	case PIN_CONFIG_BIAS_PULL_UP:
635 		iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
636 		if (!disable && pull_up)
637 			return 0;
638 		else
639 			return -EINVAL;
640 
641 	case PIN_CONFIG_BIAS_PULL_DOWN:
642 		iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
643 		if (!disable && !pull_up)
644 			return 0;
645 		else
646 			return -EINVAL;
647 
648 	case PIN_CONFIG_DRIVE_STRENGTH:
649 		ret = iproc_gpio_get_strength(chip, gpio, &arg);
650 		if (ret)
651 			return ret;
652 		*config = pinconf_to_config_packed(param, arg);
653 
654 		return 0;
655 
656 	default:
657 		return -ENOTSUPP;
658 	}
659 
660 	return -ENOTSUPP;
661 }
662 
663 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
664 				 unsigned long *configs, unsigned num_configs)
665 {
666 	struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
667 	enum pin_config_param param;
668 	u32 arg;
669 	unsigned i, gpio = iproc_pin_to_gpio(pin);
670 	int ret = -ENOTSUPP;
671 
672 	for (i = 0; i < num_configs; i++) {
673 		param = pinconf_to_config_param(configs[i]);
674 
675 		if (iproc_pinconf_param_is_disabled(chip, param))
676 			return -ENOTSUPP;
677 
678 		arg = pinconf_to_config_argument(configs[i]);
679 
680 		switch (param) {
681 		case PIN_CONFIG_BIAS_DISABLE:
682 			ret = iproc_gpio_set_pull(chip, gpio, true, false);
683 			if (ret < 0)
684 				goto out;
685 			break;
686 
687 		case PIN_CONFIG_BIAS_PULL_UP:
688 			ret = iproc_gpio_set_pull(chip, gpio, false, true);
689 			if (ret < 0)
690 				goto out;
691 			break;
692 
693 		case PIN_CONFIG_BIAS_PULL_DOWN:
694 			ret = iproc_gpio_set_pull(chip, gpio, false, false);
695 			if (ret < 0)
696 				goto out;
697 			break;
698 
699 		case PIN_CONFIG_DRIVE_STRENGTH:
700 			ret = iproc_gpio_set_strength(chip, gpio, arg);
701 			if (ret < 0)
702 				goto out;
703 			break;
704 
705 		default:
706 			dev_err(chip->dev, "invalid configuration\n");
707 			return -ENOTSUPP;
708 		}
709 	} /* for each config */
710 
711 out:
712 	return ret;
713 }
714 
715 static const struct pinconf_ops iproc_pconf_ops = {
716 	.is_generic = true,
717 	.pin_config_get = iproc_pin_config_get,
718 	.pin_config_set = iproc_pin_config_set,
719 };
720 
721 /*
722  * Iproc GPIO controller supports some PINCONF related configurations such as
723  * pull up, pull down, and drive strength, when the pin is configured to GPIO
724  *
725  * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
726  * local GPIO pins
727  */
728 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
729 {
730 	struct pinctrl_desc *pctldesc = &chip->pctldesc;
731 	struct pinctrl_pin_desc *pins;
732 	struct gpio_chip *gc = &chip->gc;
733 	int i;
734 
735 	pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
736 	if (!pins)
737 		return -ENOMEM;
738 
739 	for (i = 0; i < gc->ngpio; i++) {
740 		pins[i].number = i;
741 		pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
742 					      "gpio-%d", i);
743 		if (!pins[i].name)
744 			return -ENOMEM;
745 	}
746 
747 	pctldesc->name = dev_name(chip->dev);
748 	pctldesc->pctlops = &iproc_pctrl_ops;
749 	pctldesc->pins = pins;
750 	pctldesc->npins = gc->ngpio;
751 	pctldesc->confops = &iproc_pconf_ops;
752 
753 	chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
754 	if (IS_ERR(chip->pctl)) {
755 		dev_err(chip->dev, "unable to register pinctrl device\n");
756 		return PTR_ERR(chip->pctl);
757 	}
758 
759 	return 0;
760 }
761 
762 static const struct of_device_id iproc_gpio_of_match[] = {
763 	{ .compatible = "brcm,iproc-gpio" },
764 	{ .compatible = "brcm,cygnus-ccm-gpio" },
765 	{ .compatible = "brcm,cygnus-asiu-gpio" },
766 	{ .compatible = "brcm,cygnus-crmu-gpio" },
767 	{ .compatible = "brcm,iproc-nsp-gpio" },
768 	{ .compatible = "brcm,iproc-stingray-gpio" },
769 	{ /* sentinel */ }
770 };
771 
772 static int iproc_gpio_probe(struct platform_device *pdev)
773 {
774 	struct device *dev = &pdev->dev;
775 	struct resource *res;
776 	struct iproc_gpio *chip;
777 	struct gpio_chip *gc;
778 	u32 ngpios, pinconf_disable_mask = 0;
779 	int irq, ret;
780 	bool no_pinconf = false;
781 	enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
782 
783 	/* NSP does not support drive strength config */
784 	if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
785 		pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
786 	/* Stingray does not support pinconf in this controller */
787 	else if (of_device_is_compatible(dev->of_node,
788 					 "brcm,iproc-stingray-gpio"))
789 		no_pinconf = true;
790 
791 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
792 	if (!chip)
793 		return -ENOMEM;
794 
795 	chip->dev = dev;
796 	platform_set_drvdata(pdev, chip);
797 
798 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
799 	chip->base = devm_ioremap_resource(dev, res);
800 	if (IS_ERR(chip->base)) {
801 		dev_err(dev, "unable to map I/O memory\n");
802 		return PTR_ERR(chip->base);
803 	}
804 
805 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
806 	if (res) {
807 		chip->io_ctrl = devm_ioremap_resource(dev, res);
808 		if (IS_ERR(chip->io_ctrl)) {
809 			dev_err(dev, "unable to map I/O memory\n");
810 			return PTR_ERR(chip->io_ctrl);
811 		}
812 		if (of_device_is_compatible(dev->of_node,
813 					    "brcm,cygnus-ccm-gpio"))
814 			io_ctrl_type = IOCTRL_TYPE_CDRU;
815 		else
816 			io_ctrl_type = IOCTRL_TYPE_AON;
817 	}
818 
819 	chip->io_ctrl_type = io_ctrl_type;
820 
821 	if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
822 		dev_err(&pdev->dev, "missing ngpios DT property\n");
823 		return -ENODEV;
824 	}
825 
826 	raw_spin_lock_init(&chip->lock);
827 
828 	gc = &chip->gc;
829 	gc->base = -1;
830 	gc->ngpio = ngpios;
831 	chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
832 	gc->label = dev_name(dev);
833 	gc->parent = dev;
834 	gc->of_node = dev->of_node;
835 	gc->request = iproc_gpio_request;
836 	gc->free = iproc_gpio_free;
837 	gc->direction_input = iproc_gpio_direction_input;
838 	gc->direction_output = iproc_gpio_direction_output;
839 	gc->get_direction = iproc_gpio_get_direction;
840 	gc->set = iproc_gpio_set;
841 	gc->get = iproc_gpio_get;
842 
843 	chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
844 							"gpio-ranges");
845 
846 	/* optional GPIO interrupt support */
847 	irq = platform_get_irq(pdev, 0);
848 	if (irq > 0) {
849 		struct irq_chip *irqc;
850 		struct gpio_irq_chip *girq;
851 
852 		irqc = &chip->irqchip;
853 		irqc->name = "bcm-iproc-gpio";
854 		irqc->irq_ack = iproc_gpio_irq_ack;
855 		irqc->irq_mask = iproc_gpio_irq_mask;
856 		irqc->irq_unmask = iproc_gpio_irq_unmask;
857 		irqc->irq_set_type = iproc_gpio_irq_set_type;
858 		irqc->irq_enable = iproc_gpio_irq_unmask;
859 		irqc->irq_disable = iproc_gpio_irq_mask;
860 
861 		girq = &gc->irq;
862 		girq->chip = irqc;
863 		girq->parent_handler = iproc_gpio_irq_handler;
864 		girq->num_parents = 1;
865 		girq->parents = devm_kcalloc(dev, 1,
866 					     sizeof(*girq->parents),
867 					     GFP_KERNEL);
868 		if (!girq->parents)
869 			return -ENOMEM;
870 		girq->parents[0] = irq;
871 		girq->default_type = IRQ_TYPE_NONE;
872 		girq->handler = handle_simple_irq;
873 	}
874 
875 	ret = gpiochip_add_data(gc, chip);
876 	if (ret < 0) {
877 		dev_err(dev, "unable to add GPIO chip\n");
878 		return ret;
879 	}
880 
881 	if (!no_pinconf) {
882 		ret = iproc_gpio_register_pinconf(chip);
883 		if (ret) {
884 			dev_err(dev, "unable to register pinconf\n");
885 			goto err_rm_gpiochip;
886 		}
887 
888 		if (pinconf_disable_mask) {
889 			ret = iproc_pinconf_disable_map_create(chip,
890 							 pinconf_disable_mask);
891 			if (ret) {
892 				dev_err(dev,
893 					"unable to create pinconf disable map\n");
894 				goto err_rm_gpiochip;
895 			}
896 		}
897 	}
898 
899 	return 0;
900 
901 err_rm_gpiochip:
902 	gpiochip_remove(gc);
903 
904 	return ret;
905 }
906 
907 static struct platform_driver iproc_gpio_driver = {
908 	.driver = {
909 		.name = "iproc-gpio",
910 		.of_match_table = iproc_gpio_of_match,
911 	},
912 	.probe = iproc_gpio_probe,
913 };
914 
915 static int __init iproc_gpio_init(void)
916 {
917 	return platform_driver_register(&iproc_gpio_driver);
918 }
919 arch_initcall_sync(iproc_gpio_init);
920