1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2017 Broadcom 4 */ 5 6 /* 7 * This file contains the Broadcom Iproc GPIO driver that supports 3 8 * GPIO controllers on Iproc including the ASIU GPIO controller, the 9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic 10 * PINCONF such as bias pull up/down, and drive strength are also supported 11 * in this driver. 12 * 13 * It provides the functionality where pins from the GPIO can be 14 * individually muxed to GPIO function, if individual pad 15 * configuration is supported, through the interaction with respective 16 * SoCs IOMUX controller. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/slab.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/ioport.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 31 #include "../pinctrl-utils.h" 32 33 #define IPROC_GPIO_DATA_IN_OFFSET 0x00 34 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04 35 #define IPROC_GPIO_OUT_EN_OFFSET 0x08 36 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c 37 #define IPROC_GPIO_INT_DE_OFFSET 0x10 38 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14 39 #define IPROC_GPIO_INT_MSK_OFFSET 0x18 40 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c 41 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20 42 #define IPROC_GPIO_INT_CLR_OFFSET 0x24 43 #define IPROC_GPIO_PAD_RES_OFFSET 0x34 44 #define IPROC_GPIO_RES_EN_OFFSET 0x38 45 46 /* drive strength control for ASIU GPIO */ 47 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 48 49 /* pinconf for CCM GPIO */ 50 #define IPROC_GPIO_PULL_DN_OFFSET 0x10 51 #define IPROC_GPIO_PULL_UP_OFFSET 0x14 52 53 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/ 54 #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00 55 56 #define GPIO_BANK_SIZE 0x200 57 #define NGPIOS_PER_BANK 32 58 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK) 59 60 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) 61 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK) 62 63 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20 64 #define GPIO_DRV_STRENGTH_BITS 3 65 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1) 66 67 enum iproc_pinconf_param { 68 IPROC_PINCONF_DRIVE_STRENGTH = 0, 69 IPROC_PINCONF_BIAS_DISABLE, 70 IPROC_PINCONF_BIAS_PULL_UP, 71 IPROC_PINCONF_BIAS_PULL_DOWN, 72 IPROC_PINCON_MAX, 73 }; 74 75 enum iproc_pinconf_ctrl_type { 76 IOCTRL_TYPE_AON = 1, 77 IOCTRL_TYPE_CDRU, 78 IOCTRL_TYPE_INVALID, 79 }; 80 81 /* 82 * Iproc GPIO core 83 * 84 * @dev: pointer to device 85 * @base: I/O register base for Iproc GPIO controller 86 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that 87 * has the PINCONF support implemented outside of the GPIO block 88 * @lock: lock to protect access to I/O registers 89 * @gc: GPIO chip 90 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs 91 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins 92 * that can be individually muxed to GPIO 93 * @pinconf_disable: contains a list of PINCONF parameters that need to be 94 * disabled 95 * @nr_pinconf_disable: total number of PINCONF parameters that need to be 96 * disabled 97 * @pctl: pointer to pinctrl_dev 98 * @pctldesc: pinctrl descriptor 99 */ 100 struct iproc_gpio { 101 struct device *dev; 102 103 void __iomem *base; 104 void __iomem *io_ctrl; 105 enum iproc_pinconf_ctrl_type io_ctrl_type; 106 107 raw_spinlock_t lock; 108 109 struct irq_chip irqchip; 110 struct gpio_chip gc; 111 unsigned num_banks; 112 113 bool pinmux_is_supported; 114 115 enum pin_config_param *pinconf_disable; 116 unsigned int nr_pinconf_disable; 117 118 struct pinctrl_dev *pctl; 119 struct pinctrl_desc pctldesc; 120 }; 121 122 /* 123 * Mapping from PINCONF pins to GPIO pins is 1-to-1 124 */ 125 static inline unsigned iproc_pin_to_gpio(unsigned pin) 126 { 127 return pin; 128 } 129 130 /** 131 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a 132 * Iproc GPIO register 133 * 134 * @iproc_gpio: Iproc GPIO device 135 * @reg: register offset 136 * @gpio: GPIO pin 137 * @set: set or clear 138 */ 139 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, 140 unsigned gpio, bool set) 141 { 142 unsigned int offset = IPROC_GPIO_REG(gpio, reg); 143 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 144 u32 val; 145 146 val = readl(chip->base + offset); 147 if (set) 148 val |= BIT(shift); 149 else 150 val &= ~BIT(shift); 151 writel(val, chip->base + offset); 152 } 153 154 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, 155 unsigned gpio) 156 { 157 unsigned int offset = IPROC_GPIO_REG(gpio, reg); 158 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 159 160 return !!(readl(chip->base + offset) & BIT(shift)); 161 } 162 163 static void iproc_gpio_irq_handler(struct irq_desc *desc) 164 { 165 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 166 struct iproc_gpio *chip = gpiochip_get_data(gc); 167 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 168 int i, bit; 169 170 chained_irq_enter(irq_chip, desc); 171 172 /* go through the entire GPIO banks and handle all interrupts */ 173 for (i = 0; i < chip->num_banks; i++) { 174 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) + 175 IPROC_GPIO_INT_MSTAT_OFFSET); 176 177 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { 178 unsigned pin = NGPIOS_PER_BANK * i + bit; 179 int child_irq = irq_find_mapping(gc->irq.domain, pin); 180 181 /* 182 * Clear the interrupt before invoking the 183 * handler, so we do not leave any window 184 */ 185 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) + 186 IPROC_GPIO_INT_CLR_OFFSET); 187 188 generic_handle_irq(child_irq); 189 } 190 } 191 192 chained_irq_exit(irq_chip, desc); 193 } 194 195 196 static void iproc_gpio_irq_ack(struct irq_data *d) 197 { 198 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 199 struct iproc_gpio *chip = gpiochip_get_data(gc); 200 unsigned gpio = d->hwirq; 201 unsigned int offset = IPROC_GPIO_REG(gpio, 202 IPROC_GPIO_INT_CLR_OFFSET); 203 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 204 u32 val = BIT(shift); 205 206 writel(val, chip->base + offset); 207 } 208 209 /** 210 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt 211 * 212 * @d: IRQ chip data 213 * @unmask: mask/unmask GPIO interrupt 214 */ 215 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask) 216 { 217 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 218 struct iproc_gpio *chip = gpiochip_get_data(gc); 219 unsigned gpio = d->hwirq; 220 221 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); 222 } 223 224 static void iproc_gpio_irq_mask(struct irq_data *d) 225 { 226 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 227 struct iproc_gpio *chip = gpiochip_get_data(gc); 228 unsigned long flags; 229 230 raw_spin_lock_irqsave(&chip->lock, flags); 231 iproc_gpio_irq_set_mask(d, false); 232 raw_spin_unlock_irqrestore(&chip->lock, flags); 233 } 234 235 static void iproc_gpio_irq_unmask(struct irq_data *d) 236 { 237 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 238 struct iproc_gpio *chip = gpiochip_get_data(gc); 239 unsigned long flags; 240 241 raw_spin_lock_irqsave(&chip->lock, flags); 242 iproc_gpio_irq_set_mask(d, true); 243 raw_spin_unlock_irqrestore(&chip->lock, flags); 244 } 245 246 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) 247 { 248 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 249 struct iproc_gpio *chip = gpiochip_get_data(gc); 250 unsigned gpio = d->hwirq; 251 bool level_triggered = false; 252 bool dual_edge = false; 253 bool rising_or_high = false; 254 unsigned long flags; 255 256 switch (type & IRQ_TYPE_SENSE_MASK) { 257 case IRQ_TYPE_EDGE_RISING: 258 rising_or_high = true; 259 break; 260 261 case IRQ_TYPE_EDGE_FALLING: 262 break; 263 264 case IRQ_TYPE_EDGE_BOTH: 265 dual_edge = true; 266 break; 267 268 case IRQ_TYPE_LEVEL_HIGH: 269 level_triggered = true; 270 rising_or_high = true; 271 break; 272 273 case IRQ_TYPE_LEVEL_LOW: 274 level_triggered = true; 275 break; 276 277 default: 278 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n", 279 type); 280 return -EINVAL; 281 } 282 283 raw_spin_lock_irqsave(&chip->lock, flags); 284 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio, 285 level_triggered); 286 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge); 287 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio, 288 rising_or_high); 289 290 if (type & IRQ_TYPE_EDGE_BOTH) 291 irq_set_handler_locked(d, handle_edge_irq); 292 else 293 irq_set_handler_locked(d, handle_level_irq); 294 295 raw_spin_unlock_irqrestore(&chip->lock, flags); 296 297 dev_dbg(chip->dev, 298 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n", 299 gpio, level_triggered, dual_edge, rising_or_high); 300 301 return 0; 302 } 303 304 /* 305 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO 306 */ 307 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) 308 { 309 struct iproc_gpio *chip = gpiochip_get_data(gc); 310 unsigned gpio = gc->base + offset; 311 312 /* not all Iproc GPIO pins can be muxed individually */ 313 if (!chip->pinmux_is_supported) 314 return 0; 315 316 return pinctrl_gpio_request(gpio); 317 } 318 319 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) 320 { 321 struct iproc_gpio *chip = gpiochip_get_data(gc); 322 unsigned gpio = gc->base + offset; 323 324 if (!chip->pinmux_is_supported) 325 return; 326 327 pinctrl_gpio_free(gpio); 328 } 329 330 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 331 { 332 struct iproc_gpio *chip = gpiochip_get_data(gc); 333 unsigned long flags; 334 335 raw_spin_lock_irqsave(&chip->lock, flags); 336 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false); 337 raw_spin_unlock_irqrestore(&chip->lock, flags); 338 339 dev_dbg(chip->dev, "gpio:%u set input\n", gpio); 340 341 return 0; 342 } 343 344 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, 345 int val) 346 { 347 struct iproc_gpio *chip = gpiochip_get_data(gc); 348 unsigned long flags; 349 350 raw_spin_lock_irqsave(&chip->lock, flags); 351 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true); 352 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); 353 raw_spin_unlock_irqrestore(&chip->lock, flags); 354 355 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val); 356 357 return 0; 358 } 359 360 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 361 { 362 struct iproc_gpio *chip = gpiochip_get_data(gc); 363 unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET); 364 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 365 366 return !(readl(chip->base + offset) & BIT(shift)); 367 } 368 369 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) 370 { 371 struct iproc_gpio *chip = gpiochip_get_data(gc); 372 unsigned long flags; 373 374 raw_spin_lock_irqsave(&chip->lock, flags); 375 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val)); 376 raw_spin_unlock_irqrestore(&chip->lock, flags); 377 378 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val); 379 } 380 381 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio) 382 { 383 struct iproc_gpio *chip = gpiochip_get_data(gc); 384 unsigned int offset = IPROC_GPIO_REG(gpio, 385 IPROC_GPIO_DATA_IN_OFFSET); 386 unsigned int shift = IPROC_GPIO_SHIFT(gpio); 387 388 return !!(readl(chip->base + offset) & BIT(shift)); 389 } 390 391 /* 392 * Mapping of the iProc PINCONF parameters to the generic pin configuration 393 * parameters 394 */ 395 static const enum pin_config_param iproc_pinconf_disable_map[] = { 396 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH, 397 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE, 398 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP, 399 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN, 400 }; 401 402 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip, 403 enum pin_config_param param) 404 { 405 unsigned int i; 406 407 if (!chip->nr_pinconf_disable) 408 return false; 409 410 for (i = 0; i < chip->nr_pinconf_disable; i++) 411 if (chip->pinconf_disable[i] == param) 412 return true; 413 414 return false; 415 } 416 417 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip, 418 unsigned long disable_mask) 419 { 420 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map); 421 unsigned int bit, nbits = 0; 422 423 /* figure out total number of PINCONF parameters to disable */ 424 for_each_set_bit(bit, &disable_mask, map_size) 425 nbits++; 426 427 if (!nbits) 428 return 0; 429 430 /* 431 * Allocate an array to store PINCONF parameters that need to be 432 * disabled 433 */ 434 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits, 435 sizeof(*chip->pinconf_disable), 436 GFP_KERNEL); 437 if (!chip->pinconf_disable) 438 return -ENOMEM; 439 440 chip->nr_pinconf_disable = nbits; 441 442 /* now store these parameters */ 443 nbits = 0; 444 for_each_set_bit(bit, &disable_mask, map_size) 445 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit]; 446 447 return 0; 448 } 449 450 static int iproc_get_groups_count(struct pinctrl_dev *pctldev) 451 { 452 return 1; 453 } 454 455 /* 456 * Only one group: "gpio_grp", since this local pinctrl device only performs 457 * GPIO specific PINCONF configurations 458 */ 459 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev, 460 unsigned selector) 461 { 462 return "gpio_grp"; 463 } 464 465 static const struct pinctrl_ops iproc_pctrl_ops = { 466 .get_groups_count = iproc_get_groups_count, 467 .get_group_name = iproc_get_group_name, 468 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 469 .dt_free_map = pinctrl_utils_free_map, 470 }; 471 472 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, 473 bool disable, bool pull_up) 474 { 475 void __iomem *base; 476 unsigned long flags; 477 unsigned int shift; 478 u32 val_1, val_2; 479 480 raw_spin_lock_irqsave(&chip->lock, flags); 481 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { 482 base = chip->io_ctrl; 483 shift = IPROC_GPIO_SHIFT(gpio); 484 485 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET); 486 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET); 487 if (disable) { 488 /* no pull-up or pull-down */ 489 val_1 &= ~BIT(shift); 490 val_2 &= ~BIT(shift); 491 } else if (pull_up) { 492 val_1 |= BIT(shift); 493 val_2 &= ~BIT(shift); 494 } else { 495 val_1 &= ~BIT(shift); 496 val_2 |= BIT(shift); 497 } 498 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET); 499 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET); 500 } else { 501 if (disable) { 502 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, 503 false); 504 } else { 505 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, 506 pull_up); 507 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, 508 true); 509 } 510 } 511 512 raw_spin_unlock_irqrestore(&chip->lock, flags); 513 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); 514 515 return 0; 516 } 517 518 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, 519 bool *disable, bool *pull_up) 520 { 521 void __iomem *base; 522 unsigned long flags; 523 unsigned int shift; 524 u32 val_1, val_2; 525 526 raw_spin_lock_irqsave(&chip->lock, flags); 527 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { 528 base = chip->io_ctrl; 529 shift = IPROC_GPIO_SHIFT(gpio); 530 531 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift); 532 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift); 533 534 *pull_up = val_1 ? true : false; 535 *disable = (val_1 | val_2) ? false : true; 536 537 } else { 538 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); 539 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); 540 } 541 raw_spin_unlock_irqrestore(&chip->lock, flags); 542 } 543 544 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \ 545 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \ 546 ((type) == IOCTRL_TYPE_CDRU) ? \ 547 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \ 548 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET))) 549 550 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, 551 unsigned strength) 552 { 553 void __iomem *base; 554 unsigned int i, offset, shift; 555 u32 val; 556 unsigned long flags; 557 558 /* make sure drive strength is supported */ 559 if (strength < 2 || strength > 16 || (strength % 2)) 560 return -ENOTSUPP; 561 562 if (chip->io_ctrl) { 563 base = chip->io_ctrl; 564 } else { 565 base = chip->base; 566 } 567 568 shift = IPROC_GPIO_SHIFT(gpio); 569 570 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio, 571 strength); 572 573 raw_spin_lock_irqsave(&chip->lock, flags); 574 strength = (strength / 2) - 1; 575 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { 576 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); 577 val = readl(base + offset); 578 val &= ~BIT(shift); 579 val |= ((strength >> i) & 0x1) << shift; 580 writel(val, base + offset); 581 } 582 raw_spin_unlock_irqrestore(&chip->lock, flags); 583 584 return 0; 585 } 586 587 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, 588 u16 *strength) 589 { 590 void __iomem *base; 591 unsigned int i, offset, shift; 592 u32 val; 593 unsigned long flags; 594 595 if (chip->io_ctrl) { 596 base = chip->io_ctrl; 597 } else { 598 base = chip->base; 599 } 600 601 shift = IPROC_GPIO_SHIFT(gpio); 602 603 raw_spin_lock_irqsave(&chip->lock, flags); 604 *strength = 0; 605 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { 606 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); 607 val = readl(base + offset) & BIT(shift); 608 val >>= shift; 609 *strength += (val << i); 610 } 611 612 /* convert to mA */ 613 *strength = (*strength + 1) * 2; 614 raw_spin_unlock_irqrestore(&chip->lock, flags); 615 616 return 0; 617 } 618 619 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 620 unsigned long *config) 621 { 622 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 623 enum pin_config_param param = pinconf_to_config_param(*config); 624 unsigned gpio = iproc_pin_to_gpio(pin); 625 u16 arg; 626 bool disable, pull_up; 627 int ret; 628 629 if (iproc_pinconf_param_is_disabled(chip, param)) 630 return -ENOTSUPP; 631 632 switch (param) { 633 case PIN_CONFIG_BIAS_DISABLE: 634 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); 635 if (disable) 636 return 0; 637 else 638 return -EINVAL; 639 640 case PIN_CONFIG_BIAS_PULL_UP: 641 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); 642 if (!disable && pull_up) 643 return 0; 644 else 645 return -EINVAL; 646 647 case PIN_CONFIG_BIAS_PULL_DOWN: 648 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up); 649 if (!disable && !pull_up) 650 return 0; 651 else 652 return -EINVAL; 653 654 case PIN_CONFIG_DRIVE_STRENGTH: 655 ret = iproc_gpio_get_strength(chip, gpio, &arg); 656 if (ret) 657 return ret; 658 *config = pinconf_to_config_packed(param, arg); 659 660 return 0; 661 662 default: 663 return -ENOTSUPP; 664 } 665 666 return -ENOTSUPP; 667 } 668 669 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, 670 unsigned long *configs, unsigned num_configs) 671 { 672 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev); 673 enum pin_config_param param; 674 u32 arg; 675 unsigned i, gpio = iproc_pin_to_gpio(pin); 676 int ret = -ENOTSUPP; 677 678 for (i = 0; i < num_configs; i++) { 679 param = pinconf_to_config_param(configs[i]); 680 681 if (iproc_pinconf_param_is_disabled(chip, param)) 682 return -ENOTSUPP; 683 684 arg = pinconf_to_config_argument(configs[i]); 685 686 switch (param) { 687 case PIN_CONFIG_BIAS_DISABLE: 688 ret = iproc_gpio_set_pull(chip, gpio, true, false); 689 if (ret < 0) 690 goto out; 691 break; 692 693 case PIN_CONFIG_BIAS_PULL_UP: 694 ret = iproc_gpio_set_pull(chip, gpio, false, true); 695 if (ret < 0) 696 goto out; 697 break; 698 699 case PIN_CONFIG_BIAS_PULL_DOWN: 700 ret = iproc_gpio_set_pull(chip, gpio, false, false); 701 if (ret < 0) 702 goto out; 703 break; 704 705 case PIN_CONFIG_DRIVE_STRENGTH: 706 ret = iproc_gpio_set_strength(chip, gpio, arg); 707 if (ret < 0) 708 goto out; 709 break; 710 711 default: 712 dev_err(chip->dev, "invalid configuration\n"); 713 return -ENOTSUPP; 714 } 715 } /* for each config */ 716 717 out: 718 return ret; 719 } 720 721 static const struct pinconf_ops iproc_pconf_ops = { 722 .is_generic = true, 723 .pin_config_get = iproc_pin_config_get, 724 .pin_config_set = iproc_pin_config_set, 725 }; 726 727 /* 728 * Iproc GPIO controller supports some PINCONF related configurations such as 729 * pull up, pull down, and drive strength, when the pin is configured to GPIO 730 * 731 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the 732 * local GPIO pins 733 */ 734 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip) 735 { 736 struct pinctrl_desc *pctldesc = &chip->pctldesc; 737 struct pinctrl_pin_desc *pins; 738 struct gpio_chip *gc = &chip->gc; 739 int i; 740 741 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL); 742 if (!pins) 743 return -ENOMEM; 744 745 for (i = 0; i < gc->ngpio; i++) { 746 pins[i].number = i; 747 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL, 748 "gpio-%d", i); 749 if (!pins[i].name) 750 return -ENOMEM; 751 } 752 753 pctldesc->name = dev_name(chip->dev); 754 pctldesc->pctlops = &iproc_pctrl_ops; 755 pctldesc->pins = pins; 756 pctldesc->npins = gc->ngpio; 757 pctldesc->confops = &iproc_pconf_ops; 758 759 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip); 760 if (IS_ERR(chip->pctl)) { 761 dev_err(chip->dev, "unable to register pinctrl device\n"); 762 return PTR_ERR(chip->pctl); 763 } 764 765 return 0; 766 } 767 768 static const struct of_device_id iproc_gpio_of_match[] = { 769 { .compatible = "brcm,iproc-gpio" }, 770 { .compatible = "brcm,cygnus-ccm-gpio" }, 771 { .compatible = "brcm,cygnus-asiu-gpio" }, 772 { .compatible = "brcm,cygnus-crmu-gpio" }, 773 { .compatible = "brcm,iproc-nsp-gpio" }, 774 { .compatible = "brcm,iproc-stingray-gpio" }, 775 { /* sentinel */ } 776 }; 777 778 static int iproc_gpio_probe(struct platform_device *pdev) 779 { 780 struct device *dev = &pdev->dev; 781 struct resource *res; 782 struct iproc_gpio *chip; 783 struct gpio_chip *gc; 784 u32 ngpios, pinconf_disable_mask = 0; 785 int irq, ret; 786 bool no_pinconf = false; 787 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID; 788 789 /* NSP does not support drive strength config */ 790 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio")) 791 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH); 792 /* Stingray does not support pinconf in this controller */ 793 else if (of_device_is_compatible(dev->of_node, 794 "brcm,iproc-stingray-gpio")) 795 no_pinconf = true; 796 797 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 798 if (!chip) 799 return -ENOMEM; 800 801 chip->dev = dev; 802 platform_set_drvdata(pdev, chip); 803 804 chip->base = devm_platform_ioremap_resource(pdev, 0); 805 if (IS_ERR(chip->base)) { 806 dev_err(dev, "unable to map I/O memory\n"); 807 return PTR_ERR(chip->base); 808 } 809 810 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 811 if (res) { 812 chip->io_ctrl = devm_ioremap_resource(dev, res); 813 if (IS_ERR(chip->io_ctrl)) { 814 dev_err(dev, "unable to map I/O memory\n"); 815 return PTR_ERR(chip->io_ctrl); 816 } 817 if (of_device_is_compatible(dev->of_node, 818 "brcm,cygnus-ccm-gpio")) 819 io_ctrl_type = IOCTRL_TYPE_CDRU; 820 else 821 io_ctrl_type = IOCTRL_TYPE_AON; 822 } 823 824 chip->io_ctrl_type = io_ctrl_type; 825 826 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { 827 dev_err(&pdev->dev, "missing ngpios DT property\n"); 828 return -ENODEV; 829 } 830 831 raw_spin_lock_init(&chip->lock); 832 833 gc = &chip->gc; 834 gc->base = -1; 835 gc->ngpio = ngpios; 836 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK; 837 gc->label = dev_name(dev); 838 gc->parent = dev; 839 gc->of_node = dev->of_node; 840 gc->request = iproc_gpio_request; 841 gc->free = iproc_gpio_free; 842 gc->direction_input = iproc_gpio_direction_input; 843 gc->direction_output = iproc_gpio_direction_output; 844 gc->get_direction = iproc_gpio_get_direction; 845 gc->set = iproc_gpio_set; 846 gc->get = iproc_gpio_get; 847 848 chip->pinmux_is_supported = of_property_read_bool(dev->of_node, 849 "gpio-ranges"); 850 851 /* optional GPIO interrupt support */ 852 irq = platform_get_irq_optional(pdev, 0); 853 if (irq > 0) { 854 struct irq_chip *irqc; 855 struct gpio_irq_chip *girq; 856 857 irqc = &chip->irqchip; 858 irqc->name = dev_name(dev); 859 irqc->irq_ack = iproc_gpio_irq_ack; 860 irqc->irq_mask = iproc_gpio_irq_mask; 861 irqc->irq_unmask = iproc_gpio_irq_unmask; 862 irqc->irq_set_type = iproc_gpio_irq_set_type; 863 irqc->irq_enable = iproc_gpio_irq_unmask; 864 irqc->irq_disable = iproc_gpio_irq_mask; 865 866 girq = &gc->irq; 867 girq->chip = irqc; 868 girq->parent_handler = iproc_gpio_irq_handler; 869 girq->num_parents = 1; 870 girq->parents = devm_kcalloc(dev, 1, 871 sizeof(*girq->parents), 872 GFP_KERNEL); 873 if (!girq->parents) 874 return -ENOMEM; 875 girq->parents[0] = irq; 876 girq->default_type = IRQ_TYPE_NONE; 877 girq->handler = handle_bad_irq; 878 } 879 880 ret = gpiochip_add_data(gc, chip); 881 if (ret < 0) { 882 dev_err(dev, "unable to add GPIO chip\n"); 883 return ret; 884 } 885 886 if (!no_pinconf) { 887 ret = iproc_gpio_register_pinconf(chip); 888 if (ret) { 889 dev_err(dev, "unable to register pinconf\n"); 890 goto err_rm_gpiochip; 891 } 892 893 if (pinconf_disable_mask) { 894 ret = iproc_pinconf_disable_map_create(chip, 895 pinconf_disable_mask); 896 if (ret) { 897 dev_err(dev, 898 "unable to create pinconf disable map\n"); 899 goto err_rm_gpiochip; 900 } 901 } 902 } 903 904 return 0; 905 906 err_rm_gpiochip: 907 gpiochip_remove(gc); 908 909 return ret; 910 } 911 912 static struct platform_driver iproc_gpio_driver = { 913 .driver = { 914 .name = "iproc-gpio", 915 .of_match_table = iproc_gpio_of_match, 916 }, 917 .probe = iproc_gpio_probe, 918 }; 919 920 static int __init iproc_gpio_init(void) 921 { 922 return platform_driver_register(&iproc_gpio_driver); 923 } 924 arch_initcall_sync(iproc_gpio_init); 925