1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014-2017 Broadcom
3 
4 /*
5  * Broadcom Cygnus IOMUX driver
6  *
7  * This file contains the Cygnus IOMUX driver that supports group based PINMUX
8  * configuration. Although PINMUX configuration is mainly group based, the
9  * Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO
10  * function, and therefore be controlled by the Cygnus ASIU GPIO controller
11  */
12 
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/slab.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include "../core.h"
23 #include "../pinctrl-utils.h"
24 
25 #define CYGNUS_NUM_IOMUX_REGS     8
26 #define CYGNUS_NUM_MUX_PER_REG    8
27 #define CYGNUS_NUM_IOMUX          (CYGNUS_NUM_IOMUX_REGS * \
28 				   CYGNUS_NUM_MUX_PER_REG)
29 
30 /*
31  * Cygnus IOMUX register description
32  *
33  * @offset: register offset for mux configuration of a group
34  * @shift: bit shift for mux configuration of a group
35  * @alt: alternate function to set to
36  */
37 struct cygnus_mux {
38 	unsigned int offset;
39 	unsigned int shift;
40 	unsigned int alt;
41 };
42 
43 /*
44  * Keep track of Cygnus IOMUX configuration and prevent double configuration
45  *
46  * @cygnus_mux: Cygnus IOMUX register description
47  * @is_configured: flag to indicate whether a mux setting has already been
48  * configured
49  */
50 struct cygnus_mux_log {
51 	struct cygnus_mux mux;
52 	bool is_configured;
53 };
54 
55 /*
56  * Group based IOMUX configuration
57  *
58  * @name: name of the group
59  * @pins: array of pins used by this group
60  * @num_pins: total number of pins used by this group
61  * @mux: Cygnus group based IOMUX configuration
62  */
63 struct cygnus_pin_group {
64 	const char *name;
65 	const unsigned *pins;
66 	unsigned num_pins;
67 	struct cygnus_mux mux;
68 };
69 
70 /*
71  * Cygnus mux function and supported pin groups
72  *
73  * @name: name of the function
74  * @groups: array of groups that can be supported by this function
75  * @num_groups: total number of groups that can be supported by this function
76  */
77 struct cygnus_pin_function {
78 	const char *name;
79 	const char * const *groups;
80 	unsigned num_groups;
81 };
82 
83 /*
84  * Cygnus IOMUX pinctrl core
85  *
86  * @pctl: pointer to pinctrl_dev
87  * @dev: pointer to device
88  * @base0: first I/O register base of the Cygnus IOMUX controller
89  * @base1: second I/O register base
90  * @groups: pointer to array of groups
91  * @num_groups: total number of groups
92  * @functions: pointer to array of functions
93  * @num_functions: total number of functions
94  * @mux_log: pointer to the array of mux logs
95  * @lock: lock to protect register access
96  */
97 struct cygnus_pinctrl {
98 	struct pinctrl_dev *pctl;
99 	struct device *dev;
100 	void __iomem *base0;
101 	void __iomem *base1;
102 
103 	const struct cygnus_pin_group *groups;
104 	unsigned num_groups;
105 
106 	const struct cygnus_pin_function *functions;
107 	unsigned num_functions;
108 
109 	struct cygnus_mux_log *mux_log;
110 
111 	spinlock_t lock;
112 };
113 
114 /*
115  * Certain pins can be individually muxed to GPIO function
116  *
117  * @is_supported: flag to indicate GPIO mux is supported for this pin
118  * @offset: register offset for GPIO mux override of a pin
119  * @shift: bit shift for GPIO mux override of a pin
120  */
121 struct cygnus_gpio_mux {
122 	int is_supported;
123 	unsigned int offset;
124 	unsigned int shift;
125 };
126 
127 /*
128  * Description of a pin in Cygnus
129  *
130  * @pin: pin number
131  * @name: pin name
132  * @gpio_mux: GPIO override related information
133  */
134 struct cygnus_pin {
135 	unsigned pin;
136 	char *name;
137 	struct cygnus_gpio_mux gpio_mux;
138 };
139 
140 #define CYGNUS_PIN_DESC(p, n, i, o, s)	\
141 {					\
142 	.pin = p,			\
143 	.name = n,			\
144 	.gpio_mux = {			\
145 		.is_supported = i,	\
146 		.offset = o,		\
147 		.shift = s,		\
148 	},				\
149 }
150 
151 /*
152  * List of pins in Cygnus
153  */
154 static struct cygnus_pin cygnus_pins[] = {
155 	CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
156 	CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
157 	CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
158 	CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
159 	CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
160 	CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
161 	CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),
162 	CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),
163 	CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),
164 	CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),
165 	CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),
166 	CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),
167 	CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),
168 	CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),
169 	CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),
170 	CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),
171 	CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),
172 	CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),
173 	CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),
174 	CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),
175 	CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),
176 	CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),
177 	CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),
178 	CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),
179 	CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),
180 	CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),
181 	CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),
182 	CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),
183 	CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),
184 	CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),
185 	CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),
186 	CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),
187 	CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),
188 	CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),
189 	CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),
190 	CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),
191 	CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),
192 	CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),
193 	CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),
194 	CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),
195 	CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),
196 	CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),
197 	CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),
198 	CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),
199 	CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),
200 	CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),
201 	CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),
202 	CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),
203 	CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),
204 	CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),
205 	CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),
206 	CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),
207 	CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),
208 	CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),
209 	CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),
210 	CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),
211 	CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),
212 	CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),
213 	CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),
214 	CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),
215 	CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),
216 	CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),
217 	CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),
218 	CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),
219 	CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),
220 	CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),
221 	CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),
222 	CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),
223 	CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),
224 	CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),
225 	CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),
226 	CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),
227 	CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),
228 	CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),
229 	CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),
230 	CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),
231 	CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),
232 	CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),
233 	CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),
234 	CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),
235 	CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),
236 	CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),
237 	CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),
238 	CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),
239 	CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),
240 	CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),
241 	CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),
242 	CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),
243 	CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),
244 	CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),
245 	CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),
246 	CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),
247 	CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),
248 	CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),
249 	CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),
250 	CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),
251 	CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),
252 	CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),
253 	CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),
254 	CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),
255 	CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),
256 	CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),
257 	CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),
258 	CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),
259 	CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),
260 	CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),
261 	CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),
262 	CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),
263 	CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),
264 	CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),
265 	CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),
266 	CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),
267 	CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),
268 	CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),
269 	CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),
270 	CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),
271 	CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),
272 	CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),
273 	CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),
274 	CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),
275 	CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),
276 	CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),
277 	CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),
278 	CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),
279 	CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),
280 	CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),
281 	CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),
282 	CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),
283 	CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),
284 	CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),
285 	CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),
286 	CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),
287 	CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),
288 	CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),
289 	CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),
290 	CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),
291 	CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),
292 	CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),
293 	CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),
294 	CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),
295 	CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),
296 	CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),
297 	CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),
298 	CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),
299 	CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),
300 	CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),
301 	CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),
302 	CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),
303 	CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),
304 	CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),
305 	CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),
306 	CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),
307 	CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),
308 	CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),
309 	CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),
310 	CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),
311 	CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),
312 	CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),
313 	CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),
314 	CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),
315 	CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),
316 	CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),
317 	CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),
318 	CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),
319 	CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),
320 	CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),
321 	CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),
322 	CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),
323 	CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),
324 	CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),
325 	CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),
326 	CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),
327 	CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),
328 	CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),
329 	CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),
330 	CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),
331 	CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),
332 	CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),
333 	CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),
334 	CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),
335 };
336 
337 /*
338  * List of groups of pins
339  */
340 static const unsigned bsc1_pins[] = { 8, 9 };
341 static const unsigned pcie_clkreq_pins[] = { 8, 9 };
342 
343 static const unsigned i2s2_0_pins[] = { 12 };
344 static const unsigned i2s2_1_pins[] = { 13 };
345 static const unsigned i2s2_2_pins[] = { 14 };
346 static const unsigned i2s2_3_pins[] = { 15 };
347 static const unsigned i2s2_4_pins[] = { 16 };
348 
349 static const unsigned pwm4_pins[] = { 17 };
350 static const unsigned pwm5_pins[] = { 18 };
351 
352 static const unsigned key0_pins[] = { 20 };
353 static const unsigned key1_pins[] = { 21 };
354 static const unsigned key2_pins[] = { 22 };
355 static const unsigned key3_pins[] = { 23 };
356 static const unsigned key4_pins[] = { 24 };
357 static const unsigned key5_pins[] = { 25 };
358 
359 static const unsigned key6_pins[] = { 26 };
360 static const unsigned audio_dte0_pins[] = { 26 };
361 
362 static const unsigned key7_pins[] = { 27 };
363 static const unsigned audio_dte1_pins[] = { 27 };
364 
365 static const unsigned key8_pins[] = { 28 };
366 static const unsigned key9_pins[] = { 29 };
367 static const unsigned key10_pins[] = { 30 };
368 static const unsigned key11_pins[] = { 31 };
369 static const unsigned key12_pins[] = { 32 };
370 static const unsigned key13_pins[] = { 33 };
371 
372 static const unsigned key14_pins[] = { 34 };
373 static const unsigned audio_dte2_pins[] = { 34 };
374 
375 static const unsigned key15_pins[] = { 35 };
376 static const unsigned audio_dte3_pins[] = { 35 };
377 
378 static const unsigned pwm0_pins[] = { 38 };
379 static const unsigned pwm1_pins[] = { 39 };
380 static const unsigned pwm2_pins[] = { 40 };
381 static const unsigned pwm3_pins[] = { 41 };
382 
383 static const unsigned sdio0_pins[] = { 94, 95, 96, 97, 98, 99 };
384 
385 static const unsigned smart_card0_pins[] = { 42, 43, 44, 46, 47 };
386 static const unsigned i2s0_0_pins[] = { 42, 43, 44, 46 };
387 static const unsigned spdif_pins[] = { 47 };
388 
389 static const unsigned smart_card1_pins[] = { 48, 49, 50, 52, 53 };
390 static const unsigned i2s1_0_pins[] = { 48, 49, 50, 52 };
391 
392 static const unsigned spi0_pins[] = { 54, 55, 56, 57 };
393 
394 static const unsigned spi1_pins[] = { 58, 59, 60, 61 };
395 
396 static const unsigned spi2_pins[] = { 62, 63, 64, 65 };
397 
398 static const unsigned spi3_pins[] = { 66, 67, 68, 69 };
399 static const unsigned sw_led0_0_pins[] = { 66, 67, 68, 69 };
400 
401 static const unsigned d1w_pins[] = { 10, 11 };
402 static const unsigned uart4_pins[] = { 10, 11 };
403 static const unsigned sw_led2_0_pins[] = { 10, 11 };
404 
405 static const unsigned lcd_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
406 	134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
407 	148, 149, 150, 151, 152, 153, 154, 155 };
408 static const unsigned sram_0_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
409 	134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
410 	148, 149, 150, 151, 152, 153, 154, 155 };
411 static const unsigned spi5_pins[] = { 141, 142, 143, 144 };
412 
413 static const unsigned uart0_pins[] = { 70, 71, 72, 73 };
414 static const unsigned sw_led0_1_pins[] = { 70, 71, 72, 73 };
415 
416 static const unsigned uart1_dte_pins[] = { 75, 76, 77, 78 };
417 static const unsigned uart2_pins[] = { 75, 76, 77, 78 };
418 
419 static const unsigned uart1_pins[] = { 74, 79, 80, 81 };
420 
421 static const unsigned uart3_pins[] = { 82, 83 };
422 
423 static const unsigned qspi_0_pins[] = { 104, 105, 106, 107 };
424 
425 static const unsigned nand_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
426 	118, 119, 120, 121, 122, 123, 124, 125 };
427 
428 static const unsigned sdio0_cd_pins[] = { 103 };
429 
430 static const unsigned sdio0_mmc_pins[] = { 100, 101, 102 };
431 
432 static const unsigned sdio1_data_0_pins[] = { 86, 87 };
433 static const unsigned can0_pins[] = { 86, 87 };
434 static const unsigned spi4_0_pins[] = { 86, 87 };
435 
436 static const unsigned sdio1_data_1_pins[] = { 88, 89 };
437 static const unsigned can1_pins[] = { 88, 89 };
438 static const unsigned spi4_1_pins[] = { 88, 89 };
439 
440 static const unsigned sdio1_cd_pins[] = { 93 };
441 
442 static const unsigned sdio1_led_pins[] = { 84, 85 };
443 static const unsigned sw_led2_1_pins[] = { 84, 85 };
444 
445 static const unsigned sdio1_mmc_pins[] = { 90, 91, 92 };
446 
447 static const unsigned cam_led_pins[] = { 156, 157, 158, 159, 160 };
448 static const unsigned sw_led1_pins[] = { 156, 157, 158, 159 };
449 
450 static const unsigned cam_0_pins[] = { 169, 170, 171, 169, 170 };
451 
452 static const unsigned cam_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
453 	168 };
454 static const unsigned sram_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
455 	168 };
456 
457 static const unsigned qspi_1_pins[] = { 108, 109 };
458 
459 static const unsigned smart_card0_fcb_pins[] = { 45 };
460 static const unsigned i2s0_1_pins[] = { 45 };
461 
462 static const unsigned smart_card1_fcb_pins[] = { 51 };
463 static const unsigned i2s1_1_pins[] = { 51 };
464 
465 static const unsigned gpio0_3p3_pins[] = { 176 };
466 static const unsigned usb0_oc_pins[] = { 176 };
467 
468 static const unsigned gpio1_3p3_pins[] = { 177 };
469 static const unsigned usb1_oc_pins[] = { 177 };
470 
471 static const unsigned gpio2_3p3_pins[] = { 178 };
472 static const unsigned usb2_oc_pins[] = { 178 };
473 
474 #define CYGNUS_PIN_GROUP(group_name, off, sh, al)	\
475 {							\
476 	.name = __stringify(group_name) "_grp",		\
477 	.pins = group_name ## _pins,			\
478 	.num_pins = ARRAY_SIZE(group_name ## _pins),	\
479 	.mux = {					\
480 		.offset = off,				\
481 		.shift = sh,				\
482 		.alt = al,				\
483 	}						\
484 }
485 
486 /*
487  * List of Cygnus pin groups
488  */
489 static const struct cygnus_pin_group cygnus_pin_groups[] = {
490 	CYGNUS_PIN_GROUP(i2s2_0, 0x0, 0, 2),
491 	CYGNUS_PIN_GROUP(i2s2_1, 0x0, 4, 2),
492 	CYGNUS_PIN_GROUP(i2s2_2, 0x0, 8, 2),
493 	CYGNUS_PIN_GROUP(i2s2_3, 0x0, 12, 2),
494 	CYGNUS_PIN_GROUP(i2s2_4, 0x0, 16, 2),
495 	CYGNUS_PIN_GROUP(pwm4, 0x0, 20, 0),
496 	CYGNUS_PIN_GROUP(pwm5, 0x0, 24, 2),
497 	CYGNUS_PIN_GROUP(key0, 0x4, 0, 1),
498 	CYGNUS_PIN_GROUP(key1, 0x4, 4, 1),
499 	CYGNUS_PIN_GROUP(key2, 0x4, 8, 1),
500 	CYGNUS_PIN_GROUP(key3, 0x4, 12, 1),
501 	CYGNUS_PIN_GROUP(key4, 0x4, 16, 1),
502 	CYGNUS_PIN_GROUP(key5, 0x4, 20, 1),
503 	CYGNUS_PIN_GROUP(key6, 0x4, 24, 1),
504 	CYGNUS_PIN_GROUP(audio_dte0, 0x4, 24, 2),
505 	CYGNUS_PIN_GROUP(key7, 0x4, 28, 1),
506 	CYGNUS_PIN_GROUP(audio_dte1, 0x4, 28, 2),
507 	CYGNUS_PIN_GROUP(key8, 0x8, 0, 1),
508 	CYGNUS_PIN_GROUP(key9, 0x8, 4, 1),
509 	CYGNUS_PIN_GROUP(key10, 0x8, 8, 1),
510 	CYGNUS_PIN_GROUP(key11, 0x8, 12, 1),
511 	CYGNUS_PIN_GROUP(key12, 0x8, 16, 1),
512 	CYGNUS_PIN_GROUP(key13, 0x8, 20, 1),
513 	CYGNUS_PIN_GROUP(key14, 0x8, 24, 1),
514 	CYGNUS_PIN_GROUP(audio_dte2, 0x8, 24, 2),
515 	CYGNUS_PIN_GROUP(key15, 0x8, 28, 1),
516 	CYGNUS_PIN_GROUP(audio_dte3, 0x8, 28, 2),
517 	CYGNUS_PIN_GROUP(pwm0, 0xc, 0, 0),
518 	CYGNUS_PIN_GROUP(pwm1, 0xc, 4, 0),
519 	CYGNUS_PIN_GROUP(pwm2, 0xc, 8, 0),
520 	CYGNUS_PIN_GROUP(pwm3, 0xc, 12, 0),
521 	CYGNUS_PIN_GROUP(sdio0, 0xc, 16, 0),
522 	CYGNUS_PIN_GROUP(smart_card0, 0xc, 20, 0),
523 	CYGNUS_PIN_GROUP(i2s0_0, 0xc, 20, 1),
524 	CYGNUS_PIN_GROUP(spdif, 0xc, 20, 1),
525 	CYGNUS_PIN_GROUP(smart_card1, 0xc, 24, 0),
526 	CYGNUS_PIN_GROUP(i2s1_0, 0xc, 24, 1),
527 	CYGNUS_PIN_GROUP(spi0, 0x10, 0, 0),
528 	CYGNUS_PIN_GROUP(spi1, 0x10, 4, 0),
529 	CYGNUS_PIN_GROUP(spi2, 0x10, 8, 0),
530 	CYGNUS_PIN_GROUP(spi3, 0x10, 12, 0),
531 	CYGNUS_PIN_GROUP(sw_led0_0, 0x10, 12, 2),
532 	CYGNUS_PIN_GROUP(d1w, 0x10, 16, 0),
533 	CYGNUS_PIN_GROUP(uart4, 0x10, 16, 1),
534 	CYGNUS_PIN_GROUP(sw_led2_0, 0x10, 16, 2),
535 	CYGNUS_PIN_GROUP(lcd, 0x10, 20, 0),
536 	CYGNUS_PIN_GROUP(sram_0, 0x10, 20, 1),
537 	CYGNUS_PIN_GROUP(spi5, 0x10, 20, 2),
538 	CYGNUS_PIN_GROUP(uart0, 0x14, 0, 0),
539 	CYGNUS_PIN_GROUP(sw_led0_1, 0x14, 0, 2),
540 	CYGNUS_PIN_GROUP(uart1_dte, 0x14, 4, 0),
541 	CYGNUS_PIN_GROUP(uart2, 0x14, 4, 1),
542 	CYGNUS_PIN_GROUP(uart1, 0x14, 8, 0),
543 	CYGNUS_PIN_GROUP(uart3, 0x14, 12, 0),
544 	CYGNUS_PIN_GROUP(qspi_0, 0x14, 16, 0),
545 	CYGNUS_PIN_GROUP(nand, 0x14, 20, 0),
546 	CYGNUS_PIN_GROUP(sdio0_cd, 0x18, 0, 0),
547 	CYGNUS_PIN_GROUP(sdio0_mmc, 0x18, 4, 0),
548 	CYGNUS_PIN_GROUP(sdio1_data_0, 0x18, 8, 0),
549 	CYGNUS_PIN_GROUP(can0, 0x18, 8, 1),
550 	CYGNUS_PIN_GROUP(spi4_0, 0x18, 8, 2),
551 	CYGNUS_PIN_GROUP(sdio1_data_1, 0x18, 12, 0),
552 	CYGNUS_PIN_GROUP(can1, 0x18, 12, 1),
553 	CYGNUS_PIN_GROUP(spi4_1, 0x18, 12, 2),
554 	CYGNUS_PIN_GROUP(sdio1_cd, 0x18, 16, 0),
555 	CYGNUS_PIN_GROUP(sdio1_led, 0x18, 20, 0),
556 	CYGNUS_PIN_GROUP(sw_led2_1, 0x18, 20, 2),
557 	CYGNUS_PIN_GROUP(sdio1_mmc, 0x18, 24, 0),
558 	CYGNUS_PIN_GROUP(cam_led, 0x1c, 0, 0),
559 	CYGNUS_PIN_GROUP(sw_led1, 0x1c, 0, 1),
560 	CYGNUS_PIN_GROUP(cam_0, 0x1c, 4, 0),
561 	CYGNUS_PIN_GROUP(cam_1, 0x1c, 8, 0),
562 	CYGNUS_PIN_GROUP(sram_1, 0x1c, 8, 1),
563 	CYGNUS_PIN_GROUP(qspi_1, 0x1c, 12, 0),
564 	CYGNUS_PIN_GROUP(bsc1, 0x1c, 16, 0),
565 	CYGNUS_PIN_GROUP(pcie_clkreq, 0x1c, 16, 1),
566 	CYGNUS_PIN_GROUP(smart_card0_fcb, 0x20, 0, 0),
567 	CYGNUS_PIN_GROUP(i2s0_1, 0x20, 0, 1),
568 	CYGNUS_PIN_GROUP(smart_card1_fcb, 0x20, 4, 0),
569 	CYGNUS_PIN_GROUP(i2s1_1, 0x20, 4, 1),
570 	CYGNUS_PIN_GROUP(gpio0_3p3, 0x28, 0, 0),
571 	CYGNUS_PIN_GROUP(usb0_oc, 0x28, 0, 1),
572 	CYGNUS_PIN_GROUP(gpio1_3p3, 0x28, 4, 0),
573 	CYGNUS_PIN_GROUP(usb1_oc, 0x28, 4, 1),
574 	CYGNUS_PIN_GROUP(gpio2_3p3, 0x28, 8, 0),
575 	CYGNUS_PIN_GROUP(usb2_oc, 0x28, 8, 1),
576 };
577 
578 /*
579  * List of groups supported by functions
580  */
581 static const char * const i2s0_grps[] = { "i2s0_0_grp", "i2s0_1_grp" };
582 static const char * const i2s1_grps[] = { "i2s1_0_grp", "i2s1_1_grp" };
583 static const char * const i2s2_grps[] = { "i2s2_0_grp", "i2s2_1_grp",
584 	"i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" };
585 static const char * const spdif_grps[] = { "spdif_grp" };
586 static const char * const pwm0_grps[] = { "pwm0_grp" };
587 static const char * const pwm1_grps[] = { "pwm1_grp" };
588 static const char * const pwm2_grps[] = { "pwm2_grp" };
589 static const char * const pwm3_grps[] = { "pwm3_grp" };
590 static const char * const pwm4_grps[] = { "pwm4_grp" };
591 static const char * const pwm5_grps[] = { "pwm5_grp" };
592 static const char * const key_grps[] = { "key0_grp", "key1_grp", "key2_grp",
593 	"key3_grp", "key4_grp", "key5_grp", "key6_grp", "key7_grp", "key8_grp",
594 	"key9_grp", "key10_grp", "key11_grp", "key12_grp", "key13_grp",
595 	"key14_grp", "key15_grp" };
596 static const char * const audio_dte_grps[] = { "audio_dte0_grp",
597 	"audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" };
598 static const char * const smart_card0_grps[] = { "smart_card0_grp",
599 	"smart_card0_fcb_grp" };
600 static const char * const smart_card1_grps[] = { "smart_card1_grp",
601 	"smart_card1_fcb_grp" };
602 static const char * const spi0_grps[] = { "spi0_grp" };
603 static const char * const spi1_grps[] = { "spi1_grp" };
604 static const char * const spi2_grps[] = { "spi2_grp" };
605 static const char * const spi3_grps[] = { "spi3_grp" };
606 static const char * const spi4_grps[] = { "spi4_0_grp", "spi4_1_grp" };
607 static const char * const spi5_grps[] = { "spi5_grp" };
608 
609 static const char * const sw_led0_grps[] = { "sw_led0_0_grp",
610 	"sw_led0_1_grp" };
611 static const char * const sw_led1_grps[] = { "sw_led1_grp" };
612 static const char * const sw_led2_grps[] = { "sw_led2_0_grp",
613 	"sw_led2_1_grp" };
614 static const char * const d1w_grps[] = { "d1w_grp" };
615 static const char * const lcd_grps[] = { "lcd_grp" };
616 static const char * const sram_grps[] = { "sram_0_grp", "sram_1_grp" };
617 
618 static const char * const uart0_grps[] = { "uart0_grp" };
619 static const char * const uart1_grps[] = { "uart1_grp", "uart1_dte_grp" };
620 static const char * const uart2_grps[] = { "uart2_grp" };
621 static const char * const uart3_grps[] = { "uart3_grp" };
622 static const char * const uart4_grps[] = { "uart4_grp" };
623 static const char * const qspi_grps[] = { "qspi_0_grp", "qspi_1_grp" };
624 static const char * const nand_grps[] = { "nand_grp" };
625 static const char * const sdio0_grps[] = { "sdio0_grp", "sdio0_cd_grp",
626 	"sdio0_mmc_grp" };
627 static const char * const sdio1_grps[] = { "sdio1_data_0_grp",
628 	"sdio1_data_1_grp", "sdio1_cd_grp", "sdio1_led_grp", "sdio1_mmc_grp" };
629 static const char * const can0_grps[] = { "can0_grp" };
630 static const char * const can1_grps[] = { "can1_grp" };
631 static const char * const cam_grps[] = { "cam_led_grp", "cam_0_grp",
632 	"cam_1_grp" };
633 static const char * const bsc1_grps[] = { "bsc1_grp" };
634 static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" };
635 static const char * const usb0_oc_grps[] = { "usb0_oc_grp" };
636 static const char * const usb1_oc_grps[] = { "usb1_oc_grp" };
637 static const char * const usb2_oc_grps[] = { "usb2_oc_grp" };
638 
639 #define CYGNUS_PIN_FUNCTION(func)				\
640 {								\
641 	.name = #func,						\
642 	.groups = func ## _grps,				\
643 	.num_groups = ARRAY_SIZE(func ## _grps),		\
644 }
645 
646 /*
647  * List of supported functions in Cygnus
648  */
649 static const struct cygnus_pin_function cygnus_pin_functions[] = {
650 	CYGNUS_PIN_FUNCTION(i2s0),
651 	CYGNUS_PIN_FUNCTION(i2s1),
652 	CYGNUS_PIN_FUNCTION(i2s2),
653 	CYGNUS_PIN_FUNCTION(spdif),
654 	CYGNUS_PIN_FUNCTION(pwm0),
655 	CYGNUS_PIN_FUNCTION(pwm1),
656 	CYGNUS_PIN_FUNCTION(pwm2),
657 	CYGNUS_PIN_FUNCTION(pwm3),
658 	CYGNUS_PIN_FUNCTION(pwm4),
659 	CYGNUS_PIN_FUNCTION(pwm5),
660 	CYGNUS_PIN_FUNCTION(key),
661 	CYGNUS_PIN_FUNCTION(audio_dte),
662 	CYGNUS_PIN_FUNCTION(smart_card0),
663 	CYGNUS_PIN_FUNCTION(smart_card1),
664 	CYGNUS_PIN_FUNCTION(spi0),
665 	CYGNUS_PIN_FUNCTION(spi1),
666 	CYGNUS_PIN_FUNCTION(spi2),
667 	CYGNUS_PIN_FUNCTION(spi3),
668 	CYGNUS_PIN_FUNCTION(spi4),
669 	CYGNUS_PIN_FUNCTION(spi5),
670 	CYGNUS_PIN_FUNCTION(sw_led0),
671 	CYGNUS_PIN_FUNCTION(sw_led1),
672 	CYGNUS_PIN_FUNCTION(sw_led2),
673 	CYGNUS_PIN_FUNCTION(d1w),
674 	CYGNUS_PIN_FUNCTION(lcd),
675 	CYGNUS_PIN_FUNCTION(sram),
676 	CYGNUS_PIN_FUNCTION(uart0),
677 	CYGNUS_PIN_FUNCTION(uart1),
678 	CYGNUS_PIN_FUNCTION(uart2),
679 	CYGNUS_PIN_FUNCTION(uart3),
680 	CYGNUS_PIN_FUNCTION(uart4),
681 	CYGNUS_PIN_FUNCTION(qspi),
682 	CYGNUS_PIN_FUNCTION(nand),
683 	CYGNUS_PIN_FUNCTION(sdio0),
684 	CYGNUS_PIN_FUNCTION(sdio1),
685 	CYGNUS_PIN_FUNCTION(can0),
686 	CYGNUS_PIN_FUNCTION(can1),
687 	CYGNUS_PIN_FUNCTION(cam),
688 	CYGNUS_PIN_FUNCTION(bsc1),
689 	CYGNUS_PIN_FUNCTION(pcie_clkreq),
690 	CYGNUS_PIN_FUNCTION(usb0_oc),
691 	CYGNUS_PIN_FUNCTION(usb1_oc),
692 	CYGNUS_PIN_FUNCTION(usb2_oc),
693 };
694 
695 static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev)
696 {
697 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
698 
699 	return pinctrl->num_groups;
700 }
701 
702 static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev,
703 					 unsigned selector)
704 {
705 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
706 
707 	return pinctrl->groups[selector].name;
708 }
709 
710 static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev,
711 				 unsigned selector, const unsigned **pins,
712 				 unsigned *num_pins)
713 {
714 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
715 
716 	*pins = pinctrl->groups[selector].pins;
717 	*num_pins = pinctrl->groups[selector].num_pins;
718 
719 	return 0;
720 }
721 
722 static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
723 				struct seq_file *s, unsigned offset)
724 {
725 	seq_printf(s, " %s", dev_name(pctrl_dev->dev));
726 }
727 
728 static const struct pinctrl_ops cygnus_pinctrl_ops = {
729 	.get_groups_count = cygnus_get_groups_count,
730 	.get_group_name = cygnus_get_group_name,
731 	.get_group_pins = cygnus_get_group_pins,
732 	.pin_dbg_show = cygnus_pin_dbg_show,
733 	.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
734 	.dt_free_map = pinctrl_utils_free_map,
735 };
736 
737 static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev)
738 {
739 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
740 
741 	return pinctrl->num_functions;
742 }
743 
744 static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev,
745 					    unsigned selector)
746 {
747 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
748 
749 	return pinctrl->functions[selector].name;
750 }
751 
752 static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev,
753 				      unsigned selector,
754 				      const char * const **groups,
755 				      unsigned * const num_groups)
756 {
757 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
758 
759 	*groups = pinctrl->functions[selector].groups;
760 	*num_groups = pinctrl->functions[selector].num_groups;
761 
762 	return 0;
763 }
764 
765 static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl,
766 			     const struct cygnus_pin_function *func,
767 			     const struct cygnus_pin_group *grp,
768 			     struct cygnus_mux_log *mux_log)
769 {
770 	const struct cygnus_mux *mux = &grp->mux;
771 	int i;
772 	u32 val, mask = 0x7;
773 	unsigned long flags;
774 
775 	for (i = 0; i < CYGNUS_NUM_IOMUX; i++) {
776 		if (mux->offset != mux_log[i].mux.offset ||
777 		    mux->shift != mux_log[i].mux.shift)
778 			continue;
779 
780 		/* match found if we reach here */
781 
782 		/* if this is a new configuration, just do it! */
783 		if (!mux_log[i].is_configured)
784 			break;
785 
786 		/*
787 		 * IOMUX has been configured previously and one is trying to
788 		 * configure it to a different function
789 		 */
790 		if (mux_log[i].mux.alt != mux->alt) {
791 			dev_err(pinctrl->dev,
792 				"double configuration error detected!\n");
793 			dev_err(pinctrl->dev, "func:%s grp:%s\n",
794 				func->name, grp->name);
795 			return -EINVAL;
796 		} else {
797 			/*
798 			 * One tries to configure it to the same function.
799 			 * Just quit and don't bother
800 			 */
801 			return 0;
802 		}
803 	}
804 
805 	mux_log[i].mux.alt = mux->alt;
806 	mux_log[i].is_configured = true;
807 
808 	spin_lock_irqsave(&pinctrl->lock, flags);
809 
810 	val = readl(pinctrl->base0 + grp->mux.offset);
811 	val &= ~(mask << grp->mux.shift);
812 	val |= grp->mux.alt << grp->mux.shift;
813 	writel(val, pinctrl->base0 + grp->mux.offset);
814 
815 	spin_unlock_irqrestore(&pinctrl->lock, flags);
816 
817 	return 0;
818 }
819 
820 static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
821 				 unsigned func_select, unsigned grp_select)
822 {
823 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
824 	const struct cygnus_pin_function *func =
825 		&pinctrl->functions[func_select];
826 	const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select];
827 
828 	dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
829 		func_select, func->name, grp_select, grp->name);
830 
831 	dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
832 		grp->mux.offset, grp->mux.shift, grp->mux.alt);
833 
834 	return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
835 }
836 
837 static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
838 				      struct pinctrl_gpio_range *range,
839 				      unsigned pin)
840 {
841 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
842 	const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
843 	u32 val;
844 	unsigned long flags;
845 
846 	/* not all pins support GPIO pinmux override */
847 	if (!mux->is_supported)
848 		return -ENOTSUPP;
849 
850 	spin_lock_irqsave(&pinctrl->lock, flags);
851 
852 	val = readl(pinctrl->base1 + mux->offset);
853 	val |= 0x3 << mux->shift;
854 	writel(val, pinctrl->base1 + mux->offset);
855 
856 	spin_unlock_irqrestore(&pinctrl->lock, flags);
857 
858 	dev_dbg(pctrl_dev->dev,
859 		"gpio request enable pin=%u offset=0x%x shift=%u\n",
860 		pin, mux->offset, mux->shift);
861 
862 	return 0;
863 }
864 
865 static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
866 				     struct pinctrl_gpio_range *range,
867 				     unsigned pin)
868 {
869 	struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
870 	struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
871 	u32 val;
872 	unsigned long flags;
873 
874 	if (!mux->is_supported)
875 		return;
876 
877 	spin_lock_irqsave(&pinctrl->lock, flags);
878 
879 	val = readl(pinctrl->base1 + mux->offset);
880 	val &= ~(0x3 << mux->shift);
881 	writel(val, pinctrl->base1 + mux->offset);
882 
883 	spin_unlock_irqrestore(&pinctrl->lock, flags);
884 
885 	dev_err(pctrl_dev->dev,
886 		"gpio disable free pin=%u offset=0x%x shift=%u\n",
887 		pin, mux->offset, mux->shift);
888 }
889 
890 static const struct pinmux_ops cygnus_pinmux_ops = {
891 	.get_functions_count = cygnus_get_functions_count,
892 	.get_function_name = cygnus_get_function_name,
893 	.get_function_groups = cygnus_get_function_groups,
894 	.set_mux = cygnus_pinmux_set_mux,
895 	.gpio_request_enable = cygnus_gpio_request_enable,
896 	.gpio_disable_free = cygnus_gpio_disable_free,
897 };
898 
899 static struct pinctrl_desc cygnus_pinctrl_desc = {
900 	.name = "cygnus-pinmux",
901 	.pctlops = &cygnus_pinctrl_ops,
902 	.pmxops = &cygnus_pinmux_ops,
903 };
904 
905 static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
906 {
907 	struct cygnus_mux_log *log;
908 	unsigned int i, j;
909 
910 	pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX,
911 					sizeof(struct cygnus_mux_log),
912 					GFP_KERNEL);
913 	if (!pinctrl->mux_log)
914 		return -ENOMEM;
915 
916 	for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {
917 		for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
918 			log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG
919 				+ j];
920 			log->mux.offset = i * 4;
921 			log->mux.shift = j * 4;
922 			log->mux.alt = 0;
923 			log->is_configured = false;
924 		}
925 	}
926 
927 	return 0;
928 }
929 
930 static int cygnus_pinmux_probe(struct platform_device *pdev)
931 {
932 	struct cygnus_pinctrl *pinctrl;
933 	int i, ret;
934 	struct pinctrl_pin_desc *pins;
935 	unsigned num_pins = ARRAY_SIZE(cygnus_pins);
936 
937 	pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
938 	if (!pinctrl)
939 		return -ENOMEM;
940 
941 	pinctrl->dev = &pdev->dev;
942 	platform_set_drvdata(pdev, pinctrl);
943 	spin_lock_init(&pinctrl->lock);
944 
945 	pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
946 	if (IS_ERR(pinctrl->base0)) {
947 		dev_err(&pdev->dev, "unable to map I/O space\n");
948 		return PTR_ERR(pinctrl->base0);
949 	}
950 
951 	pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1);
952 	if (IS_ERR(pinctrl->base1)) {
953 		dev_err(&pdev->dev, "unable to map I/O space\n");
954 		return PTR_ERR(pinctrl->base1);
955 	}
956 
957 	ret = cygnus_mux_log_init(pinctrl);
958 	if (ret) {
959 		dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
960 		return ret;
961 	}
962 
963 	pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
964 	if (!pins)
965 		return -ENOMEM;
966 
967 	for (i = 0; i < num_pins; i++) {
968 		pins[i].number = cygnus_pins[i].pin;
969 		pins[i].name = cygnus_pins[i].name;
970 		pins[i].drv_data = &cygnus_pins[i].gpio_mux;
971 	}
972 
973 	pinctrl->groups = cygnus_pin_groups;
974 	pinctrl->num_groups = ARRAY_SIZE(cygnus_pin_groups);
975 	pinctrl->functions = cygnus_pin_functions;
976 	pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);
977 	cygnus_pinctrl_desc.pins = pins;
978 	cygnus_pinctrl_desc.npins = num_pins;
979 
980 	pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &cygnus_pinctrl_desc,
981 			pinctrl);
982 	if (IS_ERR(pinctrl->pctl)) {
983 		dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n");
984 		return PTR_ERR(pinctrl->pctl);
985 	}
986 
987 	return 0;
988 }
989 
990 static const struct of_device_id cygnus_pinmux_of_match[] = {
991 	{ .compatible = "brcm,cygnus-pinmux" },
992 	{ }
993 };
994 
995 static struct platform_driver cygnus_pinmux_driver = {
996 	.driver = {
997 		.name = "cygnus-pinmux",
998 		.of_match_table = cygnus_pinmux_of_match,
999 		.suppress_bind_attrs = true,
1000 	},
1001 	.probe = cygnus_pinmux_probe,
1002 };
1003 
1004 static int __init cygnus_pinmux_init(void)
1005 {
1006 	return platform_driver_register(&cygnus_pinmux_driver);
1007 }
1008 arch_initcall(cygnus_pinmux_init);
1009