1 /* 2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) 3 * 4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 5 * 6 * This driver is inspired by: 7 * pinctrl-nomadik.c, please see original file for copyright information 8 * pinctrl-tegra.c, please see original file for copyright information 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/bitmap.h> 22 #include <linux/bug.h> 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/err.h> 26 #include <linux/gpio.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/irq.h> 30 #include <linux/irqdesc.h> 31 #include <linux/irqdomain.h> 32 #include <linux/module.h> 33 #include <linux/of_address.h> 34 #include <linux/of.h> 35 #include <linux/of_irq.h> 36 #include <linux/pinctrl/consumer.h> 37 #include <linux/pinctrl/machine.h> 38 #include <linux/pinctrl/pinconf.h> 39 #include <linux/pinctrl/pinctrl.h> 40 #include <linux/pinctrl/pinmux.h> 41 #include <linux/platform_device.h> 42 #include <linux/seq_file.h> 43 #include <linux/slab.h> 44 #include <linux/spinlock.h> 45 #include <linux/types.h> 46 47 #define MODULE_NAME "pinctrl-bcm2835" 48 #define BCM2835_NUM_GPIOS 54 49 #define BCM2835_NUM_BANKS 2 50 51 #define BCM2835_PIN_BITMAP_SZ \ 52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8) 53 54 /* GPIO register offsets */ 55 #define GPFSEL0 0x0 /* Function Select */ 56 #define GPSET0 0x1c /* Pin Output Set */ 57 #define GPCLR0 0x28 /* Pin Output Clear */ 58 #define GPLEV0 0x34 /* Pin Level */ 59 #define GPEDS0 0x40 /* Pin Event Detect Status */ 60 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ 61 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ 62 #define GPHEN0 0x64 /* Pin High Detect Enable */ 63 #define GPLEN0 0x70 /* Pin Low Detect Enable */ 64 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ 65 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ 66 #define GPPUD 0x94 /* Pin Pull-up/down Enable */ 67 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ 68 69 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) 70 #define FSEL_SHIFT(p) (((p) % 10) * 3) 71 #define GPIO_REG_OFFSET(p) ((p) / 32) 72 #define GPIO_REG_SHIFT(p) ((p) % 32) 73 74 enum bcm2835_pinconf_param { 75 /* argument: bcm2835_pinconf_pull */ 76 BCM2835_PINCONF_PARAM_PULL, 77 }; 78 79 enum bcm2835_pinconf_pull { 80 BCM2835_PINCONFIG_PULL_NONE, 81 BCM2835_PINCONFIG_PULL_DOWN, 82 BCM2835_PINCONFIG_PULL_UP, 83 }; 84 85 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 86 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 87 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 88 89 struct bcm2835_gpio_irqdata { 90 struct bcm2835_pinctrl *pc; 91 int bank; 92 }; 93 94 struct bcm2835_pinctrl { 95 struct device *dev; 96 void __iomem *base; 97 int irq[BCM2835_NUM_BANKS]; 98 99 /* note: locking assumes each bank will have its own unsigned long */ 100 unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; 101 unsigned int irq_type[BCM2835_NUM_GPIOS]; 102 103 struct pinctrl_dev *pctl_dev; 104 struct irq_domain *irq_domain; 105 struct gpio_chip gpio_chip; 106 struct pinctrl_gpio_range gpio_range; 107 108 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS]; 109 spinlock_t irq_lock[BCM2835_NUM_BANKS]; 110 }; 111 112 static struct lock_class_key gpio_lock_class; 113 114 /* pins are just named GPIO0..GPIO53 */ 115 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 116 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 117 BCM2835_GPIO_PIN(0), 118 BCM2835_GPIO_PIN(1), 119 BCM2835_GPIO_PIN(2), 120 BCM2835_GPIO_PIN(3), 121 BCM2835_GPIO_PIN(4), 122 BCM2835_GPIO_PIN(5), 123 BCM2835_GPIO_PIN(6), 124 BCM2835_GPIO_PIN(7), 125 BCM2835_GPIO_PIN(8), 126 BCM2835_GPIO_PIN(9), 127 BCM2835_GPIO_PIN(10), 128 BCM2835_GPIO_PIN(11), 129 BCM2835_GPIO_PIN(12), 130 BCM2835_GPIO_PIN(13), 131 BCM2835_GPIO_PIN(14), 132 BCM2835_GPIO_PIN(15), 133 BCM2835_GPIO_PIN(16), 134 BCM2835_GPIO_PIN(17), 135 BCM2835_GPIO_PIN(18), 136 BCM2835_GPIO_PIN(19), 137 BCM2835_GPIO_PIN(20), 138 BCM2835_GPIO_PIN(21), 139 BCM2835_GPIO_PIN(22), 140 BCM2835_GPIO_PIN(23), 141 BCM2835_GPIO_PIN(24), 142 BCM2835_GPIO_PIN(25), 143 BCM2835_GPIO_PIN(26), 144 BCM2835_GPIO_PIN(27), 145 BCM2835_GPIO_PIN(28), 146 BCM2835_GPIO_PIN(29), 147 BCM2835_GPIO_PIN(30), 148 BCM2835_GPIO_PIN(31), 149 BCM2835_GPIO_PIN(32), 150 BCM2835_GPIO_PIN(33), 151 BCM2835_GPIO_PIN(34), 152 BCM2835_GPIO_PIN(35), 153 BCM2835_GPIO_PIN(36), 154 BCM2835_GPIO_PIN(37), 155 BCM2835_GPIO_PIN(38), 156 BCM2835_GPIO_PIN(39), 157 BCM2835_GPIO_PIN(40), 158 BCM2835_GPIO_PIN(41), 159 BCM2835_GPIO_PIN(42), 160 BCM2835_GPIO_PIN(43), 161 BCM2835_GPIO_PIN(44), 162 BCM2835_GPIO_PIN(45), 163 BCM2835_GPIO_PIN(46), 164 BCM2835_GPIO_PIN(47), 165 BCM2835_GPIO_PIN(48), 166 BCM2835_GPIO_PIN(49), 167 BCM2835_GPIO_PIN(50), 168 BCM2835_GPIO_PIN(51), 169 BCM2835_GPIO_PIN(52), 170 BCM2835_GPIO_PIN(53), 171 }; 172 173 /* one pin per group */ 174 static const char * const bcm2835_gpio_groups[] = { 175 "gpio0", 176 "gpio1", 177 "gpio2", 178 "gpio3", 179 "gpio4", 180 "gpio5", 181 "gpio6", 182 "gpio7", 183 "gpio8", 184 "gpio9", 185 "gpio10", 186 "gpio11", 187 "gpio12", 188 "gpio13", 189 "gpio14", 190 "gpio15", 191 "gpio16", 192 "gpio17", 193 "gpio18", 194 "gpio19", 195 "gpio20", 196 "gpio21", 197 "gpio22", 198 "gpio23", 199 "gpio24", 200 "gpio25", 201 "gpio26", 202 "gpio27", 203 "gpio28", 204 "gpio29", 205 "gpio30", 206 "gpio31", 207 "gpio32", 208 "gpio33", 209 "gpio34", 210 "gpio35", 211 "gpio36", 212 "gpio37", 213 "gpio38", 214 "gpio39", 215 "gpio40", 216 "gpio41", 217 "gpio42", 218 "gpio43", 219 "gpio44", 220 "gpio45", 221 "gpio46", 222 "gpio47", 223 "gpio48", 224 "gpio49", 225 "gpio50", 226 "gpio51", 227 "gpio52", 228 "gpio53", 229 }; 230 231 enum bcm2835_fsel { 232 BCM2835_FSEL_GPIO_IN = 0, 233 BCM2835_FSEL_GPIO_OUT = 1, 234 BCM2835_FSEL_ALT0 = 4, 235 BCM2835_FSEL_ALT1 = 5, 236 BCM2835_FSEL_ALT2 = 6, 237 BCM2835_FSEL_ALT3 = 7, 238 BCM2835_FSEL_ALT4 = 3, 239 BCM2835_FSEL_ALT5 = 2, 240 BCM2835_FSEL_COUNT = 8, 241 BCM2835_FSEL_MASK = 0x7, 242 }; 243 244 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { 245 [BCM2835_FSEL_GPIO_IN] = "gpio_in", 246 [BCM2835_FSEL_GPIO_OUT] = "gpio_out", 247 [BCM2835_FSEL_ALT0] = "alt0", 248 [BCM2835_FSEL_ALT1] = "alt1", 249 [BCM2835_FSEL_ALT2] = "alt2", 250 [BCM2835_FSEL_ALT3] = "alt3", 251 [BCM2835_FSEL_ALT4] = "alt4", 252 [BCM2835_FSEL_ALT5] = "alt5", 253 }; 254 255 static const char * const irq_type_names[] = { 256 [IRQ_TYPE_NONE] = "none", 257 [IRQ_TYPE_EDGE_RISING] = "edge-rising", 258 [IRQ_TYPE_EDGE_FALLING] = "edge-falling", 259 [IRQ_TYPE_EDGE_BOTH] = "edge-both", 260 [IRQ_TYPE_LEVEL_HIGH] = "level-high", 261 [IRQ_TYPE_LEVEL_LOW] = "level-low", 262 }; 263 264 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 265 { 266 return readl(pc->base + reg); 267 } 268 269 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, 270 u32 val) 271 { 272 writel(val, pc->base + reg); 273 } 274 275 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, 276 unsigned bit) 277 { 278 reg += GPIO_REG_OFFSET(bit) * 4; 279 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; 280 } 281 282 /* note NOT a read/modify/write cycle */ 283 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, 284 unsigned reg, unsigned bit) 285 { 286 reg += GPIO_REG_OFFSET(bit) * 4; 287 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); 288 } 289 290 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( 291 struct bcm2835_pinctrl *pc, unsigned pin) 292 { 293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 295 296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, 297 bcm2835_functions[status]); 298 299 return status; 300 } 301 302 static inline void bcm2835_pinctrl_fsel_set( 303 struct bcm2835_pinctrl *pc, unsigned pin, 304 enum bcm2835_fsel fsel) 305 { 306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 308 309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, 310 bcm2835_functions[cur]); 311 312 if (cur == fsel) 313 return; 314 315 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { 316 /* always transition through GPIO_IN */ 317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); 319 320 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, 321 bcm2835_functions[BCM2835_FSEL_GPIO_IN]); 322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 323 } 324 325 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 326 val |= fsel << FSEL_SHIFT(pin); 327 328 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, 329 bcm2835_functions[fsel]); 330 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 331 } 332 333 static int bcm2835_gpio_request(struct gpio_chip *chip, unsigned offset) 334 { 335 return pinctrl_request_gpio(chip->base + offset); 336 } 337 338 static void bcm2835_gpio_free(struct gpio_chip *chip, unsigned offset) 339 { 340 pinctrl_free_gpio(chip->base + offset); 341 } 342 343 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 344 { 345 return pinctrl_gpio_direction_input(chip->base + offset); 346 } 347 348 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) 349 { 350 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); 351 352 return bcm2835_gpio_get_bit(pc, GPLEV0, offset); 353 } 354 355 static int bcm2835_gpio_direction_output(struct gpio_chip *chip, 356 unsigned offset, int value) 357 { 358 return pinctrl_gpio_direction_output(chip->base + offset); 359 } 360 361 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 362 { 363 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); 364 365 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 366 } 367 368 static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 369 { 370 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); 371 372 return irq_linear_revmap(pc->irq_domain, offset); 373 } 374 375 static struct gpio_chip bcm2835_gpio_chip = { 376 .label = MODULE_NAME, 377 .owner = THIS_MODULE, 378 .request = bcm2835_gpio_request, 379 .free = bcm2835_gpio_free, 380 .direction_input = bcm2835_gpio_direction_input, 381 .direction_output = bcm2835_gpio_direction_output, 382 .get = bcm2835_gpio_get, 383 .set = bcm2835_gpio_set, 384 .to_irq = bcm2835_gpio_to_irq, 385 .base = -1, 386 .ngpio = BCM2835_NUM_GPIOS, 387 .can_sleep = false, 388 }; 389 390 static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) 391 { 392 struct bcm2835_gpio_irqdata *irqdata = dev_id; 393 struct bcm2835_pinctrl *pc = irqdata->pc; 394 int bank = irqdata->bank; 395 unsigned long events; 396 unsigned offset; 397 unsigned gpio; 398 unsigned int type; 399 400 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); 401 events &= pc->enabled_irq_map[bank]; 402 for_each_set_bit(offset, &events, 32) { 403 gpio = (32 * bank) + offset; 404 type = pc->irq_type[gpio]; 405 406 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); 407 } 408 return events ? IRQ_HANDLED : IRQ_NONE; 409 } 410 411 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 412 unsigned reg, unsigned offset, bool enable) 413 { 414 u32 value; 415 reg += GPIO_REG_OFFSET(offset) * 4; 416 value = bcm2835_gpio_rd(pc, reg); 417 if (enable) 418 value |= BIT(GPIO_REG_SHIFT(offset)); 419 else 420 value &= ~(BIT(GPIO_REG_SHIFT(offset))); 421 bcm2835_gpio_wr(pc, reg, value); 422 } 423 424 /* fast path for IRQ handler */ 425 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 426 unsigned offset, bool enable) 427 { 428 switch (pc->irq_type[offset]) { 429 case IRQ_TYPE_EDGE_RISING: 430 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 431 break; 432 433 case IRQ_TYPE_EDGE_FALLING: 434 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 435 break; 436 437 case IRQ_TYPE_EDGE_BOTH: 438 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 439 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 440 break; 441 442 case IRQ_TYPE_LEVEL_HIGH: 443 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); 444 break; 445 446 case IRQ_TYPE_LEVEL_LOW: 447 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); 448 break; 449 } 450 } 451 452 static void bcm2835_gpio_irq_enable(struct irq_data *data) 453 { 454 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 455 unsigned gpio = irqd_to_hwirq(data); 456 unsigned offset = GPIO_REG_SHIFT(gpio); 457 unsigned bank = GPIO_REG_OFFSET(gpio); 458 unsigned long flags; 459 460 spin_lock_irqsave(&pc->irq_lock[bank], flags); 461 set_bit(offset, &pc->enabled_irq_map[bank]); 462 bcm2835_gpio_irq_config(pc, gpio, true); 463 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 464 } 465 466 static void bcm2835_gpio_irq_disable(struct irq_data *data) 467 { 468 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 469 unsigned gpio = irqd_to_hwirq(data); 470 unsigned offset = GPIO_REG_SHIFT(gpio); 471 unsigned bank = GPIO_REG_OFFSET(gpio); 472 unsigned long flags; 473 474 spin_lock_irqsave(&pc->irq_lock[bank], flags); 475 bcm2835_gpio_irq_config(pc, gpio, false); 476 /* Clear events that were latched prior to clearing event sources */ 477 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 478 clear_bit(offset, &pc->enabled_irq_map[bank]); 479 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 480 } 481 482 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, 483 unsigned offset, unsigned int type) 484 { 485 switch (type) { 486 case IRQ_TYPE_NONE: 487 case IRQ_TYPE_EDGE_RISING: 488 case IRQ_TYPE_EDGE_FALLING: 489 case IRQ_TYPE_EDGE_BOTH: 490 case IRQ_TYPE_LEVEL_HIGH: 491 case IRQ_TYPE_LEVEL_LOW: 492 pc->irq_type[offset] = type; 493 break; 494 495 default: 496 return -EINVAL; 497 } 498 return 0; 499 } 500 501 /* slower path for reconfiguring IRQ type */ 502 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, 503 unsigned offset, unsigned int type) 504 { 505 switch (type) { 506 case IRQ_TYPE_NONE: 507 if (pc->irq_type[offset] != type) { 508 bcm2835_gpio_irq_config(pc, offset, false); 509 pc->irq_type[offset] = type; 510 } 511 break; 512 513 case IRQ_TYPE_EDGE_RISING: 514 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 515 /* RISING already enabled, disable FALLING */ 516 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 517 bcm2835_gpio_irq_config(pc, offset, false); 518 pc->irq_type[offset] = type; 519 } else if (pc->irq_type[offset] != type) { 520 bcm2835_gpio_irq_config(pc, offset, false); 521 pc->irq_type[offset] = type; 522 bcm2835_gpio_irq_config(pc, offset, true); 523 } 524 break; 525 526 case IRQ_TYPE_EDGE_FALLING: 527 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 528 /* FALLING already enabled, disable RISING */ 529 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 530 bcm2835_gpio_irq_config(pc, offset, false); 531 pc->irq_type[offset] = type; 532 } else if (pc->irq_type[offset] != type) { 533 bcm2835_gpio_irq_config(pc, offset, false); 534 pc->irq_type[offset] = type; 535 bcm2835_gpio_irq_config(pc, offset, true); 536 } 537 break; 538 539 case IRQ_TYPE_EDGE_BOTH: 540 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { 541 /* RISING already enabled, enable FALLING too */ 542 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 543 bcm2835_gpio_irq_config(pc, offset, true); 544 pc->irq_type[offset] = type; 545 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { 546 /* FALLING already enabled, enable RISING too */ 547 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 548 bcm2835_gpio_irq_config(pc, offset, true); 549 pc->irq_type[offset] = type; 550 } else if (pc->irq_type[offset] != type) { 551 bcm2835_gpio_irq_config(pc, offset, false); 552 pc->irq_type[offset] = type; 553 bcm2835_gpio_irq_config(pc, offset, true); 554 } 555 break; 556 557 case IRQ_TYPE_LEVEL_HIGH: 558 case IRQ_TYPE_LEVEL_LOW: 559 if (pc->irq_type[offset] != type) { 560 bcm2835_gpio_irq_config(pc, offset, false); 561 pc->irq_type[offset] = type; 562 bcm2835_gpio_irq_config(pc, offset, true); 563 } 564 break; 565 566 default: 567 return -EINVAL; 568 } 569 return 0; 570 } 571 572 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) 573 { 574 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 575 unsigned gpio = irqd_to_hwirq(data); 576 unsigned offset = GPIO_REG_SHIFT(gpio); 577 unsigned bank = GPIO_REG_OFFSET(gpio); 578 unsigned long flags; 579 int ret; 580 581 spin_lock_irqsave(&pc->irq_lock[bank], flags); 582 583 if (test_bit(offset, &pc->enabled_irq_map[bank])) 584 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); 585 else 586 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 587 588 if (type & IRQ_TYPE_EDGE_BOTH) 589 irq_set_handler_locked(data, handle_edge_irq); 590 else 591 irq_set_handler_locked(data, handle_level_irq); 592 593 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 594 595 return ret; 596 } 597 598 static void bcm2835_gpio_irq_ack(struct irq_data *data) 599 { 600 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 601 unsigned gpio = irqd_to_hwirq(data); 602 603 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 604 } 605 606 static struct irq_chip bcm2835_gpio_irq_chip = { 607 .name = MODULE_NAME, 608 .irq_enable = bcm2835_gpio_irq_enable, 609 .irq_disable = bcm2835_gpio_irq_disable, 610 .irq_set_type = bcm2835_gpio_irq_set_type, 611 .irq_ack = bcm2835_gpio_irq_ack, 612 .irq_mask = bcm2835_gpio_irq_disable, 613 .irq_unmask = bcm2835_gpio_irq_enable, 614 }; 615 616 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 617 { 618 return ARRAY_SIZE(bcm2835_gpio_groups); 619 } 620 621 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, 622 unsigned selector) 623 { 624 return bcm2835_gpio_groups[selector]; 625 } 626 627 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, 628 unsigned selector, 629 const unsigned **pins, 630 unsigned *num_pins) 631 { 632 *pins = &bcm2835_gpio_pins[selector].number; 633 *num_pins = 1; 634 635 return 0; 636 } 637 638 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 639 struct seq_file *s, 640 unsigned offset) 641 { 642 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 643 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 644 const char *fname = bcm2835_functions[fsel]; 645 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); 646 int irq = irq_find_mapping(pc->irq_domain, offset); 647 648 seq_printf(s, "function %s in %s; irq %d (%s)", 649 fname, value ? "hi" : "lo", 650 irq, irq_type_names[pc->irq_type[offset]]); 651 } 652 653 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, 654 struct pinctrl_map *maps, unsigned num_maps) 655 { 656 int i; 657 658 for (i = 0; i < num_maps; i++) 659 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 660 kfree(maps[i].data.configs.configs); 661 662 kfree(maps); 663 } 664 665 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, 666 struct device_node *np, u32 pin, u32 fnum, 667 struct pinctrl_map **maps) 668 { 669 struct pinctrl_map *map = *maps; 670 671 if (fnum >= ARRAY_SIZE(bcm2835_functions)) { 672 dev_err(pc->dev, "%s: invalid brcm,function %d\n", 673 of_node_full_name(np), fnum); 674 return -EINVAL; 675 } 676 677 map->type = PIN_MAP_TYPE_MUX_GROUP; 678 map->data.mux.group = bcm2835_gpio_groups[pin]; 679 map->data.mux.function = bcm2835_functions[fnum]; 680 (*maps)++; 681 682 return 0; 683 } 684 685 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, 686 struct device_node *np, u32 pin, u32 pull, 687 struct pinctrl_map **maps) 688 { 689 struct pinctrl_map *map = *maps; 690 unsigned long *configs; 691 692 if (pull > 2) { 693 dev_err(pc->dev, "%s: invalid brcm,pull %d\n", 694 of_node_full_name(np), pull); 695 return -EINVAL; 696 } 697 698 configs = kzalloc(sizeof(*configs), GFP_KERNEL); 699 if (!configs) 700 return -ENOMEM; 701 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull); 702 703 map->type = PIN_MAP_TYPE_CONFIGS_PIN; 704 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; 705 map->data.configs.configs = configs; 706 map->data.configs.num_configs = 1; 707 (*maps)++; 708 709 return 0; 710 } 711 712 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 713 struct device_node *np, 714 struct pinctrl_map **map, unsigned *num_maps) 715 { 716 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 717 struct property *pins, *funcs, *pulls; 718 int num_pins, num_funcs, num_pulls, maps_per_pin; 719 struct pinctrl_map *maps, *cur_map; 720 int i, err; 721 u32 pin, func, pull; 722 723 pins = of_find_property(np, "brcm,pins", NULL); 724 if (!pins) { 725 dev_err(pc->dev, "%s: missing brcm,pins property\n", 726 of_node_full_name(np)); 727 return -EINVAL; 728 } 729 730 funcs = of_find_property(np, "brcm,function", NULL); 731 pulls = of_find_property(np, "brcm,pull", NULL); 732 733 if (!funcs && !pulls) { 734 dev_err(pc->dev, 735 "%s: neither brcm,function nor brcm,pull specified\n", 736 of_node_full_name(np)); 737 return -EINVAL; 738 } 739 740 num_pins = pins->length / 4; 741 num_funcs = funcs ? (funcs->length / 4) : 0; 742 num_pulls = pulls ? (pulls->length / 4) : 0; 743 744 if (num_funcs > 1 && num_funcs != num_pins) { 745 dev_err(pc->dev, 746 "%s: brcm,function must have 1 or %d entries\n", 747 of_node_full_name(np), num_pins); 748 return -EINVAL; 749 } 750 751 if (num_pulls > 1 && num_pulls != num_pins) { 752 dev_err(pc->dev, 753 "%s: brcm,pull must have 1 or %d entries\n", 754 of_node_full_name(np), num_pins); 755 return -EINVAL; 756 } 757 758 maps_per_pin = 0; 759 if (num_funcs) 760 maps_per_pin++; 761 if (num_pulls) 762 maps_per_pin++; 763 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps), 764 GFP_KERNEL); 765 if (!maps) 766 return -ENOMEM; 767 768 for (i = 0; i < num_pins; i++) { 769 err = of_property_read_u32_index(np, "brcm,pins", i, &pin); 770 if (err) 771 goto out; 772 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) { 773 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n", 774 of_node_full_name(np), pin); 775 err = -EINVAL; 776 goto out; 777 } 778 779 if (num_funcs) { 780 err = of_property_read_u32_index(np, "brcm,function", 781 (num_funcs > 1) ? i : 0, &func); 782 if (err) 783 goto out; 784 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 785 func, &cur_map); 786 if (err) 787 goto out; 788 } 789 if (num_pulls) { 790 err = of_property_read_u32_index(np, "brcm,pull", 791 (num_funcs > 1) ? i : 0, &pull); 792 if (err) 793 goto out; 794 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 795 pull, &cur_map); 796 if (err) 797 goto out; 798 } 799 } 800 801 *map = maps; 802 *num_maps = num_pins * maps_per_pin; 803 804 return 0; 805 806 out: 807 kfree(maps); 808 return err; 809 } 810 811 static const struct pinctrl_ops bcm2835_pctl_ops = { 812 .get_groups_count = bcm2835_pctl_get_groups_count, 813 .get_group_name = bcm2835_pctl_get_group_name, 814 .get_group_pins = bcm2835_pctl_get_group_pins, 815 .pin_dbg_show = bcm2835_pctl_pin_dbg_show, 816 .dt_node_to_map = bcm2835_pctl_dt_node_to_map, 817 .dt_free_map = bcm2835_pctl_dt_free_map, 818 }; 819 820 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) 821 { 822 return BCM2835_FSEL_COUNT; 823 } 824 825 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, 826 unsigned selector) 827 { 828 return bcm2835_functions[selector]; 829 } 830 831 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, 832 unsigned selector, 833 const char * const **groups, 834 unsigned * const num_groups) 835 { 836 /* every pin can do every function */ 837 *groups = bcm2835_gpio_groups; 838 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups); 839 840 return 0; 841 } 842 843 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, 844 unsigned func_selector, 845 unsigned group_selector) 846 { 847 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 848 849 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); 850 851 return 0; 852 } 853 854 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 855 struct pinctrl_gpio_range *range, 856 unsigned offset) 857 { 858 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 859 860 /* disable by setting to GPIO_IN */ 861 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 862 } 863 864 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 865 struct pinctrl_gpio_range *range, 866 unsigned offset, 867 bool input) 868 { 869 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 870 enum bcm2835_fsel fsel = input ? 871 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; 872 873 bcm2835_pinctrl_fsel_set(pc, offset, fsel); 874 875 return 0; 876 } 877 878 static const struct pinmux_ops bcm2835_pmx_ops = { 879 .get_functions_count = bcm2835_pmx_get_functions_count, 880 .get_function_name = bcm2835_pmx_get_function_name, 881 .get_function_groups = bcm2835_pmx_get_function_groups, 882 .set_mux = bcm2835_pmx_set, 883 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 884 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 885 }; 886 887 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 888 unsigned pin, unsigned long *config) 889 { 890 /* No way to read back config in HW */ 891 return -ENOTSUPP; 892 } 893 894 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, 895 unsigned pin, unsigned long *configs, 896 unsigned num_configs) 897 { 898 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 899 enum bcm2835_pinconf_param param; 900 u16 arg; 901 u32 off, bit; 902 int i; 903 904 for (i = 0; i < num_configs; i++) { 905 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]); 906 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]); 907 908 if (param != BCM2835_PINCONF_PARAM_PULL) 909 return -EINVAL; 910 911 off = GPIO_REG_OFFSET(pin); 912 bit = GPIO_REG_SHIFT(pin); 913 914 bcm2835_gpio_wr(pc, GPPUD, arg & 3); 915 /* 916 * Docs say to wait 150 cycles, but not of what. We assume a 917 * 1 MHz clock here, which is pretty slow... 918 */ 919 udelay(150); 920 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); 921 udelay(150); 922 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); 923 } /* for each config */ 924 925 return 0; 926 } 927 928 static const struct pinconf_ops bcm2835_pinconf_ops = { 929 .pin_config_get = bcm2835_pinconf_get, 930 .pin_config_set = bcm2835_pinconf_set, 931 }; 932 933 static struct pinctrl_desc bcm2835_pinctrl_desc = { 934 .name = MODULE_NAME, 935 .pins = bcm2835_gpio_pins, 936 .npins = ARRAY_SIZE(bcm2835_gpio_pins), 937 .pctlops = &bcm2835_pctl_ops, 938 .pmxops = &bcm2835_pmx_ops, 939 .confops = &bcm2835_pinconf_ops, 940 .owner = THIS_MODULE, 941 }; 942 943 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { 944 .name = MODULE_NAME, 945 .npins = BCM2835_NUM_GPIOS, 946 }; 947 948 static int bcm2835_pinctrl_probe(struct platform_device *pdev) 949 { 950 struct device *dev = &pdev->dev; 951 struct device_node *np = dev->of_node; 952 struct bcm2835_pinctrl *pc; 953 struct resource iomem; 954 int err, i; 955 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS); 956 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS); 957 958 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 959 if (!pc) 960 return -ENOMEM; 961 962 platform_set_drvdata(pdev, pc); 963 pc->dev = dev; 964 965 err = of_address_to_resource(np, 0, &iomem); 966 if (err) { 967 dev_err(dev, "could not get IO memory\n"); 968 return err; 969 } 970 971 pc->base = devm_ioremap_resource(dev, &iomem); 972 if (IS_ERR(pc->base)) 973 return PTR_ERR(pc->base); 974 975 pc->gpio_chip = bcm2835_gpio_chip; 976 pc->gpio_chip.dev = dev; 977 pc->gpio_chip.of_node = np; 978 979 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS, 980 &irq_domain_simple_ops, NULL); 981 if (!pc->irq_domain) { 982 dev_err(dev, "could not create IRQ domain\n"); 983 return -ENOMEM; 984 } 985 986 for (i = 0; i < BCM2835_NUM_GPIOS; i++) { 987 int irq = irq_create_mapping(pc->irq_domain, i); 988 irq_set_lockdep_class(irq, &gpio_lock_class); 989 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip, 990 handle_level_irq); 991 irq_set_chip_data(irq, pc); 992 } 993 994 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 995 unsigned long events; 996 unsigned offset; 997 int len; 998 char *name; 999 1000 /* clear event detection flags */ 1001 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); 1002 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); 1003 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); 1004 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); 1005 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); 1006 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); 1007 1008 /* clear all the events */ 1009 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); 1010 for_each_set_bit(offset, &events, 32) 1011 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); 1012 1013 pc->irq[i] = irq_of_parse_and_map(np, i); 1014 pc->irq_data[i].pc = pc; 1015 pc->irq_data[i].bank = i; 1016 spin_lock_init(&pc->irq_lock[i]); 1017 1018 len = strlen(dev_name(pc->dev)) + 16; 1019 name = devm_kzalloc(pc->dev, len, GFP_KERNEL); 1020 if (!name) 1021 return -ENOMEM; 1022 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); 1023 1024 err = devm_request_irq(dev, pc->irq[i], 1025 bcm2835_gpio_irq_handler, IRQF_SHARED, 1026 name, &pc->irq_data[i]); 1027 if (err) { 1028 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]); 1029 return err; 1030 } 1031 } 1032 1033 err = gpiochip_add(&pc->gpio_chip); 1034 if (err) { 1035 dev_err(dev, "could not add GPIO chip\n"); 1036 return err; 1037 } 1038 1039 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc); 1040 if (IS_ERR(pc->pctl_dev)) { 1041 gpiochip_remove(&pc->gpio_chip); 1042 return PTR_ERR(pc->pctl_dev); 1043 } 1044 1045 pc->gpio_range = bcm2835_pinctrl_gpio_range; 1046 pc->gpio_range.base = pc->gpio_chip.base; 1047 pc->gpio_range.gc = &pc->gpio_chip; 1048 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); 1049 1050 return 0; 1051 } 1052 1053 static int bcm2835_pinctrl_remove(struct platform_device *pdev) 1054 { 1055 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev); 1056 1057 pinctrl_unregister(pc->pctl_dev); 1058 gpiochip_remove(&pc->gpio_chip); 1059 1060 return 0; 1061 } 1062 1063 static const struct of_device_id bcm2835_pinctrl_match[] = { 1064 { .compatible = "brcm,bcm2835-gpio" }, 1065 {} 1066 }; 1067 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match); 1068 1069 static struct platform_driver bcm2835_pinctrl_driver = { 1070 .probe = bcm2835_pinctrl_probe, 1071 .remove = bcm2835_pinctrl_remove, 1072 .driver = { 1073 .name = MODULE_NAME, 1074 .of_match_table = bcm2835_pinctrl_match, 1075 }, 1076 }; 1077 module_platform_driver(bcm2835_pinctrl_driver); 1078 1079 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren"); 1080 MODULE_DESCRIPTION("BCM2835 Pin control driver"); 1081 MODULE_LICENSE("GPL"); 1082