1 /* 2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) 3 * 4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 5 * 6 * This driver is inspired by: 7 * pinctrl-nomadik.c, please see original file for copyright information 8 * pinctrl-tegra.c, please see original file for copyright information 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/bitmap.h> 22 #include <linux/bug.h> 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/err.h> 26 #include <linux/gpio/driver.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/irqdesc.h> 30 #include <linux/init.h> 31 #include <linux/of_address.h> 32 #include <linux/of.h> 33 #include <linux/of_irq.h> 34 #include <linux/pinctrl/consumer.h> 35 #include <linux/pinctrl/machine.h> 36 #include <linux/pinctrl/pinconf.h> 37 #include <linux/pinctrl/pinctrl.h> 38 #include <linux/pinctrl/pinmux.h> 39 #include <linux/platform_device.h> 40 #include <linux/seq_file.h> 41 #include <linux/slab.h> 42 #include <linux/spinlock.h> 43 #include <linux/types.h> 44 45 #define MODULE_NAME "pinctrl-bcm2835" 46 #define BCM2835_NUM_GPIOS 54 47 #define BCM2835_NUM_BANKS 2 48 #define BCM2835_NUM_IRQS 3 49 50 #define BCM2835_PIN_BITMAP_SZ \ 51 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8) 52 53 /* GPIO register offsets */ 54 #define GPFSEL0 0x0 /* Function Select */ 55 #define GPSET0 0x1c /* Pin Output Set */ 56 #define GPCLR0 0x28 /* Pin Output Clear */ 57 #define GPLEV0 0x34 /* Pin Level */ 58 #define GPEDS0 0x40 /* Pin Event Detect Status */ 59 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ 60 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ 61 #define GPHEN0 0x64 /* Pin High Detect Enable */ 62 #define GPLEN0 0x70 /* Pin Low Detect Enable */ 63 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ 64 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ 65 #define GPPUD 0x94 /* Pin Pull-up/down Enable */ 66 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ 67 68 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) 69 #define FSEL_SHIFT(p) (((p) % 10) * 3) 70 #define GPIO_REG_OFFSET(p) ((p) / 32) 71 #define GPIO_REG_SHIFT(p) ((p) % 32) 72 73 enum bcm2835_pinconf_param { 74 /* argument: bcm2835_pinconf_pull */ 75 BCM2835_PINCONF_PARAM_PULL, 76 }; 77 78 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 79 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 80 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 81 82 struct bcm2835_pinctrl { 83 struct device *dev; 84 void __iomem *base; 85 int irq[BCM2835_NUM_IRQS]; 86 87 /* note: locking assumes each bank will have its own unsigned long */ 88 unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; 89 unsigned int irq_type[BCM2835_NUM_GPIOS]; 90 91 struct pinctrl_dev *pctl_dev; 92 struct gpio_chip gpio_chip; 93 struct pinctrl_gpio_range gpio_range; 94 95 spinlock_t irq_lock[BCM2835_NUM_BANKS]; 96 }; 97 98 /* pins are just named GPIO0..GPIO53 */ 99 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 100 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 101 BCM2835_GPIO_PIN(0), 102 BCM2835_GPIO_PIN(1), 103 BCM2835_GPIO_PIN(2), 104 BCM2835_GPIO_PIN(3), 105 BCM2835_GPIO_PIN(4), 106 BCM2835_GPIO_PIN(5), 107 BCM2835_GPIO_PIN(6), 108 BCM2835_GPIO_PIN(7), 109 BCM2835_GPIO_PIN(8), 110 BCM2835_GPIO_PIN(9), 111 BCM2835_GPIO_PIN(10), 112 BCM2835_GPIO_PIN(11), 113 BCM2835_GPIO_PIN(12), 114 BCM2835_GPIO_PIN(13), 115 BCM2835_GPIO_PIN(14), 116 BCM2835_GPIO_PIN(15), 117 BCM2835_GPIO_PIN(16), 118 BCM2835_GPIO_PIN(17), 119 BCM2835_GPIO_PIN(18), 120 BCM2835_GPIO_PIN(19), 121 BCM2835_GPIO_PIN(20), 122 BCM2835_GPIO_PIN(21), 123 BCM2835_GPIO_PIN(22), 124 BCM2835_GPIO_PIN(23), 125 BCM2835_GPIO_PIN(24), 126 BCM2835_GPIO_PIN(25), 127 BCM2835_GPIO_PIN(26), 128 BCM2835_GPIO_PIN(27), 129 BCM2835_GPIO_PIN(28), 130 BCM2835_GPIO_PIN(29), 131 BCM2835_GPIO_PIN(30), 132 BCM2835_GPIO_PIN(31), 133 BCM2835_GPIO_PIN(32), 134 BCM2835_GPIO_PIN(33), 135 BCM2835_GPIO_PIN(34), 136 BCM2835_GPIO_PIN(35), 137 BCM2835_GPIO_PIN(36), 138 BCM2835_GPIO_PIN(37), 139 BCM2835_GPIO_PIN(38), 140 BCM2835_GPIO_PIN(39), 141 BCM2835_GPIO_PIN(40), 142 BCM2835_GPIO_PIN(41), 143 BCM2835_GPIO_PIN(42), 144 BCM2835_GPIO_PIN(43), 145 BCM2835_GPIO_PIN(44), 146 BCM2835_GPIO_PIN(45), 147 BCM2835_GPIO_PIN(46), 148 BCM2835_GPIO_PIN(47), 149 BCM2835_GPIO_PIN(48), 150 BCM2835_GPIO_PIN(49), 151 BCM2835_GPIO_PIN(50), 152 BCM2835_GPIO_PIN(51), 153 BCM2835_GPIO_PIN(52), 154 BCM2835_GPIO_PIN(53), 155 }; 156 157 /* one pin per group */ 158 static const char * const bcm2835_gpio_groups[] = { 159 "gpio0", 160 "gpio1", 161 "gpio2", 162 "gpio3", 163 "gpio4", 164 "gpio5", 165 "gpio6", 166 "gpio7", 167 "gpio8", 168 "gpio9", 169 "gpio10", 170 "gpio11", 171 "gpio12", 172 "gpio13", 173 "gpio14", 174 "gpio15", 175 "gpio16", 176 "gpio17", 177 "gpio18", 178 "gpio19", 179 "gpio20", 180 "gpio21", 181 "gpio22", 182 "gpio23", 183 "gpio24", 184 "gpio25", 185 "gpio26", 186 "gpio27", 187 "gpio28", 188 "gpio29", 189 "gpio30", 190 "gpio31", 191 "gpio32", 192 "gpio33", 193 "gpio34", 194 "gpio35", 195 "gpio36", 196 "gpio37", 197 "gpio38", 198 "gpio39", 199 "gpio40", 200 "gpio41", 201 "gpio42", 202 "gpio43", 203 "gpio44", 204 "gpio45", 205 "gpio46", 206 "gpio47", 207 "gpio48", 208 "gpio49", 209 "gpio50", 210 "gpio51", 211 "gpio52", 212 "gpio53", 213 }; 214 215 enum bcm2835_fsel { 216 BCM2835_FSEL_GPIO_IN = 0, 217 BCM2835_FSEL_GPIO_OUT = 1, 218 BCM2835_FSEL_ALT0 = 4, 219 BCM2835_FSEL_ALT1 = 5, 220 BCM2835_FSEL_ALT2 = 6, 221 BCM2835_FSEL_ALT3 = 7, 222 BCM2835_FSEL_ALT4 = 3, 223 BCM2835_FSEL_ALT5 = 2, 224 BCM2835_FSEL_COUNT = 8, 225 BCM2835_FSEL_MASK = 0x7, 226 }; 227 228 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { 229 [BCM2835_FSEL_GPIO_IN] = "gpio_in", 230 [BCM2835_FSEL_GPIO_OUT] = "gpio_out", 231 [BCM2835_FSEL_ALT0] = "alt0", 232 [BCM2835_FSEL_ALT1] = "alt1", 233 [BCM2835_FSEL_ALT2] = "alt2", 234 [BCM2835_FSEL_ALT3] = "alt3", 235 [BCM2835_FSEL_ALT4] = "alt4", 236 [BCM2835_FSEL_ALT5] = "alt5", 237 }; 238 239 static const char * const irq_type_names[] = { 240 [IRQ_TYPE_NONE] = "none", 241 [IRQ_TYPE_EDGE_RISING] = "edge-rising", 242 [IRQ_TYPE_EDGE_FALLING] = "edge-falling", 243 [IRQ_TYPE_EDGE_BOTH] = "edge-both", 244 [IRQ_TYPE_LEVEL_HIGH] = "level-high", 245 [IRQ_TYPE_LEVEL_LOW] = "level-low", 246 }; 247 248 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 249 { 250 return readl(pc->base + reg); 251 } 252 253 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, 254 u32 val) 255 { 256 writel(val, pc->base + reg); 257 } 258 259 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, 260 unsigned bit) 261 { 262 reg += GPIO_REG_OFFSET(bit) * 4; 263 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; 264 } 265 266 /* note NOT a read/modify/write cycle */ 267 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, 268 unsigned reg, unsigned bit) 269 { 270 reg += GPIO_REG_OFFSET(bit) * 4; 271 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); 272 } 273 274 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( 275 struct bcm2835_pinctrl *pc, unsigned pin) 276 { 277 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 278 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 279 280 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, 281 bcm2835_functions[status]); 282 283 return status; 284 } 285 286 static inline void bcm2835_pinctrl_fsel_set( 287 struct bcm2835_pinctrl *pc, unsigned pin, 288 enum bcm2835_fsel fsel) 289 { 290 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 291 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 292 293 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, 294 bcm2835_functions[cur]); 295 296 if (cur == fsel) 297 return; 298 299 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { 300 /* always transition through GPIO_IN */ 301 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 302 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); 303 304 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, 305 bcm2835_functions[BCM2835_FSEL_GPIO_IN]); 306 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 307 } 308 309 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 310 val |= fsel << FSEL_SHIFT(pin); 311 312 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, 313 bcm2835_functions[fsel]); 314 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 315 } 316 317 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 318 { 319 return pinctrl_gpio_direction_input(chip->base + offset); 320 } 321 322 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) 323 { 324 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 325 326 return bcm2835_gpio_get_bit(pc, GPLEV0, offset); 327 } 328 329 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 330 { 331 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 332 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 333 334 /* Alternative function doesn't clearly provide a direction */ 335 if (fsel > BCM2835_FSEL_GPIO_OUT) 336 return -EINVAL; 337 338 return (fsel == BCM2835_FSEL_GPIO_IN); 339 } 340 341 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 342 { 343 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 344 345 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 346 } 347 348 static int bcm2835_gpio_direction_output(struct gpio_chip *chip, 349 unsigned offset, int value) 350 { 351 bcm2835_gpio_set(chip, offset, value); 352 return pinctrl_gpio_direction_output(chip->base + offset); 353 } 354 355 static const struct gpio_chip bcm2835_gpio_chip = { 356 .label = MODULE_NAME, 357 .owner = THIS_MODULE, 358 .request = gpiochip_generic_request, 359 .free = gpiochip_generic_free, 360 .direction_input = bcm2835_gpio_direction_input, 361 .direction_output = bcm2835_gpio_direction_output, 362 .get_direction = bcm2835_gpio_get_direction, 363 .get = bcm2835_gpio_get, 364 .set = bcm2835_gpio_set, 365 .base = -1, 366 .ngpio = BCM2835_NUM_GPIOS, 367 .can_sleep = false, 368 }; 369 370 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, 371 unsigned int bank, u32 mask) 372 { 373 unsigned long events; 374 unsigned offset; 375 unsigned gpio; 376 377 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); 378 events &= mask; 379 events &= pc->enabled_irq_map[bank]; 380 for_each_set_bit(offset, &events, 32) { 381 gpio = (32 * bank) + offset; 382 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain, 383 gpio)); 384 } 385 } 386 387 static void bcm2835_gpio_irq_handler(struct irq_desc *desc) 388 { 389 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 390 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 391 struct irq_chip *host_chip = irq_desc_get_chip(desc); 392 int irq = irq_desc_get_irq(desc); 393 int group; 394 int i; 395 396 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) { 397 if (pc->irq[i] == irq) { 398 group = i; 399 break; 400 } 401 } 402 /* This should not happen, every IRQ has a bank */ 403 if (i == ARRAY_SIZE(pc->irq)) 404 BUG(); 405 406 chained_irq_enter(host_chip, desc); 407 408 switch (group) { 409 case 0: /* IRQ0 covers GPIOs 0-27 */ 410 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); 411 break; 412 case 1: /* IRQ1 covers GPIOs 28-45 */ 413 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000); 414 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); 415 break; 416 case 2: /* IRQ2 covers GPIOs 46-53 */ 417 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); 418 break; 419 } 420 421 chained_irq_exit(host_chip, desc); 422 } 423 424 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 425 unsigned reg, unsigned offset, bool enable) 426 { 427 u32 value; 428 reg += GPIO_REG_OFFSET(offset) * 4; 429 value = bcm2835_gpio_rd(pc, reg); 430 if (enable) 431 value |= BIT(GPIO_REG_SHIFT(offset)); 432 else 433 value &= ~(BIT(GPIO_REG_SHIFT(offset))); 434 bcm2835_gpio_wr(pc, reg, value); 435 } 436 437 /* fast path for IRQ handler */ 438 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 439 unsigned offset, bool enable) 440 { 441 switch (pc->irq_type[offset]) { 442 case IRQ_TYPE_EDGE_RISING: 443 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 444 break; 445 446 case IRQ_TYPE_EDGE_FALLING: 447 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 448 break; 449 450 case IRQ_TYPE_EDGE_BOTH: 451 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 452 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 453 break; 454 455 case IRQ_TYPE_LEVEL_HIGH: 456 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); 457 break; 458 459 case IRQ_TYPE_LEVEL_LOW: 460 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); 461 break; 462 } 463 } 464 465 static void bcm2835_gpio_irq_enable(struct irq_data *data) 466 { 467 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 468 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 469 unsigned gpio = irqd_to_hwirq(data); 470 unsigned offset = GPIO_REG_SHIFT(gpio); 471 unsigned bank = GPIO_REG_OFFSET(gpio); 472 unsigned long flags; 473 474 spin_lock_irqsave(&pc->irq_lock[bank], flags); 475 set_bit(offset, &pc->enabled_irq_map[bank]); 476 bcm2835_gpio_irq_config(pc, gpio, true); 477 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 478 } 479 480 static void bcm2835_gpio_irq_disable(struct irq_data *data) 481 { 482 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 483 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 484 unsigned gpio = irqd_to_hwirq(data); 485 unsigned offset = GPIO_REG_SHIFT(gpio); 486 unsigned bank = GPIO_REG_OFFSET(gpio); 487 unsigned long flags; 488 489 spin_lock_irqsave(&pc->irq_lock[bank], flags); 490 bcm2835_gpio_irq_config(pc, gpio, false); 491 /* Clear events that were latched prior to clearing event sources */ 492 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 493 clear_bit(offset, &pc->enabled_irq_map[bank]); 494 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 495 } 496 497 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, 498 unsigned offset, unsigned int type) 499 { 500 switch (type) { 501 case IRQ_TYPE_NONE: 502 case IRQ_TYPE_EDGE_RISING: 503 case IRQ_TYPE_EDGE_FALLING: 504 case IRQ_TYPE_EDGE_BOTH: 505 case IRQ_TYPE_LEVEL_HIGH: 506 case IRQ_TYPE_LEVEL_LOW: 507 pc->irq_type[offset] = type; 508 break; 509 510 default: 511 return -EINVAL; 512 } 513 return 0; 514 } 515 516 /* slower path for reconfiguring IRQ type */ 517 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, 518 unsigned offset, unsigned int type) 519 { 520 switch (type) { 521 case IRQ_TYPE_NONE: 522 if (pc->irq_type[offset] != type) { 523 bcm2835_gpio_irq_config(pc, offset, false); 524 pc->irq_type[offset] = type; 525 } 526 break; 527 528 case IRQ_TYPE_EDGE_RISING: 529 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 530 /* RISING already enabled, disable FALLING */ 531 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 532 bcm2835_gpio_irq_config(pc, offset, false); 533 pc->irq_type[offset] = type; 534 } else if (pc->irq_type[offset] != type) { 535 bcm2835_gpio_irq_config(pc, offset, false); 536 pc->irq_type[offset] = type; 537 bcm2835_gpio_irq_config(pc, offset, true); 538 } 539 break; 540 541 case IRQ_TYPE_EDGE_FALLING: 542 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 543 /* FALLING already enabled, disable RISING */ 544 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 545 bcm2835_gpio_irq_config(pc, offset, false); 546 pc->irq_type[offset] = type; 547 } else if (pc->irq_type[offset] != type) { 548 bcm2835_gpio_irq_config(pc, offset, false); 549 pc->irq_type[offset] = type; 550 bcm2835_gpio_irq_config(pc, offset, true); 551 } 552 break; 553 554 case IRQ_TYPE_EDGE_BOTH: 555 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { 556 /* RISING already enabled, enable FALLING too */ 557 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 558 bcm2835_gpio_irq_config(pc, offset, true); 559 pc->irq_type[offset] = type; 560 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { 561 /* FALLING already enabled, enable RISING too */ 562 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 563 bcm2835_gpio_irq_config(pc, offset, true); 564 pc->irq_type[offset] = type; 565 } else if (pc->irq_type[offset] != type) { 566 bcm2835_gpio_irq_config(pc, offset, false); 567 pc->irq_type[offset] = type; 568 bcm2835_gpio_irq_config(pc, offset, true); 569 } 570 break; 571 572 case IRQ_TYPE_LEVEL_HIGH: 573 case IRQ_TYPE_LEVEL_LOW: 574 if (pc->irq_type[offset] != type) { 575 bcm2835_gpio_irq_config(pc, offset, false); 576 pc->irq_type[offset] = type; 577 bcm2835_gpio_irq_config(pc, offset, true); 578 } 579 break; 580 581 default: 582 return -EINVAL; 583 } 584 return 0; 585 } 586 587 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) 588 { 589 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 590 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 591 unsigned gpio = irqd_to_hwirq(data); 592 unsigned offset = GPIO_REG_SHIFT(gpio); 593 unsigned bank = GPIO_REG_OFFSET(gpio); 594 unsigned long flags; 595 int ret; 596 597 spin_lock_irqsave(&pc->irq_lock[bank], flags); 598 599 if (test_bit(offset, &pc->enabled_irq_map[bank])) 600 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); 601 else 602 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 603 604 if (type & IRQ_TYPE_EDGE_BOTH) 605 irq_set_handler_locked(data, handle_edge_irq); 606 else 607 irq_set_handler_locked(data, handle_level_irq); 608 609 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 610 611 return ret; 612 } 613 614 static void bcm2835_gpio_irq_ack(struct irq_data *data) 615 { 616 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 617 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 618 unsigned gpio = irqd_to_hwirq(data); 619 620 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 621 } 622 623 static struct irq_chip bcm2835_gpio_irq_chip = { 624 .name = MODULE_NAME, 625 .irq_enable = bcm2835_gpio_irq_enable, 626 .irq_disable = bcm2835_gpio_irq_disable, 627 .irq_set_type = bcm2835_gpio_irq_set_type, 628 .irq_ack = bcm2835_gpio_irq_ack, 629 .irq_mask = bcm2835_gpio_irq_disable, 630 .irq_unmask = bcm2835_gpio_irq_enable, 631 }; 632 633 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 634 { 635 return ARRAY_SIZE(bcm2835_gpio_groups); 636 } 637 638 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, 639 unsigned selector) 640 { 641 return bcm2835_gpio_groups[selector]; 642 } 643 644 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, 645 unsigned selector, 646 const unsigned **pins, 647 unsigned *num_pins) 648 { 649 *pins = &bcm2835_gpio_pins[selector].number; 650 *num_pins = 1; 651 652 return 0; 653 } 654 655 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 656 struct seq_file *s, 657 unsigned offset) 658 { 659 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 660 struct gpio_chip *chip = &pc->gpio_chip; 661 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 662 const char *fname = bcm2835_functions[fsel]; 663 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); 664 int irq = irq_find_mapping(chip->irq.domain, offset); 665 666 seq_printf(s, "function %s in %s; irq %d (%s)", 667 fname, value ? "hi" : "lo", 668 irq, irq_type_names[pc->irq_type[offset]]); 669 } 670 671 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, 672 struct pinctrl_map *maps, unsigned num_maps) 673 { 674 int i; 675 676 for (i = 0; i < num_maps; i++) 677 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 678 kfree(maps[i].data.configs.configs); 679 680 kfree(maps); 681 } 682 683 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, 684 struct device_node *np, u32 pin, u32 fnum, 685 struct pinctrl_map **maps) 686 { 687 struct pinctrl_map *map = *maps; 688 689 if (fnum >= ARRAY_SIZE(bcm2835_functions)) { 690 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); 691 return -EINVAL; 692 } 693 694 map->type = PIN_MAP_TYPE_MUX_GROUP; 695 map->data.mux.group = bcm2835_gpio_groups[pin]; 696 map->data.mux.function = bcm2835_functions[fnum]; 697 (*maps)++; 698 699 return 0; 700 } 701 702 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, 703 struct device_node *np, u32 pin, u32 pull, 704 struct pinctrl_map **maps) 705 { 706 struct pinctrl_map *map = *maps; 707 unsigned long *configs; 708 709 if (pull > 2) { 710 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); 711 return -EINVAL; 712 } 713 714 configs = kzalloc(sizeof(*configs), GFP_KERNEL); 715 if (!configs) 716 return -ENOMEM; 717 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull); 718 719 map->type = PIN_MAP_TYPE_CONFIGS_PIN; 720 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; 721 map->data.configs.configs = configs; 722 map->data.configs.num_configs = 1; 723 (*maps)++; 724 725 return 0; 726 } 727 728 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 729 struct device_node *np, 730 struct pinctrl_map **map, unsigned *num_maps) 731 { 732 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 733 struct property *pins, *funcs, *pulls; 734 int num_pins, num_funcs, num_pulls, maps_per_pin; 735 struct pinctrl_map *maps, *cur_map; 736 int i, err; 737 u32 pin, func, pull; 738 739 pins = of_find_property(np, "brcm,pins", NULL); 740 if (!pins) { 741 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np); 742 return -EINVAL; 743 } 744 745 funcs = of_find_property(np, "brcm,function", NULL); 746 pulls = of_find_property(np, "brcm,pull", NULL); 747 748 if (!funcs && !pulls) { 749 dev_err(pc->dev, 750 "%pOF: neither brcm,function nor brcm,pull specified\n", 751 np); 752 return -EINVAL; 753 } 754 755 num_pins = pins->length / 4; 756 num_funcs = funcs ? (funcs->length / 4) : 0; 757 num_pulls = pulls ? (pulls->length / 4) : 0; 758 759 if (num_funcs > 1 && num_funcs != num_pins) { 760 dev_err(pc->dev, 761 "%pOF: brcm,function must have 1 or %d entries\n", 762 np, num_pins); 763 return -EINVAL; 764 } 765 766 if (num_pulls > 1 && num_pulls != num_pins) { 767 dev_err(pc->dev, 768 "%pOF: brcm,pull must have 1 or %d entries\n", 769 np, num_pins); 770 return -EINVAL; 771 } 772 773 maps_per_pin = 0; 774 if (num_funcs) 775 maps_per_pin++; 776 if (num_pulls) 777 maps_per_pin++; 778 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps), 779 GFP_KERNEL); 780 if (!maps) 781 return -ENOMEM; 782 783 for (i = 0; i < num_pins; i++) { 784 err = of_property_read_u32_index(np, "brcm,pins", i, &pin); 785 if (err) 786 goto out; 787 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) { 788 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", 789 np, pin); 790 err = -EINVAL; 791 goto out; 792 } 793 794 if (num_funcs) { 795 err = of_property_read_u32_index(np, "brcm,function", 796 (num_funcs > 1) ? i : 0, &func); 797 if (err) 798 goto out; 799 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 800 func, &cur_map); 801 if (err) 802 goto out; 803 } 804 if (num_pulls) { 805 err = of_property_read_u32_index(np, "brcm,pull", 806 (num_pulls > 1) ? i : 0, &pull); 807 if (err) 808 goto out; 809 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 810 pull, &cur_map); 811 if (err) 812 goto out; 813 } 814 } 815 816 *map = maps; 817 *num_maps = num_pins * maps_per_pin; 818 819 return 0; 820 821 out: 822 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); 823 return err; 824 } 825 826 static const struct pinctrl_ops bcm2835_pctl_ops = { 827 .get_groups_count = bcm2835_pctl_get_groups_count, 828 .get_group_name = bcm2835_pctl_get_group_name, 829 .get_group_pins = bcm2835_pctl_get_group_pins, 830 .pin_dbg_show = bcm2835_pctl_pin_dbg_show, 831 .dt_node_to_map = bcm2835_pctl_dt_node_to_map, 832 .dt_free_map = bcm2835_pctl_dt_free_map, 833 }; 834 835 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, 836 unsigned offset) 837 { 838 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 839 840 /* disable by setting to GPIO_IN */ 841 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 842 return 0; 843 } 844 845 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) 846 { 847 return BCM2835_FSEL_COUNT; 848 } 849 850 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, 851 unsigned selector) 852 { 853 return bcm2835_functions[selector]; 854 } 855 856 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, 857 unsigned selector, 858 const char * const **groups, 859 unsigned * const num_groups) 860 { 861 /* every pin can do every function */ 862 *groups = bcm2835_gpio_groups; 863 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups); 864 865 return 0; 866 } 867 868 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, 869 unsigned func_selector, 870 unsigned group_selector) 871 { 872 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 873 874 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); 875 876 return 0; 877 } 878 879 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 880 struct pinctrl_gpio_range *range, 881 unsigned offset) 882 { 883 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 884 885 /* disable by setting to GPIO_IN */ 886 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 887 } 888 889 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 890 struct pinctrl_gpio_range *range, 891 unsigned offset, 892 bool input) 893 { 894 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 895 enum bcm2835_fsel fsel = input ? 896 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; 897 898 bcm2835_pinctrl_fsel_set(pc, offset, fsel); 899 900 return 0; 901 } 902 903 static const struct pinmux_ops bcm2835_pmx_ops = { 904 .free = bcm2835_pmx_free, 905 .get_functions_count = bcm2835_pmx_get_functions_count, 906 .get_function_name = bcm2835_pmx_get_function_name, 907 .get_function_groups = bcm2835_pmx_get_function_groups, 908 .set_mux = bcm2835_pmx_set, 909 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 910 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 911 }; 912 913 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 914 unsigned pin, unsigned long *config) 915 { 916 /* No way to read back config in HW */ 917 return -ENOTSUPP; 918 } 919 920 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, 921 unsigned pin, unsigned long *configs, 922 unsigned num_configs) 923 { 924 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 925 enum bcm2835_pinconf_param param; 926 u16 arg; 927 u32 off, bit; 928 int i; 929 930 for (i = 0; i < num_configs; i++) { 931 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]); 932 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]); 933 934 if (param != BCM2835_PINCONF_PARAM_PULL) 935 return -EINVAL; 936 937 off = GPIO_REG_OFFSET(pin); 938 bit = GPIO_REG_SHIFT(pin); 939 940 bcm2835_gpio_wr(pc, GPPUD, arg & 3); 941 /* 942 * BCM2835 datasheet say to wait 150 cycles, but not of what. 943 * But the VideoCore firmware delay for this operation 944 * based nearly on the same amount of VPU cycles and this clock 945 * runs at 250 MHz. 946 */ 947 udelay(1); 948 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); 949 udelay(1); 950 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); 951 } /* for each config */ 952 953 return 0; 954 } 955 956 static const struct pinconf_ops bcm2835_pinconf_ops = { 957 .pin_config_get = bcm2835_pinconf_get, 958 .pin_config_set = bcm2835_pinconf_set, 959 }; 960 961 static struct pinctrl_desc bcm2835_pinctrl_desc = { 962 .name = MODULE_NAME, 963 .pins = bcm2835_gpio_pins, 964 .npins = ARRAY_SIZE(bcm2835_gpio_pins), 965 .pctlops = &bcm2835_pctl_ops, 966 .pmxops = &bcm2835_pmx_ops, 967 .confops = &bcm2835_pinconf_ops, 968 .owner = THIS_MODULE, 969 }; 970 971 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { 972 .name = MODULE_NAME, 973 .npins = BCM2835_NUM_GPIOS, 974 }; 975 976 static int bcm2835_pinctrl_probe(struct platform_device *pdev) 977 { 978 struct device *dev = &pdev->dev; 979 struct device_node *np = dev->of_node; 980 struct bcm2835_pinctrl *pc; 981 struct resource iomem; 982 int err, i; 983 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS); 984 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS); 985 986 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 987 if (!pc) 988 return -ENOMEM; 989 990 platform_set_drvdata(pdev, pc); 991 pc->dev = dev; 992 993 err = of_address_to_resource(np, 0, &iomem); 994 if (err) { 995 dev_err(dev, "could not get IO memory\n"); 996 return err; 997 } 998 999 pc->base = devm_ioremap_resource(dev, &iomem); 1000 if (IS_ERR(pc->base)) 1001 return PTR_ERR(pc->base); 1002 1003 pc->gpio_chip = bcm2835_gpio_chip; 1004 pc->gpio_chip.parent = dev; 1005 pc->gpio_chip.of_node = np; 1006 1007 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 1008 unsigned long events; 1009 unsigned offset; 1010 1011 /* clear event detection flags */ 1012 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); 1013 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); 1014 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); 1015 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); 1016 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); 1017 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); 1018 1019 /* clear all the events */ 1020 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); 1021 for_each_set_bit(offset, &events, 32) 1022 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); 1023 1024 spin_lock_init(&pc->irq_lock[i]); 1025 } 1026 1027 err = gpiochip_add_data(&pc->gpio_chip, pc); 1028 if (err) { 1029 dev_err(dev, "could not add GPIO chip\n"); 1030 return err; 1031 } 1032 1033 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip, 1034 0, handle_level_irq, IRQ_TYPE_NONE); 1035 if (err) { 1036 dev_info(dev, "could not add irqchip\n"); 1037 return err; 1038 } 1039 1040 for (i = 0; i < BCM2835_NUM_IRQS; i++) { 1041 pc->irq[i] = irq_of_parse_and_map(np, i); 1042 1043 if (pc->irq[i] == 0) 1044 continue; 1045 1046 /* 1047 * Use the same handler for all groups: this is necessary 1048 * since we use one gpiochip to cover all lines - the 1049 * irq handler then needs to figure out which group and 1050 * bank that was firing the IRQ and look up the per-group 1051 * and bank data. 1052 */ 1053 gpiochip_set_chained_irqchip(&pc->gpio_chip, 1054 &bcm2835_gpio_irq_chip, 1055 pc->irq[i], 1056 bcm2835_gpio_irq_handler); 1057 } 1058 1059 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc); 1060 if (IS_ERR(pc->pctl_dev)) { 1061 gpiochip_remove(&pc->gpio_chip); 1062 return PTR_ERR(pc->pctl_dev); 1063 } 1064 1065 pc->gpio_range = bcm2835_pinctrl_gpio_range; 1066 pc->gpio_range.base = pc->gpio_chip.base; 1067 pc->gpio_range.gc = &pc->gpio_chip; 1068 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); 1069 1070 return 0; 1071 } 1072 1073 static const struct of_device_id bcm2835_pinctrl_match[] = { 1074 { .compatible = "brcm,bcm2835-gpio" }, 1075 {} 1076 }; 1077 1078 static struct platform_driver bcm2835_pinctrl_driver = { 1079 .probe = bcm2835_pinctrl_probe, 1080 .driver = { 1081 .name = MODULE_NAME, 1082 .of_match_table = bcm2835_pinctrl_match, 1083 .suppress_bind_attrs = true, 1084 }, 1085 }; 1086 builtin_platform_driver(bcm2835_pinctrl_driver); 1087