1 /* 2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) 3 * 4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren 5 * 6 * This driver is inspired by: 7 * pinctrl-nomadik.c, please see original file for copyright information 8 * pinctrl-tegra.c, please see original file for copyright information 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/bitmap.h> 22 #include <linux/bug.h> 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/err.h> 26 #include <linux/gpio/driver.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/irq.h> 30 #include <linux/irqdesc.h> 31 #include <linux/irqdomain.h> 32 #include <linux/module.h> 33 #include <linux/of_address.h> 34 #include <linux/of.h> 35 #include <linux/of_irq.h> 36 #include <linux/pinctrl/consumer.h> 37 #include <linux/pinctrl/machine.h> 38 #include <linux/pinctrl/pinconf.h> 39 #include <linux/pinctrl/pinctrl.h> 40 #include <linux/pinctrl/pinmux.h> 41 #include <linux/platform_device.h> 42 #include <linux/seq_file.h> 43 #include <linux/slab.h> 44 #include <linux/spinlock.h> 45 #include <linux/types.h> 46 47 #define MODULE_NAME "pinctrl-bcm2835" 48 #define BCM2835_NUM_GPIOS 54 49 #define BCM2835_NUM_BANKS 2 50 51 #define BCM2835_PIN_BITMAP_SZ \ 52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8) 53 54 /* GPIO register offsets */ 55 #define GPFSEL0 0x0 /* Function Select */ 56 #define GPSET0 0x1c /* Pin Output Set */ 57 #define GPCLR0 0x28 /* Pin Output Clear */ 58 #define GPLEV0 0x34 /* Pin Level */ 59 #define GPEDS0 0x40 /* Pin Event Detect Status */ 60 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ 61 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ 62 #define GPHEN0 0x64 /* Pin High Detect Enable */ 63 #define GPLEN0 0x70 /* Pin Low Detect Enable */ 64 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ 65 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ 66 #define GPPUD 0x94 /* Pin Pull-up/down Enable */ 67 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ 68 69 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) 70 #define FSEL_SHIFT(p) (((p) % 10) * 3) 71 #define GPIO_REG_OFFSET(p) ((p) / 32) 72 #define GPIO_REG_SHIFT(p) ((p) % 32) 73 74 enum bcm2835_pinconf_param { 75 /* argument: bcm2835_pinconf_pull */ 76 BCM2835_PINCONF_PARAM_PULL, 77 }; 78 79 enum bcm2835_pinconf_pull { 80 BCM2835_PINCONFIG_PULL_NONE, 81 BCM2835_PINCONFIG_PULL_DOWN, 82 BCM2835_PINCONFIG_PULL_UP, 83 }; 84 85 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) 86 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) 87 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) 88 89 struct bcm2835_gpio_irqdata { 90 struct bcm2835_pinctrl *pc; 91 int bank; 92 }; 93 94 struct bcm2835_pinctrl { 95 struct device *dev; 96 void __iomem *base; 97 int irq[BCM2835_NUM_BANKS]; 98 99 /* note: locking assumes each bank will have its own unsigned long */ 100 unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; 101 unsigned int irq_type[BCM2835_NUM_GPIOS]; 102 103 struct pinctrl_dev *pctl_dev; 104 struct irq_domain *irq_domain; 105 struct gpio_chip gpio_chip; 106 struct pinctrl_gpio_range gpio_range; 107 108 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS]; 109 spinlock_t irq_lock[BCM2835_NUM_BANKS]; 110 }; 111 112 static struct lock_class_key gpio_lock_class; 113 114 /* pins are just named GPIO0..GPIO53 */ 115 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) 116 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { 117 BCM2835_GPIO_PIN(0), 118 BCM2835_GPIO_PIN(1), 119 BCM2835_GPIO_PIN(2), 120 BCM2835_GPIO_PIN(3), 121 BCM2835_GPIO_PIN(4), 122 BCM2835_GPIO_PIN(5), 123 BCM2835_GPIO_PIN(6), 124 BCM2835_GPIO_PIN(7), 125 BCM2835_GPIO_PIN(8), 126 BCM2835_GPIO_PIN(9), 127 BCM2835_GPIO_PIN(10), 128 BCM2835_GPIO_PIN(11), 129 BCM2835_GPIO_PIN(12), 130 BCM2835_GPIO_PIN(13), 131 BCM2835_GPIO_PIN(14), 132 BCM2835_GPIO_PIN(15), 133 BCM2835_GPIO_PIN(16), 134 BCM2835_GPIO_PIN(17), 135 BCM2835_GPIO_PIN(18), 136 BCM2835_GPIO_PIN(19), 137 BCM2835_GPIO_PIN(20), 138 BCM2835_GPIO_PIN(21), 139 BCM2835_GPIO_PIN(22), 140 BCM2835_GPIO_PIN(23), 141 BCM2835_GPIO_PIN(24), 142 BCM2835_GPIO_PIN(25), 143 BCM2835_GPIO_PIN(26), 144 BCM2835_GPIO_PIN(27), 145 BCM2835_GPIO_PIN(28), 146 BCM2835_GPIO_PIN(29), 147 BCM2835_GPIO_PIN(30), 148 BCM2835_GPIO_PIN(31), 149 BCM2835_GPIO_PIN(32), 150 BCM2835_GPIO_PIN(33), 151 BCM2835_GPIO_PIN(34), 152 BCM2835_GPIO_PIN(35), 153 BCM2835_GPIO_PIN(36), 154 BCM2835_GPIO_PIN(37), 155 BCM2835_GPIO_PIN(38), 156 BCM2835_GPIO_PIN(39), 157 BCM2835_GPIO_PIN(40), 158 BCM2835_GPIO_PIN(41), 159 BCM2835_GPIO_PIN(42), 160 BCM2835_GPIO_PIN(43), 161 BCM2835_GPIO_PIN(44), 162 BCM2835_GPIO_PIN(45), 163 BCM2835_GPIO_PIN(46), 164 BCM2835_GPIO_PIN(47), 165 BCM2835_GPIO_PIN(48), 166 BCM2835_GPIO_PIN(49), 167 BCM2835_GPIO_PIN(50), 168 BCM2835_GPIO_PIN(51), 169 BCM2835_GPIO_PIN(52), 170 BCM2835_GPIO_PIN(53), 171 }; 172 173 /* one pin per group */ 174 static const char * const bcm2835_gpio_groups[] = { 175 "gpio0", 176 "gpio1", 177 "gpio2", 178 "gpio3", 179 "gpio4", 180 "gpio5", 181 "gpio6", 182 "gpio7", 183 "gpio8", 184 "gpio9", 185 "gpio10", 186 "gpio11", 187 "gpio12", 188 "gpio13", 189 "gpio14", 190 "gpio15", 191 "gpio16", 192 "gpio17", 193 "gpio18", 194 "gpio19", 195 "gpio20", 196 "gpio21", 197 "gpio22", 198 "gpio23", 199 "gpio24", 200 "gpio25", 201 "gpio26", 202 "gpio27", 203 "gpio28", 204 "gpio29", 205 "gpio30", 206 "gpio31", 207 "gpio32", 208 "gpio33", 209 "gpio34", 210 "gpio35", 211 "gpio36", 212 "gpio37", 213 "gpio38", 214 "gpio39", 215 "gpio40", 216 "gpio41", 217 "gpio42", 218 "gpio43", 219 "gpio44", 220 "gpio45", 221 "gpio46", 222 "gpio47", 223 "gpio48", 224 "gpio49", 225 "gpio50", 226 "gpio51", 227 "gpio52", 228 "gpio53", 229 }; 230 231 enum bcm2835_fsel { 232 BCM2835_FSEL_GPIO_IN = 0, 233 BCM2835_FSEL_GPIO_OUT = 1, 234 BCM2835_FSEL_ALT0 = 4, 235 BCM2835_FSEL_ALT1 = 5, 236 BCM2835_FSEL_ALT2 = 6, 237 BCM2835_FSEL_ALT3 = 7, 238 BCM2835_FSEL_ALT4 = 3, 239 BCM2835_FSEL_ALT5 = 2, 240 BCM2835_FSEL_COUNT = 8, 241 BCM2835_FSEL_MASK = 0x7, 242 }; 243 244 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { 245 [BCM2835_FSEL_GPIO_IN] = "gpio_in", 246 [BCM2835_FSEL_GPIO_OUT] = "gpio_out", 247 [BCM2835_FSEL_ALT0] = "alt0", 248 [BCM2835_FSEL_ALT1] = "alt1", 249 [BCM2835_FSEL_ALT2] = "alt2", 250 [BCM2835_FSEL_ALT3] = "alt3", 251 [BCM2835_FSEL_ALT4] = "alt4", 252 [BCM2835_FSEL_ALT5] = "alt5", 253 }; 254 255 static const char * const irq_type_names[] = { 256 [IRQ_TYPE_NONE] = "none", 257 [IRQ_TYPE_EDGE_RISING] = "edge-rising", 258 [IRQ_TYPE_EDGE_FALLING] = "edge-falling", 259 [IRQ_TYPE_EDGE_BOTH] = "edge-both", 260 [IRQ_TYPE_LEVEL_HIGH] = "level-high", 261 [IRQ_TYPE_LEVEL_LOW] = "level-low", 262 }; 263 264 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) 265 { 266 return readl(pc->base + reg); 267 } 268 269 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, 270 u32 val) 271 { 272 writel(val, pc->base + reg); 273 } 274 275 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, 276 unsigned bit) 277 { 278 reg += GPIO_REG_OFFSET(bit) * 4; 279 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; 280 } 281 282 /* note NOT a read/modify/write cycle */ 283 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, 284 unsigned reg, unsigned bit) 285 { 286 reg += GPIO_REG_OFFSET(bit) * 4; 287 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); 288 } 289 290 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( 291 struct bcm2835_pinctrl *pc, unsigned pin) 292 { 293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 295 296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, 297 bcm2835_functions[status]); 298 299 return status; 300 } 301 302 static inline void bcm2835_pinctrl_fsel_set( 303 struct bcm2835_pinctrl *pc, unsigned pin, 304 enum bcm2835_fsel fsel) 305 { 306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); 307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; 308 309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, 310 bcm2835_functions[cur]); 311 312 if (cur == fsel) 313 return; 314 315 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { 316 /* always transition through GPIO_IN */ 317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); 319 320 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, 321 bcm2835_functions[BCM2835_FSEL_GPIO_IN]); 322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 323 } 324 325 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); 326 val |= fsel << FSEL_SHIFT(pin); 327 328 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, 329 bcm2835_functions[fsel]); 330 bcm2835_gpio_wr(pc, FSEL_REG(pin), val); 331 } 332 333 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 334 { 335 return pinctrl_gpio_direction_input(chip->base + offset); 336 } 337 338 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) 339 { 340 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 341 342 return bcm2835_gpio_get_bit(pc, GPLEV0, offset); 343 } 344 345 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 346 { 347 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 348 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 349 350 /* Alternative function doesn't clearly provide a direction */ 351 if (fsel > BCM2835_FSEL_GPIO_OUT) 352 return -EINVAL; 353 354 return (fsel == BCM2835_FSEL_GPIO_IN); 355 } 356 357 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 358 { 359 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 360 361 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); 362 } 363 364 static int bcm2835_gpio_direction_output(struct gpio_chip *chip, 365 unsigned offset, int value) 366 { 367 bcm2835_gpio_set(chip, offset, value); 368 return pinctrl_gpio_direction_output(chip->base + offset); 369 } 370 371 static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 372 { 373 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); 374 375 return irq_linear_revmap(pc->irq_domain, offset); 376 } 377 378 static struct gpio_chip bcm2835_gpio_chip = { 379 .label = MODULE_NAME, 380 .owner = THIS_MODULE, 381 .request = gpiochip_generic_request, 382 .free = gpiochip_generic_free, 383 .direction_input = bcm2835_gpio_direction_input, 384 .direction_output = bcm2835_gpio_direction_output, 385 .get_direction = bcm2835_gpio_get_direction, 386 .get = bcm2835_gpio_get, 387 .set = bcm2835_gpio_set, 388 .to_irq = bcm2835_gpio_to_irq, 389 .base = -1, 390 .ngpio = BCM2835_NUM_GPIOS, 391 .can_sleep = false, 392 }; 393 394 static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) 395 { 396 struct bcm2835_gpio_irqdata *irqdata = dev_id; 397 struct bcm2835_pinctrl *pc = irqdata->pc; 398 int bank = irqdata->bank; 399 unsigned long events; 400 unsigned offset; 401 unsigned gpio; 402 unsigned int type; 403 404 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); 405 events &= pc->enabled_irq_map[bank]; 406 for_each_set_bit(offset, &events, 32) { 407 gpio = (32 * bank) + offset; 408 type = pc->irq_type[gpio]; 409 410 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); 411 } 412 return events ? IRQ_HANDLED : IRQ_NONE; 413 } 414 415 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 416 unsigned reg, unsigned offset, bool enable) 417 { 418 u32 value; 419 reg += GPIO_REG_OFFSET(offset) * 4; 420 value = bcm2835_gpio_rd(pc, reg); 421 if (enable) 422 value |= BIT(GPIO_REG_SHIFT(offset)); 423 else 424 value &= ~(BIT(GPIO_REG_SHIFT(offset))); 425 bcm2835_gpio_wr(pc, reg, value); 426 } 427 428 /* fast path for IRQ handler */ 429 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, 430 unsigned offset, bool enable) 431 { 432 switch (pc->irq_type[offset]) { 433 case IRQ_TYPE_EDGE_RISING: 434 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 435 break; 436 437 case IRQ_TYPE_EDGE_FALLING: 438 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 439 break; 440 441 case IRQ_TYPE_EDGE_BOTH: 442 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); 443 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); 444 break; 445 446 case IRQ_TYPE_LEVEL_HIGH: 447 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); 448 break; 449 450 case IRQ_TYPE_LEVEL_LOW: 451 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); 452 break; 453 } 454 } 455 456 static void bcm2835_gpio_irq_enable(struct irq_data *data) 457 { 458 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 459 unsigned gpio = irqd_to_hwirq(data); 460 unsigned offset = GPIO_REG_SHIFT(gpio); 461 unsigned bank = GPIO_REG_OFFSET(gpio); 462 unsigned long flags; 463 464 spin_lock_irqsave(&pc->irq_lock[bank], flags); 465 set_bit(offset, &pc->enabled_irq_map[bank]); 466 bcm2835_gpio_irq_config(pc, gpio, true); 467 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 468 } 469 470 static void bcm2835_gpio_irq_disable(struct irq_data *data) 471 { 472 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 473 unsigned gpio = irqd_to_hwirq(data); 474 unsigned offset = GPIO_REG_SHIFT(gpio); 475 unsigned bank = GPIO_REG_OFFSET(gpio); 476 unsigned long flags; 477 478 spin_lock_irqsave(&pc->irq_lock[bank], flags); 479 bcm2835_gpio_irq_config(pc, gpio, false); 480 /* Clear events that were latched prior to clearing event sources */ 481 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 482 clear_bit(offset, &pc->enabled_irq_map[bank]); 483 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 484 } 485 486 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, 487 unsigned offset, unsigned int type) 488 { 489 switch (type) { 490 case IRQ_TYPE_NONE: 491 case IRQ_TYPE_EDGE_RISING: 492 case IRQ_TYPE_EDGE_FALLING: 493 case IRQ_TYPE_EDGE_BOTH: 494 case IRQ_TYPE_LEVEL_HIGH: 495 case IRQ_TYPE_LEVEL_LOW: 496 pc->irq_type[offset] = type; 497 break; 498 499 default: 500 return -EINVAL; 501 } 502 return 0; 503 } 504 505 /* slower path for reconfiguring IRQ type */ 506 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, 507 unsigned offset, unsigned int type) 508 { 509 switch (type) { 510 case IRQ_TYPE_NONE: 511 if (pc->irq_type[offset] != type) { 512 bcm2835_gpio_irq_config(pc, offset, false); 513 pc->irq_type[offset] = type; 514 } 515 break; 516 517 case IRQ_TYPE_EDGE_RISING: 518 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 519 /* RISING already enabled, disable FALLING */ 520 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 521 bcm2835_gpio_irq_config(pc, offset, false); 522 pc->irq_type[offset] = type; 523 } else if (pc->irq_type[offset] != type) { 524 bcm2835_gpio_irq_config(pc, offset, false); 525 pc->irq_type[offset] = type; 526 bcm2835_gpio_irq_config(pc, offset, true); 527 } 528 break; 529 530 case IRQ_TYPE_EDGE_FALLING: 531 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { 532 /* FALLING already enabled, disable RISING */ 533 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 534 bcm2835_gpio_irq_config(pc, offset, false); 535 pc->irq_type[offset] = type; 536 } else if (pc->irq_type[offset] != type) { 537 bcm2835_gpio_irq_config(pc, offset, false); 538 pc->irq_type[offset] = type; 539 bcm2835_gpio_irq_config(pc, offset, true); 540 } 541 break; 542 543 case IRQ_TYPE_EDGE_BOTH: 544 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { 545 /* RISING already enabled, enable FALLING too */ 546 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; 547 bcm2835_gpio_irq_config(pc, offset, true); 548 pc->irq_type[offset] = type; 549 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { 550 /* FALLING already enabled, enable RISING too */ 551 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; 552 bcm2835_gpio_irq_config(pc, offset, true); 553 pc->irq_type[offset] = type; 554 } else if (pc->irq_type[offset] != type) { 555 bcm2835_gpio_irq_config(pc, offset, false); 556 pc->irq_type[offset] = type; 557 bcm2835_gpio_irq_config(pc, offset, true); 558 } 559 break; 560 561 case IRQ_TYPE_LEVEL_HIGH: 562 case IRQ_TYPE_LEVEL_LOW: 563 if (pc->irq_type[offset] != type) { 564 bcm2835_gpio_irq_config(pc, offset, false); 565 pc->irq_type[offset] = type; 566 bcm2835_gpio_irq_config(pc, offset, true); 567 } 568 break; 569 570 default: 571 return -EINVAL; 572 } 573 return 0; 574 } 575 576 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) 577 { 578 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 579 unsigned gpio = irqd_to_hwirq(data); 580 unsigned offset = GPIO_REG_SHIFT(gpio); 581 unsigned bank = GPIO_REG_OFFSET(gpio); 582 unsigned long flags; 583 int ret; 584 585 spin_lock_irqsave(&pc->irq_lock[bank], flags); 586 587 if (test_bit(offset, &pc->enabled_irq_map[bank])) 588 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); 589 else 590 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 591 592 if (type & IRQ_TYPE_EDGE_BOTH) 593 irq_set_handler_locked(data, handle_edge_irq); 594 else 595 irq_set_handler_locked(data, handle_level_irq); 596 597 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 598 599 return ret; 600 } 601 602 static void bcm2835_gpio_irq_ack(struct irq_data *data) 603 { 604 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data); 605 unsigned gpio = irqd_to_hwirq(data); 606 607 bcm2835_gpio_set_bit(pc, GPEDS0, gpio); 608 } 609 610 static struct irq_chip bcm2835_gpio_irq_chip = { 611 .name = MODULE_NAME, 612 .irq_enable = bcm2835_gpio_irq_enable, 613 .irq_disable = bcm2835_gpio_irq_disable, 614 .irq_set_type = bcm2835_gpio_irq_set_type, 615 .irq_ack = bcm2835_gpio_irq_ack, 616 .irq_mask = bcm2835_gpio_irq_disable, 617 .irq_unmask = bcm2835_gpio_irq_enable, 618 }; 619 620 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 621 { 622 return ARRAY_SIZE(bcm2835_gpio_groups); 623 } 624 625 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, 626 unsigned selector) 627 { 628 return bcm2835_gpio_groups[selector]; 629 } 630 631 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, 632 unsigned selector, 633 const unsigned **pins, 634 unsigned *num_pins) 635 { 636 *pins = &bcm2835_gpio_pins[selector].number; 637 *num_pins = 1; 638 639 return 0; 640 } 641 642 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, 643 struct seq_file *s, 644 unsigned offset) 645 { 646 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 647 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); 648 const char *fname = bcm2835_functions[fsel]; 649 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); 650 int irq = irq_find_mapping(pc->irq_domain, offset); 651 652 seq_printf(s, "function %s in %s; irq %d (%s)", 653 fname, value ? "hi" : "lo", 654 irq, irq_type_names[pc->irq_type[offset]]); 655 } 656 657 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, 658 struct pinctrl_map *maps, unsigned num_maps) 659 { 660 int i; 661 662 for (i = 0; i < num_maps; i++) 663 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 664 kfree(maps[i].data.configs.configs); 665 666 kfree(maps); 667 } 668 669 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, 670 struct device_node *np, u32 pin, u32 fnum, 671 struct pinctrl_map **maps) 672 { 673 struct pinctrl_map *map = *maps; 674 675 if (fnum >= ARRAY_SIZE(bcm2835_functions)) { 676 dev_err(pc->dev, "%s: invalid brcm,function %d\n", 677 of_node_full_name(np), fnum); 678 return -EINVAL; 679 } 680 681 map->type = PIN_MAP_TYPE_MUX_GROUP; 682 map->data.mux.group = bcm2835_gpio_groups[pin]; 683 map->data.mux.function = bcm2835_functions[fnum]; 684 (*maps)++; 685 686 return 0; 687 } 688 689 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, 690 struct device_node *np, u32 pin, u32 pull, 691 struct pinctrl_map **maps) 692 { 693 struct pinctrl_map *map = *maps; 694 unsigned long *configs; 695 696 if (pull > 2) { 697 dev_err(pc->dev, "%s: invalid brcm,pull %d\n", 698 of_node_full_name(np), pull); 699 return -EINVAL; 700 } 701 702 configs = kzalloc(sizeof(*configs), GFP_KERNEL); 703 if (!configs) 704 return -ENOMEM; 705 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull); 706 707 map->type = PIN_MAP_TYPE_CONFIGS_PIN; 708 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; 709 map->data.configs.configs = configs; 710 map->data.configs.num_configs = 1; 711 (*maps)++; 712 713 return 0; 714 } 715 716 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 717 struct device_node *np, 718 struct pinctrl_map **map, unsigned *num_maps) 719 { 720 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 721 struct property *pins, *funcs, *pulls; 722 int num_pins, num_funcs, num_pulls, maps_per_pin; 723 struct pinctrl_map *maps, *cur_map; 724 int i, err; 725 u32 pin, func, pull; 726 727 pins = of_find_property(np, "brcm,pins", NULL); 728 if (!pins) { 729 dev_err(pc->dev, "%s: missing brcm,pins property\n", 730 of_node_full_name(np)); 731 return -EINVAL; 732 } 733 734 funcs = of_find_property(np, "brcm,function", NULL); 735 pulls = of_find_property(np, "brcm,pull", NULL); 736 737 if (!funcs && !pulls) { 738 dev_err(pc->dev, 739 "%s: neither brcm,function nor brcm,pull specified\n", 740 of_node_full_name(np)); 741 return -EINVAL; 742 } 743 744 num_pins = pins->length / 4; 745 num_funcs = funcs ? (funcs->length / 4) : 0; 746 num_pulls = pulls ? (pulls->length / 4) : 0; 747 748 if (num_funcs > 1 && num_funcs != num_pins) { 749 dev_err(pc->dev, 750 "%s: brcm,function must have 1 or %d entries\n", 751 of_node_full_name(np), num_pins); 752 return -EINVAL; 753 } 754 755 if (num_pulls > 1 && num_pulls != num_pins) { 756 dev_err(pc->dev, 757 "%s: brcm,pull must have 1 or %d entries\n", 758 of_node_full_name(np), num_pins); 759 return -EINVAL; 760 } 761 762 maps_per_pin = 0; 763 if (num_funcs) 764 maps_per_pin++; 765 if (num_pulls) 766 maps_per_pin++; 767 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps), 768 GFP_KERNEL); 769 if (!maps) 770 return -ENOMEM; 771 772 for (i = 0; i < num_pins; i++) { 773 err = of_property_read_u32_index(np, "brcm,pins", i, &pin); 774 if (err) 775 goto out; 776 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) { 777 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n", 778 of_node_full_name(np), pin); 779 err = -EINVAL; 780 goto out; 781 } 782 783 if (num_funcs) { 784 err = of_property_read_u32_index(np, "brcm,function", 785 (num_funcs > 1) ? i : 0, &func); 786 if (err) 787 goto out; 788 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, 789 func, &cur_map); 790 if (err) 791 goto out; 792 } 793 if (num_pulls) { 794 err = of_property_read_u32_index(np, "brcm,pull", 795 (num_pulls > 1) ? i : 0, &pull); 796 if (err) 797 goto out; 798 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, 799 pull, &cur_map); 800 if (err) 801 goto out; 802 } 803 } 804 805 *map = maps; 806 *num_maps = num_pins * maps_per_pin; 807 808 return 0; 809 810 out: 811 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); 812 return err; 813 } 814 815 static const struct pinctrl_ops bcm2835_pctl_ops = { 816 .get_groups_count = bcm2835_pctl_get_groups_count, 817 .get_group_name = bcm2835_pctl_get_group_name, 818 .get_group_pins = bcm2835_pctl_get_group_pins, 819 .pin_dbg_show = bcm2835_pctl_pin_dbg_show, 820 .dt_node_to_map = bcm2835_pctl_dt_node_to_map, 821 .dt_free_map = bcm2835_pctl_dt_free_map, 822 }; 823 824 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) 825 { 826 return BCM2835_FSEL_COUNT; 827 } 828 829 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, 830 unsigned selector) 831 { 832 return bcm2835_functions[selector]; 833 } 834 835 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, 836 unsigned selector, 837 const char * const **groups, 838 unsigned * const num_groups) 839 { 840 /* every pin can do every function */ 841 *groups = bcm2835_gpio_groups; 842 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups); 843 844 return 0; 845 } 846 847 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, 848 unsigned func_selector, 849 unsigned group_selector) 850 { 851 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 852 853 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); 854 855 return 0; 856 } 857 858 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, 859 struct pinctrl_gpio_range *range, 860 unsigned offset) 861 { 862 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 863 864 /* disable by setting to GPIO_IN */ 865 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); 866 } 867 868 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 869 struct pinctrl_gpio_range *range, 870 unsigned offset, 871 bool input) 872 { 873 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 874 enum bcm2835_fsel fsel = input ? 875 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; 876 877 bcm2835_pinctrl_fsel_set(pc, offset, fsel); 878 879 return 0; 880 } 881 882 static const struct pinmux_ops bcm2835_pmx_ops = { 883 .get_functions_count = bcm2835_pmx_get_functions_count, 884 .get_function_name = bcm2835_pmx_get_function_name, 885 .get_function_groups = bcm2835_pmx_get_function_groups, 886 .set_mux = bcm2835_pmx_set, 887 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 888 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 889 }; 890 891 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, 892 unsigned pin, unsigned long *config) 893 { 894 /* No way to read back config in HW */ 895 return -ENOTSUPP; 896 } 897 898 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, 899 unsigned pin, unsigned long *configs, 900 unsigned num_configs) 901 { 902 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 903 enum bcm2835_pinconf_param param; 904 u16 arg; 905 u32 off, bit; 906 int i; 907 908 for (i = 0; i < num_configs; i++) { 909 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]); 910 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]); 911 912 if (param != BCM2835_PINCONF_PARAM_PULL) 913 return -EINVAL; 914 915 off = GPIO_REG_OFFSET(pin); 916 bit = GPIO_REG_SHIFT(pin); 917 918 bcm2835_gpio_wr(pc, GPPUD, arg & 3); 919 /* 920 * Docs say to wait 150 cycles, but not of what. We assume a 921 * 1 MHz clock here, which is pretty slow... 922 */ 923 udelay(150); 924 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); 925 udelay(150); 926 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); 927 } /* for each config */ 928 929 return 0; 930 } 931 932 static const struct pinconf_ops bcm2835_pinconf_ops = { 933 .pin_config_get = bcm2835_pinconf_get, 934 .pin_config_set = bcm2835_pinconf_set, 935 }; 936 937 static struct pinctrl_desc bcm2835_pinctrl_desc = { 938 .name = MODULE_NAME, 939 .pins = bcm2835_gpio_pins, 940 .npins = ARRAY_SIZE(bcm2835_gpio_pins), 941 .pctlops = &bcm2835_pctl_ops, 942 .pmxops = &bcm2835_pmx_ops, 943 .confops = &bcm2835_pinconf_ops, 944 .owner = THIS_MODULE, 945 }; 946 947 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { 948 .name = MODULE_NAME, 949 .npins = BCM2835_NUM_GPIOS, 950 }; 951 952 static int bcm2835_pinctrl_probe(struct platform_device *pdev) 953 { 954 struct device *dev = &pdev->dev; 955 struct device_node *np = dev->of_node; 956 struct bcm2835_pinctrl *pc; 957 struct resource iomem; 958 int err, i; 959 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS); 960 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS); 961 962 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 963 if (!pc) 964 return -ENOMEM; 965 966 platform_set_drvdata(pdev, pc); 967 pc->dev = dev; 968 969 err = of_address_to_resource(np, 0, &iomem); 970 if (err) { 971 dev_err(dev, "could not get IO memory\n"); 972 return err; 973 } 974 975 pc->base = devm_ioremap_resource(dev, &iomem); 976 if (IS_ERR(pc->base)) 977 return PTR_ERR(pc->base); 978 979 pc->gpio_chip = bcm2835_gpio_chip; 980 pc->gpio_chip.parent = dev; 981 pc->gpio_chip.of_node = np; 982 983 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS, 984 &irq_domain_simple_ops, NULL); 985 if (!pc->irq_domain) { 986 dev_err(dev, "could not create IRQ domain\n"); 987 return -ENOMEM; 988 } 989 990 for (i = 0; i < BCM2835_NUM_GPIOS; i++) { 991 int irq = irq_create_mapping(pc->irq_domain, i); 992 irq_set_lockdep_class(irq, &gpio_lock_class); 993 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip, 994 handle_level_irq); 995 irq_set_chip_data(irq, pc); 996 } 997 998 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 999 unsigned long events; 1000 unsigned offset; 1001 int len; 1002 char *name; 1003 1004 /* clear event detection flags */ 1005 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); 1006 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); 1007 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); 1008 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); 1009 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); 1010 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); 1011 1012 /* clear all the events */ 1013 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); 1014 for_each_set_bit(offset, &events, 32) 1015 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); 1016 1017 pc->irq[i] = irq_of_parse_and_map(np, i); 1018 pc->irq_data[i].pc = pc; 1019 pc->irq_data[i].bank = i; 1020 spin_lock_init(&pc->irq_lock[i]); 1021 1022 len = strlen(dev_name(pc->dev)) + 16; 1023 name = devm_kzalloc(pc->dev, len, GFP_KERNEL); 1024 if (!name) 1025 return -ENOMEM; 1026 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); 1027 1028 err = devm_request_irq(dev, pc->irq[i], 1029 bcm2835_gpio_irq_handler, IRQF_SHARED, 1030 name, &pc->irq_data[i]); 1031 if (err) { 1032 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]); 1033 return err; 1034 } 1035 } 1036 1037 err = gpiochip_add_data(&pc->gpio_chip, pc); 1038 if (err) { 1039 dev_err(dev, "could not add GPIO chip\n"); 1040 return err; 1041 } 1042 1043 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc); 1044 if (IS_ERR(pc->pctl_dev)) { 1045 gpiochip_remove(&pc->gpio_chip); 1046 return PTR_ERR(pc->pctl_dev); 1047 } 1048 1049 pc->gpio_range = bcm2835_pinctrl_gpio_range; 1050 pc->gpio_range.base = pc->gpio_chip.base; 1051 pc->gpio_range.gc = &pc->gpio_chip; 1052 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); 1053 1054 return 0; 1055 } 1056 1057 static int bcm2835_pinctrl_remove(struct platform_device *pdev) 1058 { 1059 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev); 1060 1061 gpiochip_remove(&pc->gpio_chip); 1062 1063 return 0; 1064 } 1065 1066 static const struct of_device_id bcm2835_pinctrl_match[] = { 1067 { .compatible = "brcm,bcm2835-gpio" }, 1068 {} 1069 }; 1070 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match); 1071 1072 static struct platform_driver bcm2835_pinctrl_driver = { 1073 .probe = bcm2835_pinctrl_probe, 1074 .remove = bcm2835_pinctrl_remove, 1075 .driver = { 1076 .name = MODULE_NAME, 1077 .of_match_table = bcm2835_pinctrl_match, 1078 }, 1079 }; 1080 module_platform_driver(bcm2835_pinctrl_driver); 1081 1082 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren"); 1083 MODULE_DESCRIPTION("BCM2835 Pin control driver"); 1084 MODULE_LICENSE("GPL"); 1085