1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2013-2017 Broadcom
3 
4 #include <linux/err.h>
5 #include <linux/init.h>
6 #include <linux/io.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/seq_file.h>
11 #include <linux/slab.h>
12 
13 #include <linux/pinctrl/pinconf-generic.h>
14 #include <linux/pinctrl/pinconf.h>
15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/pinctrl/pinmux.h>
17 
18 #include "../core.h"
19 #include "../pinctrl-utils.h"
20 
21 /* BCM281XX Pin Control Registers Definitions */
22 
23 /* Function Select bits are the same for all pin control registers */
24 #define BCM281XX_PIN_REG_F_SEL_MASK		0x0700
25 #define BCM281XX_PIN_REG_F_SEL_SHIFT		8
26 
27 /* Standard pin register */
28 #define BCM281XX_STD_PIN_REG_DRV_STR_MASK	0x0007
29 #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT	0
30 #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK	0x0008
31 #define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT	3
32 #define BCM281XX_STD_PIN_REG_SLEW_MASK		0x0010
33 #define BCM281XX_STD_PIN_REG_SLEW_SHIFT		4
34 #define BCM281XX_STD_PIN_REG_PULL_UP_MASK	0x0020
35 #define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT	5
36 #define BCM281XX_STD_PIN_REG_PULL_DN_MASK	0x0040
37 #define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT	6
38 #define BCM281XX_STD_PIN_REG_HYST_MASK		0x0080
39 #define BCM281XX_STD_PIN_REG_HYST_SHIFT		7
40 
41 /* I2C pin register */
42 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK	0x0004
43 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT	2
44 #define BCM281XX_I2C_PIN_REG_SLEW_MASK		0x0008
45 #define BCM281XX_I2C_PIN_REG_SLEW_SHIFT		3
46 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK	0x0070
47 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT	4
48 
49 /* HDMI pin register */
50 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK	0x0008
51 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT	3
52 #define BCM281XX_HDMI_PIN_REG_MODE_MASK		0x0010
53 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT	4
54 
55 /*
56  * bcm281xx_pin_type - types of pin register
57  */
58 enum bcm281xx_pin_type {
59 	BCM281XX_PIN_TYPE_UNKNOWN = 0,
60 	BCM281XX_PIN_TYPE_STD,
61 	BCM281XX_PIN_TYPE_I2C,
62 	BCM281XX_PIN_TYPE_HDMI,
63 };
64 
65 static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
66 static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
67 static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
68 
69 /*
70  * bcm281xx_pin_function- define pin function
71  */
72 struct bcm281xx_pin_function {
73 	const char *name;
74 	const char * const *groups;
75 	const unsigned ngroups;
76 };
77 
78 /*
79  * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
80  * @reg_base - base of pinctrl registers
81  */
82 struct bcm281xx_pinctrl_data {
83 	void __iomem *reg_base;
84 
85 	/* List of all pins */
86 	const struct pinctrl_pin_desc *pins;
87 	const unsigned npins;
88 
89 	const struct bcm281xx_pin_function *functions;
90 	const unsigned nfunctions;
91 
92 	struct regmap *regmap;
93 };
94 
95 /*
96  * Pin number definition.  The order here must be the same as defined in the
97  * PADCTRLREG block in the RDB.
98  */
99 #define BCM281XX_PIN_ADCSYNC		0
100 #define BCM281XX_PIN_BAT_RM		1
101 #define BCM281XX_PIN_BSC1_SCL		2
102 #define BCM281XX_PIN_BSC1_SDA		3
103 #define BCM281XX_PIN_BSC2_SCL		4
104 #define BCM281XX_PIN_BSC2_SDA		5
105 #define BCM281XX_PIN_CLASSGPWR		6
106 #define BCM281XX_PIN_CLK_CX8		7
107 #define BCM281XX_PIN_CLKOUT_0		8
108 #define BCM281XX_PIN_CLKOUT_1		9
109 #define BCM281XX_PIN_CLKOUT_2		10
110 #define BCM281XX_PIN_CLKOUT_3		11
111 #define BCM281XX_PIN_CLKREQ_IN_0	12
112 #define BCM281XX_PIN_CLKREQ_IN_1	13
113 #define BCM281XX_PIN_CWS_SYS_REQ1	14
114 #define BCM281XX_PIN_CWS_SYS_REQ2	15
115 #define BCM281XX_PIN_CWS_SYS_REQ3	16
116 #define BCM281XX_PIN_DIGMIC1_CLK	17
117 #define BCM281XX_PIN_DIGMIC1_DQ		18
118 #define BCM281XX_PIN_DIGMIC2_CLK	19
119 #define BCM281XX_PIN_DIGMIC2_DQ		20
120 #define BCM281XX_PIN_GPEN13		21
121 #define BCM281XX_PIN_GPEN14		22
122 #define BCM281XX_PIN_GPEN15		23
123 #define BCM281XX_PIN_GPIO00		24
124 #define BCM281XX_PIN_GPIO01		25
125 #define BCM281XX_PIN_GPIO02		26
126 #define BCM281XX_PIN_GPIO03		27
127 #define BCM281XX_PIN_GPIO04		28
128 #define BCM281XX_PIN_GPIO05		29
129 #define BCM281XX_PIN_GPIO06		30
130 #define BCM281XX_PIN_GPIO07		31
131 #define BCM281XX_PIN_GPIO08		32
132 #define BCM281XX_PIN_GPIO09		33
133 #define BCM281XX_PIN_GPIO10		34
134 #define BCM281XX_PIN_GPIO11		35
135 #define BCM281XX_PIN_GPIO12		36
136 #define BCM281XX_PIN_GPIO13		37
137 #define BCM281XX_PIN_GPIO14		38
138 #define BCM281XX_PIN_GPS_PABLANK	39
139 #define BCM281XX_PIN_GPS_TMARK		40
140 #define BCM281XX_PIN_HDMI_SCL		41
141 #define BCM281XX_PIN_HDMI_SDA		42
142 #define BCM281XX_PIN_IC_DM		43
143 #define BCM281XX_PIN_IC_DP		44
144 #define BCM281XX_PIN_KP_COL_IP_0	45
145 #define BCM281XX_PIN_KP_COL_IP_1	46
146 #define BCM281XX_PIN_KP_COL_IP_2	47
147 #define BCM281XX_PIN_KP_COL_IP_3	48
148 #define BCM281XX_PIN_KP_ROW_OP_0	49
149 #define BCM281XX_PIN_KP_ROW_OP_1	50
150 #define BCM281XX_PIN_KP_ROW_OP_2	51
151 #define BCM281XX_PIN_KP_ROW_OP_3	52
152 #define BCM281XX_PIN_LCD_B_0		53
153 #define BCM281XX_PIN_LCD_B_1		54
154 #define BCM281XX_PIN_LCD_B_2		55
155 #define BCM281XX_PIN_LCD_B_3		56
156 #define BCM281XX_PIN_LCD_B_4		57
157 #define BCM281XX_PIN_LCD_B_5		58
158 #define BCM281XX_PIN_LCD_B_6		59
159 #define BCM281XX_PIN_LCD_B_7		60
160 #define BCM281XX_PIN_LCD_G_0		61
161 #define BCM281XX_PIN_LCD_G_1		62
162 #define BCM281XX_PIN_LCD_G_2		63
163 #define BCM281XX_PIN_LCD_G_3		64
164 #define BCM281XX_PIN_LCD_G_4		65
165 #define BCM281XX_PIN_LCD_G_5		66
166 #define BCM281XX_PIN_LCD_G_6		67
167 #define BCM281XX_PIN_LCD_G_7		68
168 #define BCM281XX_PIN_LCD_HSYNC		69
169 #define BCM281XX_PIN_LCD_OE		70
170 #define BCM281XX_PIN_LCD_PCLK		71
171 #define BCM281XX_PIN_LCD_R_0		72
172 #define BCM281XX_PIN_LCD_R_1		73
173 #define BCM281XX_PIN_LCD_R_2		74
174 #define BCM281XX_PIN_LCD_R_3		75
175 #define BCM281XX_PIN_LCD_R_4		76
176 #define BCM281XX_PIN_LCD_R_5		77
177 #define BCM281XX_PIN_LCD_R_6		78
178 #define BCM281XX_PIN_LCD_R_7		79
179 #define BCM281XX_PIN_LCD_VSYNC		80
180 #define BCM281XX_PIN_MDMGPIO0		81
181 #define BCM281XX_PIN_MDMGPIO1		82
182 #define BCM281XX_PIN_MDMGPIO2		83
183 #define BCM281XX_PIN_MDMGPIO3		84
184 #define BCM281XX_PIN_MDMGPIO4		85
185 #define BCM281XX_PIN_MDMGPIO5		86
186 #define BCM281XX_PIN_MDMGPIO6		87
187 #define BCM281XX_PIN_MDMGPIO7		88
188 #define BCM281XX_PIN_MDMGPIO8		89
189 #define BCM281XX_PIN_MPHI_DATA_0	90
190 #define BCM281XX_PIN_MPHI_DATA_1	91
191 #define BCM281XX_PIN_MPHI_DATA_2	92
192 #define BCM281XX_PIN_MPHI_DATA_3	93
193 #define BCM281XX_PIN_MPHI_DATA_4	94
194 #define BCM281XX_PIN_MPHI_DATA_5	95
195 #define BCM281XX_PIN_MPHI_DATA_6	96
196 #define BCM281XX_PIN_MPHI_DATA_7	97
197 #define BCM281XX_PIN_MPHI_DATA_8	98
198 #define BCM281XX_PIN_MPHI_DATA_9	99
199 #define BCM281XX_PIN_MPHI_DATA_10	100
200 #define BCM281XX_PIN_MPHI_DATA_11	101
201 #define BCM281XX_PIN_MPHI_DATA_12	102
202 #define BCM281XX_PIN_MPHI_DATA_13	103
203 #define BCM281XX_PIN_MPHI_DATA_14	104
204 #define BCM281XX_PIN_MPHI_DATA_15	105
205 #define BCM281XX_PIN_MPHI_HA0		106
206 #define BCM281XX_PIN_MPHI_HAT0		107
207 #define BCM281XX_PIN_MPHI_HAT1		108
208 #define BCM281XX_PIN_MPHI_HCE0_N	109
209 #define BCM281XX_PIN_MPHI_HCE1_N	110
210 #define BCM281XX_PIN_MPHI_HRD_N		111
211 #define BCM281XX_PIN_MPHI_HWR_N		112
212 #define BCM281XX_PIN_MPHI_RUN0		113
213 #define BCM281XX_PIN_MPHI_RUN1		114
214 #define BCM281XX_PIN_MTX_SCAN_CLK	115
215 #define BCM281XX_PIN_MTX_SCAN_DATA	116
216 #define BCM281XX_PIN_NAND_AD_0		117
217 #define BCM281XX_PIN_NAND_AD_1		118
218 #define BCM281XX_PIN_NAND_AD_2		119
219 #define BCM281XX_PIN_NAND_AD_3		120
220 #define BCM281XX_PIN_NAND_AD_4		121
221 #define BCM281XX_PIN_NAND_AD_5		122
222 #define BCM281XX_PIN_NAND_AD_6		123
223 #define BCM281XX_PIN_NAND_AD_7		124
224 #define BCM281XX_PIN_NAND_ALE		125
225 #define BCM281XX_PIN_NAND_CEN_0		126
226 #define BCM281XX_PIN_NAND_CEN_1		127
227 #define BCM281XX_PIN_NAND_CLE		128
228 #define BCM281XX_PIN_NAND_OEN		129
229 #define BCM281XX_PIN_NAND_RDY_0		130
230 #define BCM281XX_PIN_NAND_RDY_1		131
231 #define BCM281XX_PIN_NAND_WEN		132
232 #define BCM281XX_PIN_NAND_WP		133
233 #define BCM281XX_PIN_PC1		134
234 #define BCM281XX_PIN_PC2		135
235 #define BCM281XX_PIN_PMU_INT		136
236 #define BCM281XX_PIN_PMU_SCL		137
237 #define BCM281XX_PIN_PMU_SDA		138
238 #define BCM281XX_PIN_RFST2G_MTSLOTEN3G	139
239 #define BCM281XX_PIN_RGMII_0_RX_CTL	140
240 #define BCM281XX_PIN_RGMII_0_RXC	141
241 #define BCM281XX_PIN_RGMII_0_RXD_0	142
242 #define BCM281XX_PIN_RGMII_0_RXD_1	143
243 #define BCM281XX_PIN_RGMII_0_RXD_2	144
244 #define BCM281XX_PIN_RGMII_0_RXD_3	145
245 #define BCM281XX_PIN_RGMII_0_TX_CTL	146
246 #define BCM281XX_PIN_RGMII_0_TXC	147
247 #define BCM281XX_PIN_RGMII_0_TXD_0	148
248 #define BCM281XX_PIN_RGMII_0_TXD_1	149
249 #define BCM281XX_PIN_RGMII_0_TXD_2	150
250 #define BCM281XX_PIN_RGMII_0_TXD_3	151
251 #define BCM281XX_PIN_RGMII_1_RX_CTL	152
252 #define BCM281XX_PIN_RGMII_1_RXC	153
253 #define BCM281XX_PIN_RGMII_1_RXD_0	154
254 #define BCM281XX_PIN_RGMII_1_RXD_1	155
255 #define BCM281XX_PIN_RGMII_1_RXD_2	156
256 #define BCM281XX_PIN_RGMII_1_RXD_3	157
257 #define BCM281XX_PIN_RGMII_1_TX_CTL	158
258 #define BCM281XX_PIN_RGMII_1_TXC	159
259 #define BCM281XX_PIN_RGMII_1_TXD_0	160
260 #define BCM281XX_PIN_RGMII_1_TXD_1	161
261 #define BCM281XX_PIN_RGMII_1_TXD_2	162
262 #define BCM281XX_PIN_RGMII_1_TXD_3	163
263 #define BCM281XX_PIN_RGMII_GPIO_0	164
264 #define BCM281XX_PIN_RGMII_GPIO_1	165
265 #define BCM281XX_PIN_RGMII_GPIO_2	166
266 #define BCM281XX_PIN_RGMII_GPIO_3	167
267 #define BCM281XX_PIN_RTXDATA2G_TXDATA3G1	168
268 #define BCM281XX_PIN_RTXEN2G_TXDATA3G2	169
269 #define BCM281XX_PIN_RXDATA3G0		170
270 #define BCM281XX_PIN_RXDATA3G1		171
271 #define BCM281XX_PIN_RXDATA3G2		172
272 #define BCM281XX_PIN_SDIO1_CLK		173
273 #define BCM281XX_PIN_SDIO1_CMD		174
274 #define BCM281XX_PIN_SDIO1_DATA_0	175
275 #define BCM281XX_PIN_SDIO1_DATA_1	176
276 #define BCM281XX_PIN_SDIO1_DATA_2	177
277 #define BCM281XX_PIN_SDIO1_DATA_3	178
278 #define BCM281XX_PIN_SDIO4_CLK		179
279 #define BCM281XX_PIN_SDIO4_CMD		180
280 #define BCM281XX_PIN_SDIO4_DATA_0	181
281 #define BCM281XX_PIN_SDIO4_DATA_1	182
282 #define BCM281XX_PIN_SDIO4_DATA_2	183
283 #define BCM281XX_PIN_SDIO4_DATA_3	184
284 #define BCM281XX_PIN_SIM_CLK		185
285 #define BCM281XX_PIN_SIM_DATA		186
286 #define BCM281XX_PIN_SIM_DET		187
287 #define BCM281XX_PIN_SIM_RESETN		188
288 #define BCM281XX_PIN_SIM2_CLK		189
289 #define BCM281XX_PIN_SIM2_DATA		190
290 #define BCM281XX_PIN_SIM2_DET		191
291 #define BCM281XX_PIN_SIM2_RESETN	192
292 #define BCM281XX_PIN_SRI_C		193
293 #define BCM281XX_PIN_SRI_D		194
294 #define BCM281XX_PIN_SRI_E		195
295 #define BCM281XX_PIN_SSP_EXTCLK		196
296 #define BCM281XX_PIN_SSP0_CLK		197
297 #define BCM281XX_PIN_SSP0_FS		198
298 #define BCM281XX_PIN_SSP0_RXD		199
299 #define BCM281XX_PIN_SSP0_TXD		200
300 #define BCM281XX_PIN_SSP2_CLK		201
301 #define BCM281XX_PIN_SSP2_FS_0		202
302 #define BCM281XX_PIN_SSP2_FS_1		203
303 #define BCM281XX_PIN_SSP2_FS_2		204
304 #define BCM281XX_PIN_SSP2_FS_3		205
305 #define BCM281XX_PIN_SSP2_RXD_0		206
306 #define BCM281XX_PIN_SSP2_RXD_1		207
307 #define BCM281XX_PIN_SSP2_TXD_0		208
308 #define BCM281XX_PIN_SSP2_TXD_1		209
309 #define BCM281XX_PIN_SSP3_CLK		210
310 #define BCM281XX_PIN_SSP3_FS		211
311 #define BCM281XX_PIN_SSP3_RXD		212
312 #define BCM281XX_PIN_SSP3_TXD		213
313 #define BCM281XX_PIN_SSP4_CLK		214
314 #define BCM281XX_PIN_SSP4_FS		215
315 #define BCM281XX_PIN_SSP4_RXD		216
316 #define BCM281XX_PIN_SSP4_TXD		217
317 #define BCM281XX_PIN_SSP5_CLK		218
318 #define BCM281XX_PIN_SSP5_FS		219
319 #define BCM281XX_PIN_SSP5_RXD		220
320 #define BCM281XX_PIN_SSP5_TXD		221
321 #define BCM281XX_PIN_SSP6_CLK		222
322 #define BCM281XX_PIN_SSP6_FS		223
323 #define BCM281XX_PIN_SSP6_RXD		224
324 #define BCM281XX_PIN_SSP6_TXD		225
325 #define BCM281XX_PIN_STAT_1		226
326 #define BCM281XX_PIN_STAT_2		227
327 #define BCM281XX_PIN_SYSCLKEN		228
328 #define BCM281XX_PIN_TRACECLK		229
329 #define BCM281XX_PIN_TRACEDT00		230
330 #define BCM281XX_PIN_TRACEDT01		231
331 #define BCM281XX_PIN_TRACEDT02		232
332 #define BCM281XX_PIN_TRACEDT03		233
333 #define BCM281XX_PIN_TRACEDT04		234
334 #define BCM281XX_PIN_TRACEDT05		235
335 #define BCM281XX_PIN_TRACEDT06		236
336 #define BCM281XX_PIN_TRACEDT07		237
337 #define BCM281XX_PIN_TRACEDT08		238
338 #define BCM281XX_PIN_TRACEDT09		239
339 #define BCM281XX_PIN_TRACEDT10		240
340 #define BCM281XX_PIN_TRACEDT11		241
341 #define BCM281XX_PIN_TRACEDT12		242
342 #define BCM281XX_PIN_TRACEDT13		243
343 #define BCM281XX_PIN_TRACEDT14		244
344 #define BCM281XX_PIN_TRACEDT15		245
345 #define BCM281XX_PIN_TXDATA3G0		246
346 #define BCM281XX_PIN_TXPWRIND		247
347 #define BCM281XX_PIN_UARTB1_UCTS	248
348 #define BCM281XX_PIN_UARTB1_URTS	249
349 #define BCM281XX_PIN_UARTB1_URXD	250
350 #define BCM281XX_PIN_UARTB1_UTXD	251
351 #define BCM281XX_PIN_UARTB2_URXD	252
352 #define BCM281XX_PIN_UARTB2_UTXD	253
353 #define BCM281XX_PIN_UARTB3_UCTS	254
354 #define BCM281XX_PIN_UARTB3_URTS	255
355 #define BCM281XX_PIN_UARTB3_URXD	256
356 #define BCM281XX_PIN_UARTB3_UTXD	257
357 #define BCM281XX_PIN_UARTB4_UCTS	258
358 #define BCM281XX_PIN_UARTB4_URTS	259
359 #define BCM281XX_PIN_UARTB4_URXD	260
360 #define BCM281XX_PIN_UARTB4_UTXD	261
361 #define BCM281XX_PIN_VC_CAM1_SCL	262
362 #define BCM281XX_PIN_VC_CAM1_SDA	263
363 #define BCM281XX_PIN_VC_CAM2_SCL	264
364 #define BCM281XX_PIN_VC_CAM2_SDA	265
365 #define BCM281XX_PIN_VC_CAM3_SCL	266
366 #define BCM281XX_PIN_VC_CAM3_SDA	267
367 
368 #define BCM281XX_PIN_DESC(a, b, c) \
369 	{ .number = a, .name = b, .drv_data = &c##_pin }
370 
371 /*
372  * Pin description definition.  The order here must be the same as defined in
373  * the PADCTRLREG block in the RDB, since the pin number is used as an index
374  * into this array.
375  */
376 static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
377 	BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
378 	BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
379 	BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
380 	BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
381 	BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
382 	BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
383 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
384 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
385 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
386 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
387 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
388 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
389 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
390 	BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
391 	BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
392 	BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
393 	BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
394 	BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
395 	BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
396 	BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
397 	BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
398 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
399 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
400 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
401 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
402 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
403 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
404 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
405 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
406 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
407 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
408 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
409 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
410 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
411 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
412 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
413 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
414 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
415 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
416 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
417 	BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
418 	BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
419 	BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
420 	BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
421 	BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
422 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
423 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
424 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
425 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
426 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
427 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
428 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
429 	BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
430 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
431 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
432 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
433 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
434 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
435 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
436 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
437 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
438 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
439 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
440 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
441 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
442 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
443 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
444 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
445 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
446 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
447 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
448 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
449 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
450 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
451 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
452 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
453 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
454 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
455 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
456 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
457 	BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
458 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
459 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
460 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
461 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
462 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
463 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
464 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
465 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
466 	BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
467 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
468 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
469 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
470 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
471 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
472 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
473 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
474 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
475 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
476 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
477 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
478 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
479 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
480 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
481 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
482 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
483 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
484 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
485 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
486 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
487 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
488 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
489 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
490 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
491 	BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
492 	BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
493 	BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
494 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
495 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
496 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
497 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
498 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
499 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
500 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
501 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
502 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
503 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
504 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
505 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
506 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
507 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
508 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
509 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
510 	BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
511 	BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
512 	BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
513 	BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
514 	BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
515 	BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
516 	BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
517 		std),
518 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
519 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
520 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
521 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
522 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
523 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
524 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
525 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
526 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
527 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
528 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
529 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
530 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
531 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
532 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
533 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
534 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
535 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
536 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
537 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
538 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
539 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
540 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
541 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
542 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
543 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
544 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
545 	BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
546 	BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
547 		"rtxdata2g_txdata3g1", std),
548 	BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
549 		std),
550 	BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
551 	BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
552 	BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
553 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
554 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
555 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
556 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
557 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
558 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
559 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
560 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
561 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
562 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
563 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
564 	BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
565 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
566 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
567 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
568 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
569 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
570 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
571 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
572 	BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
573 	BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
574 	BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
575 	BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
576 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
577 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
578 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
579 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
580 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
581 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
582 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
583 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
584 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
585 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
586 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
587 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
588 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
589 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
590 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
591 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
592 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
593 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
594 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
595 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
596 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
597 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
598 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
599 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
600 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
601 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
602 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
603 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
604 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
605 	BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
606 	BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
607 	BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
608 	BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
609 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
610 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
611 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
612 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
613 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
614 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
615 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
616 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
617 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
618 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
619 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
620 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
621 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
622 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
623 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
624 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
625 	BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
626 	BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
627 	BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
628 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
629 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
630 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
631 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
632 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
633 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
634 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
635 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
636 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
637 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
638 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
639 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
640 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
641 	BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
642 	BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
643 	BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
644 	BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
645 	BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
646 	BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
647 	BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
648 };
649 
650 static const char * const bcm281xx_alt_groups[] = {
651 	"adcsync",
652 	"bat_rm",
653 	"bsc1_scl",
654 	"bsc1_sda",
655 	"bsc2_scl",
656 	"bsc2_sda",
657 	"classgpwr",
658 	"clk_cx8",
659 	"clkout_0",
660 	"clkout_1",
661 	"clkout_2",
662 	"clkout_3",
663 	"clkreq_in_0",
664 	"clkreq_in_1",
665 	"cws_sys_req1",
666 	"cws_sys_req2",
667 	"cws_sys_req3",
668 	"digmic1_clk",
669 	"digmic1_dq",
670 	"digmic2_clk",
671 	"digmic2_dq",
672 	"gpen13",
673 	"gpen14",
674 	"gpen15",
675 	"gpio00",
676 	"gpio01",
677 	"gpio02",
678 	"gpio03",
679 	"gpio04",
680 	"gpio05",
681 	"gpio06",
682 	"gpio07",
683 	"gpio08",
684 	"gpio09",
685 	"gpio10",
686 	"gpio11",
687 	"gpio12",
688 	"gpio13",
689 	"gpio14",
690 	"gps_pablank",
691 	"gps_tmark",
692 	"hdmi_scl",
693 	"hdmi_sda",
694 	"ic_dm",
695 	"ic_dp",
696 	"kp_col_ip_0",
697 	"kp_col_ip_1",
698 	"kp_col_ip_2",
699 	"kp_col_ip_3",
700 	"kp_row_op_0",
701 	"kp_row_op_1",
702 	"kp_row_op_2",
703 	"kp_row_op_3",
704 	"lcd_b_0",
705 	"lcd_b_1",
706 	"lcd_b_2",
707 	"lcd_b_3",
708 	"lcd_b_4",
709 	"lcd_b_5",
710 	"lcd_b_6",
711 	"lcd_b_7",
712 	"lcd_g_0",
713 	"lcd_g_1",
714 	"lcd_g_2",
715 	"lcd_g_3",
716 	"lcd_g_4",
717 	"lcd_g_5",
718 	"lcd_g_6",
719 	"lcd_g_7",
720 	"lcd_hsync",
721 	"lcd_oe",
722 	"lcd_pclk",
723 	"lcd_r_0",
724 	"lcd_r_1",
725 	"lcd_r_2",
726 	"lcd_r_3",
727 	"lcd_r_4",
728 	"lcd_r_5",
729 	"lcd_r_6",
730 	"lcd_r_7",
731 	"lcd_vsync",
732 	"mdmgpio0",
733 	"mdmgpio1",
734 	"mdmgpio2",
735 	"mdmgpio3",
736 	"mdmgpio4",
737 	"mdmgpio5",
738 	"mdmgpio6",
739 	"mdmgpio7",
740 	"mdmgpio8",
741 	"mphi_data_0",
742 	"mphi_data_1",
743 	"mphi_data_2",
744 	"mphi_data_3",
745 	"mphi_data_4",
746 	"mphi_data_5",
747 	"mphi_data_6",
748 	"mphi_data_7",
749 	"mphi_data_8",
750 	"mphi_data_9",
751 	"mphi_data_10",
752 	"mphi_data_11",
753 	"mphi_data_12",
754 	"mphi_data_13",
755 	"mphi_data_14",
756 	"mphi_data_15",
757 	"mphi_ha0",
758 	"mphi_hat0",
759 	"mphi_hat1",
760 	"mphi_hce0_n",
761 	"mphi_hce1_n",
762 	"mphi_hrd_n",
763 	"mphi_hwr_n",
764 	"mphi_run0",
765 	"mphi_run1",
766 	"mtx_scan_clk",
767 	"mtx_scan_data",
768 	"nand_ad_0",
769 	"nand_ad_1",
770 	"nand_ad_2",
771 	"nand_ad_3",
772 	"nand_ad_4",
773 	"nand_ad_5",
774 	"nand_ad_6",
775 	"nand_ad_7",
776 	"nand_ale",
777 	"nand_cen_0",
778 	"nand_cen_1",
779 	"nand_cle",
780 	"nand_oen",
781 	"nand_rdy_0",
782 	"nand_rdy_1",
783 	"nand_wen",
784 	"nand_wp",
785 	"pc1",
786 	"pc2",
787 	"pmu_int",
788 	"pmu_scl",
789 	"pmu_sda",
790 	"rfst2g_mtsloten3g",
791 	"rgmii_0_rx_ctl",
792 	"rgmii_0_rxc",
793 	"rgmii_0_rxd_0",
794 	"rgmii_0_rxd_1",
795 	"rgmii_0_rxd_2",
796 	"rgmii_0_rxd_3",
797 	"rgmii_0_tx_ctl",
798 	"rgmii_0_txc",
799 	"rgmii_0_txd_0",
800 	"rgmii_0_txd_1",
801 	"rgmii_0_txd_2",
802 	"rgmii_0_txd_3",
803 	"rgmii_1_rx_ctl",
804 	"rgmii_1_rxc",
805 	"rgmii_1_rxd_0",
806 	"rgmii_1_rxd_1",
807 	"rgmii_1_rxd_2",
808 	"rgmii_1_rxd_3",
809 	"rgmii_1_tx_ctl",
810 	"rgmii_1_txc",
811 	"rgmii_1_txd_0",
812 	"rgmii_1_txd_1",
813 	"rgmii_1_txd_2",
814 	"rgmii_1_txd_3",
815 	"rgmii_gpio_0",
816 	"rgmii_gpio_1",
817 	"rgmii_gpio_2",
818 	"rgmii_gpio_3",
819 	"rtxdata2g_txdata3g1",
820 	"rtxen2g_txdata3g2",
821 	"rxdata3g0",
822 	"rxdata3g1",
823 	"rxdata3g2",
824 	"sdio1_clk",
825 	"sdio1_cmd",
826 	"sdio1_data_0",
827 	"sdio1_data_1",
828 	"sdio1_data_2",
829 	"sdio1_data_3",
830 	"sdio4_clk",
831 	"sdio4_cmd",
832 	"sdio4_data_0",
833 	"sdio4_data_1",
834 	"sdio4_data_2",
835 	"sdio4_data_3",
836 	"sim_clk",
837 	"sim_data",
838 	"sim_det",
839 	"sim_resetn",
840 	"sim2_clk",
841 	"sim2_data",
842 	"sim2_det",
843 	"sim2_resetn",
844 	"sri_c",
845 	"sri_d",
846 	"sri_e",
847 	"ssp_extclk",
848 	"ssp0_clk",
849 	"ssp0_fs",
850 	"ssp0_rxd",
851 	"ssp0_txd",
852 	"ssp2_clk",
853 	"ssp2_fs_0",
854 	"ssp2_fs_1",
855 	"ssp2_fs_2",
856 	"ssp2_fs_3",
857 	"ssp2_rxd_0",
858 	"ssp2_rxd_1",
859 	"ssp2_txd_0",
860 	"ssp2_txd_1",
861 	"ssp3_clk",
862 	"ssp3_fs",
863 	"ssp3_rxd",
864 	"ssp3_txd",
865 	"ssp4_clk",
866 	"ssp4_fs",
867 	"ssp4_rxd",
868 	"ssp4_txd",
869 	"ssp5_clk",
870 	"ssp5_fs",
871 	"ssp5_rxd",
872 	"ssp5_txd",
873 	"ssp6_clk",
874 	"ssp6_fs",
875 	"ssp6_rxd",
876 	"ssp6_txd",
877 	"stat_1",
878 	"stat_2",
879 	"sysclken",
880 	"traceclk",
881 	"tracedt00",
882 	"tracedt01",
883 	"tracedt02",
884 	"tracedt03",
885 	"tracedt04",
886 	"tracedt05",
887 	"tracedt06",
888 	"tracedt07",
889 	"tracedt08",
890 	"tracedt09",
891 	"tracedt10",
892 	"tracedt11",
893 	"tracedt12",
894 	"tracedt13",
895 	"tracedt14",
896 	"tracedt15",
897 	"txdata3g0",
898 	"txpwrind",
899 	"uartb1_ucts",
900 	"uartb1_urts",
901 	"uartb1_urxd",
902 	"uartb1_utxd",
903 	"uartb2_urxd",
904 	"uartb2_utxd",
905 	"uartb3_ucts",
906 	"uartb3_urts",
907 	"uartb3_urxd",
908 	"uartb3_utxd",
909 	"uartb4_ucts",
910 	"uartb4_urts",
911 	"uartb4_urxd",
912 	"uartb4_utxd",
913 	"vc_cam1_scl",
914 	"vc_cam1_sda",
915 	"vc_cam2_scl",
916 	"vc_cam2_sda",
917 	"vc_cam3_scl",
918 	"vc_cam3_sda",
919 };
920 
921 /* Every pin can implement all ALT1-ALT4 functions */
922 #define BCM281XX_PIN_FUNCTION(fcn_name)			\
923 {							\
924 	.name = #fcn_name,				\
925 	.groups = bcm281xx_alt_groups,			\
926 	.ngroups = ARRAY_SIZE(bcm281xx_alt_groups),	\
927 }
928 
929 static const struct bcm281xx_pin_function bcm281xx_functions[] = {
930 	BCM281XX_PIN_FUNCTION(alt1),
931 	BCM281XX_PIN_FUNCTION(alt2),
932 	BCM281XX_PIN_FUNCTION(alt3),
933 	BCM281XX_PIN_FUNCTION(alt4),
934 };
935 
936 static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = {
937 	.pins = bcm281xx_pinctrl_pins,
938 	.npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
939 	.functions = bcm281xx_functions,
940 	.nfunctions = ARRAY_SIZE(bcm281xx_functions),
941 };
942 
943 static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
944 						  unsigned pin)
945 {
946 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
947 
948 	if (pin >= pdata->npins)
949 		return BCM281XX_PIN_TYPE_UNKNOWN;
950 
951 	return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data);
952 }
953 
954 #define BCM281XX_PIN_SHIFT(type, param) \
955 	(BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
956 
957 #define BCM281XX_PIN_MASK(type, param) \
958 	(BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
959 
960 /*
961  * This helper function is used to build up the value and mask used to write to
962  * a pin register, but does not actually write to the register.
963  */
964 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
965 				       u32 param_val, u32 param_shift,
966 				       u32 param_mask)
967 {
968 	*reg_val &= ~param_mask;
969 	*reg_val |= (param_val << param_shift) & param_mask;
970 	*reg_mask |= param_mask;
971 }
972 
973 static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
974 	.reg_bits = 32,
975 	.reg_stride = 4,
976 	.val_bits = 32,
977 	.max_register = BCM281XX_PIN_VC_CAM3_SDA,
978 };
979 
980 static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
981 {
982 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
983 
984 	return pdata->npins;
985 }
986 
987 static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
988 						   unsigned group)
989 {
990 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
991 
992 	return pdata->pins[group].name;
993 }
994 
995 static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
996 					   unsigned group,
997 					   const unsigned **pins,
998 					   unsigned *num_pins)
999 {
1000 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1001 
1002 	*pins = &pdata->pins[group].number;
1003 	*num_pins = 1;
1004 
1005 	return 0;
1006 }
1007 
1008 static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1009 					  struct seq_file *s,
1010 					  unsigned offset)
1011 {
1012 	seq_printf(s, " %s", dev_name(pctldev->dev));
1013 }
1014 
1015 static const struct pinctrl_ops bcm281xx_pinctrl_ops = {
1016 	.get_groups_count = bcm281xx_pinctrl_get_groups_count,
1017 	.get_group_name = bcm281xx_pinctrl_get_group_name,
1018 	.get_group_pins = bcm281xx_pinctrl_get_group_pins,
1019 	.pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
1020 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1021 	.dt_free_map = pinctrl_utils_free_map,
1022 };
1023 
1024 static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1025 {
1026 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1027 
1028 	return pdata->nfunctions;
1029 }
1030 
1031 static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1032 						 unsigned function)
1033 {
1034 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1035 
1036 	return pdata->functions[function].name;
1037 }
1038 
1039 static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1040 					   unsigned function,
1041 					   const char * const **groups,
1042 					   unsigned * const num_groups)
1043 {
1044 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1045 
1046 	*groups = pdata->functions[function].groups;
1047 	*num_groups = pdata->functions[function].ngroups;
1048 
1049 	return 0;
1050 }
1051 
1052 static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1053 			       unsigned function,
1054 			       unsigned group)
1055 {
1056 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1057 	const struct bcm281xx_pin_function *f = &pdata->functions[function];
1058 	u32 offset = 4 * pdata->pins[group].number;
1059 	int rc = 0;
1060 
1061 	dev_dbg(pctldev->dev,
1062 		"%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1063 		__func__, f->name, function, pdata->pins[group].name,
1064 		pdata->pins[group].number, offset);
1065 
1066 	rc = regmap_update_bits(pdata->regmap, offset,
1067 		BCM281XX_PIN_REG_F_SEL_MASK,
1068 		function << BCM281XX_PIN_REG_F_SEL_SHIFT);
1069 	if (rc)
1070 		dev_err(pctldev->dev,
1071 			"Error updating register for pin %s (%d).\n",
1072 			pdata->pins[group].name, pdata->pins[group].number);
1073 
1074 	return rc;
1075 }
1076 
1077 static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1078 	.get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1079 	.get_function_name = bcm281xx_pinctrl_get_fcn_name,
1080 	.get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1081 	.set_mux = bcm281xx_pinmux_set,
1082 };
1083 
1084 static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1085 					   unsigned pin,
1086 					   unsigned long *config)
1087 {
1088 	return -ENOTSUPP;
1089 }
1090 
1091 
1092 /* Goes through the configs and update register val/mask */
1093 static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
1094 				   unsigned pin,
1095 				   unsigned long *configs,
1096 				   unsigned num_configs,
1097 				   u32 *val,
1098 				   u32 *mask)
1099 {
1100 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1101 	int i;
1102 	enum pin_config_param param;
1103 	u32 arg;
1104 
1105 	for (i = 0; i < num_configs; i++) {
1106 		param = pinconf_to_config_param(configs[i]);
1107 		arg = pinconf_to_config_argument(configs[i]);
1108 
1109 		switch (param) {
1110 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1111 			arg = (arg >= 1 ? 1 : 0);
1112 			bcm281xx_pin_update(val, mask, arg,
1113 				BCM281XX_PIN_SHIFT(STD, HYST),
1114 				BCM281XX_PIN_MASK(STD, HYST));
1115 			break;
1116 		/*
1117 		 * The pin bias can only be one of pull-up, pull-down, or
1118 		 * disable.  The user does not need to specify a value for the
1119 		 * property, and the default value from pinconf-generic is
1120 		 * ignored.
1121 		 */
1122 		case PIN_CONFIG_BIAS_DISABLE:
1123 			bcm281xx_pin_update(val, mask, 0,
1124 				BCM281XX_PIN_SHIFT(STD, PULL_UP),
1125 				BCM281XX_PIN_MASK(STD, PULL_UP));
1126 			bcm281xx_pin_update(val, mask, 0,
1127 				BCM281XX_PIN_SHIFT(STD, PULL_DN),
1128 				BCM281XX_PIN_MASK(STD, PULL_DN));
1129 			break;
1130 
1131 		case PIN_CONFIG_BIAS_PULL_UP:
1132 			bcm281xx_pin_update(val, mask, 1,
1133 				BCM281XX_PIN_SHIFT(STD, PULL_UP),
1134 				BCM281XX_PIN_MASK(STD, PULL_UP));
1135 			bcm281xx_pin_update(val, mask, 0,
1136 				BCM281XX_PIN_SHIFT(STD, PULL_DN),
1137 				BCM281XX_PIN_MASK(STD, PULL_DN));
1138 			break;
1139 
1140 		case PIN_CONFIG_BIAS_PULL_DOWN:
1141 			bcm281xx_pin_update(val, mask, 0,
1142 				BCM281XX_PIN_SHIFT(STD, PULL_UP),
1143 				BCM281XX_PIN_MASK(STD, PULL_UP));
1144 			bcm281xx_pin_update(val, mask, 1,
1145 				BCM281XX_PIN_SHIFT(STD, PULL_DN),
1146 				BCM281XX_PIN_MASK(STD, PULL_DN));
1147 			break;
1148 
1149 		case PIN_CONFIG_SLEW_RATE:
1150 			arg = (arg >= 1 ? 1 : 0);
1151 			bcm281xx_pin_update(val, mask, arg,
1152 				BCM281XX_PIN_SHIFT(STD, SLEW),
1153 				BCM281XX_PIN_MASK(STD, SLEW));
1154 			break;
1155 
1156 		case PIN_CONFIG_INPUT_ENABLE:
1157 			/* inversed since register is for input _disable_ */
1158 			arg = (arg >= 1 ? 0 : 1);
1159 			bcm281xx_pin_update(val, mask, arg,
1160 				BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
1161 				BCM281XX_PIN_MASK(STD, INPUT_DIS));
1162 			break;
1163 
1164 		case PIN_CONFIG_DRIVE_STRENGTH:
1165 			/* Valid range is 2-16 mA, even numbers only */
1166 			if ((arg < 2) || (arg > 16) || (arg % 2)) {
1167 				dev_err(pctldev->dev,
1168 					"Invalid Drive Strength value (%d) for "
1169 					"pin %s (%d). Valid values are "
1170 					"(2..16) mA, even numbers only.\n",
1171 					arg, pdata->pins[pin].name, pin);
1172 				return -EINVAL;
1173 			}
1174 			bcm281xx_pin_update(val, mask, (arg/2)-1,
1175 				BCM281XX_PIN_SHIFT(STD, DRV_STR),
1176 				BCM281XX_PIN_MASK(STD, DRV_STR));
1177 			break;
1178 
1179 		default:
1180 			dev_err(pctldev->dev,
1181 				"Unrecognized pin config %d for pin %s (%d).\n",
1182 				param, pdata->pins[pin].name, pin);
1183 			return -EINVAL;
1184 
1185 		} /* switch config */
1186 	} /* for each config */
1187 
1188 	return 0;
1189 }
1190 
1191 /*
1192  * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1193  * register with the following mapping:
1194  *   0b000: No pull-up
1195  *   0b001: 1200 Ohm
1196  *   0b010: 1800 Ohm
1197  *   0b011: 720 Ohm
1198  *   0b100: 2700 Ohm
1199  *   0b101: 831 Ohm
1200  *   0b110: 1080 Ohm
1201  *   0b111: 568 Ohm
1202  * This array maps pull-up strength in Ohms to register values (1+index).
1203  */
1204 static const u16 bcm281xx_pullup_map[] = {
1205 	1200, 1800, 720, 2700, 831, 1080, 568
1206 };
1207 
1208 /* Goes through the configs and update register val/mask */
1209 static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
1210 				   unsigned pin,
1211 				   unsigned long *configs,
1212 				   unsigned num_configs,
1213 				   u32 *val,
1214 				   u32 *mask)
1215 {
1216 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1217 	int i, j;
1218 	enum pin_config_param param;
1219 	u32 arg;
1220 
1221 	for (i = 0; i < num_configs; i++) {
1222 		param = pinconf_to_config_param(configs[i]);
1223 		arg = pinconf_to_config_argument(configs[i]);
1224 
1225 		switch (param) {
1226 		case PIN_CONFIG_BIAS_PULL_UP:
1227 			for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
1228 				if (bcm281xx_pullup_map[j] == arg)
1229 					break;
1230 
1231 			if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
1232 				dev_err(pctldev->dev,
1233 					"Invalid pull-up value (%d) for pin %s "
1234 					"(%d). Valid values are 568, 720, 831, "
1235 					"1080, 1200, 1800, 2700 Ohms.\n",
1236 					arg, pdata->pins[pin].name, pin);
1237 				return -EINVAL;
1238 			}
1239 
1240 			bcm281xx_pin_update(val, mask, j+1,
1241 				BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1242 				BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1243 			break;
1244 
1245 		case PIN_CONFIG_BIAS_DISABLE:
1246 			bcm281xx_pin_update(val, mask, 0,
1247 				BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1248 				BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1249 			break;
1250 
1251 		case PIN_CONFIG_SLEW_RATE:
1252 			arg = (arg >= 1 ? 1 : 0);
1253 			bcm281xx_pin_update(val, mask, arg,
1254 				BCM281XX_PIN_SHIFT(I2C, SLEW),
1255 				BCM281XX_PIN_MASK(I2C, SLEW));
1256 			break;
1257 
1258 		case PIN_CONFIG_INPUT_ENABLE:
1259 			/* inversed since register is for input _disable_ */
1260 			arg = (arg >= 1 ? 0 : 1);
1261 			bcm281xx_pin_update(val, mask, arg,
1262 				BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
1263 				BCM281XX_PIN_MASK(I2C, INPUT_DIS));
1264 			break;
1265 
1266 		default:
1267 			dev_err(pctldev->dev,
1268 				"Unrecognized pin config %d for pin %s (%d).\n",
1269 				param, pdata->pins[pin].name, pin);
1270 			return -EINVAL;
1271 
1272 		} /* switch config */
1273 	} /* for each config */
1274 
1275 	return 0;
1276 }
1277 
1278 /* Goes through the configs and update register val/mask */
1279 static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
1280 				    unsigned pin,
1281 				    unsigned long *configs,
1282 				    unsigned num_configs,
1283 				    u32 *val,
1284 				    u32 *mask)
1285 {
1286 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1287 	int i;
1288 	enum pin_config_param param;
1289 	u32 arg;
1290 
1291 	for (i = 0; i < num_configs; i++) {
1292 		param = pinconf_to_config_param(configs[i]);
1293 		arg = pinconf_to_config_argument(configs[i]);
1294 
1295 		switch (param) {
1296 		case PIN_CONFIG_SLEW_RATE:
1297 			arg = (arg >= 1 ? 1 : 0);
1298 			bcm281xx_pin_update(val, mask, arg,
1299 				BCM281XX_PIN_SHIFT(HDMI, MODE),
1300 				BCM281XX_PIN_MASK(HDMI, MODE));
1301 			break;
1302 
1303 		case PIN_CONFIG_INPUT_ENABLE:
1304 			/* inversed since register is for input _disable_ */
1305 			arg = (arg >= 1 ? 0 : 1);
1306 			bcm281xx_pin_update(val, mask, arg,
1307 				BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
1308 				BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
1309 			break;
1310 
1311 		default:
1312 			dev_err(pctldev->dev,
1313 				"Unrecognized pin config %d for pin %s (%d).\n",
1314 				param, pdata->pins[pin].name, pin);
1315 			return -EINVAL;
1316 
1317 		} /* switch config */
1318 	} /* for each config */
1319 
1320 	return 0;
1321 }
1322 
1323 static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
1324 					   unsigned pin,
1325 					   unsigned long *configs,
1326 					   unsigned num_configs)
1327 {
1328 	struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1329 	enum bcm281xx_pin_type pin_type;
1330 	u32 offset = 4 * pin;
1331 	u32 cfg_val, cfg_mask;
1332 	int rc;
1333 
1334 	cfg_val = 0;
1335 	cfg_mask = 0;
1336 	pin_type = pin_type_get(pctldev, pin);
1337 
1338 	/* Different pins have different configuration options */
1339 	switch (pin_type) {
1340 	case BCM281XX_PIN_TYPE_STD:
1341 		rc = bcm281xx_std_pin_update(pctldev, pin, configs,
1342 			num_configs, &cfg_val, &cfg_mask);
1343 		break;
1344 
1345 	case BCM281XX_PIN_TYPE_I2C:
1346 		rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
1347 			num_configs, &cfg_val, &cfg_mask);
1348 		break;
1349 
1350 	case BCM281XX_PIN_TYPE_HDMI:
1351 		rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
1352 			num_configs, &cfg_val, &cfg_mask);
1353 		break;
1354 
1355 	default:
1356 		dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
1357 			pdata->pins[pin].name, pin);
1358 		return -EINVAL;
1359 
1360 	} /* switch pin type */
1361 
1362 	if (rc)
1363 		return rc;
1364 
1365 	dev_dbg(pctldev->dev,
1366 		"%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
1367 		__func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
1368 
1369 	rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
1370 	if (rc) {
1371 		dev_err(pctldev->dev,
1372 			"Error updating register for pin %s (%d).\n",
1373 			pdata->pins[pin].name, pin);
1374 		return rc;
1375 	}
1376 
1377 	return 0;
1378 }
1379 
1380 static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
1381 	.pin_config_get = bcm281xx_pinctrl_pin_config_get,
1382 	.pin_config_set = bcm281xx_pinctrl_pin_config_set,
1383 };
1384 
1385 static struct pinctrl_desc bcm281xx_pinctrl_desc = {
1386 	/* name, pins, npins members initialized in probe function */
1387 	.pctlops = &bcm281xx_pinctrl_ops,
1388 	.pmxops = &bcm281xx_pinctrl_pinmux_ops,
1389 	.confops = &bcm281xx_pinctrl_pinconf_ops,
1390 	.owner = THIS_MODULE,
1391 };
1392 
1393 static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1394 {
1395 	struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1396 	struct pinctrl_dev *pctl;
1397 
1398 	/* So far We can assume there is only 1 bank of registers */
1399 	pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
1400 	if (IS_ERR(pdata->reg_base)) {
1401 		dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1402 		return PTR_ERR(pdata->reg_base);
1403 	}
1404 
1405 	/* Initialize the dynamic part of pinctrl_desc */
1406 	pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
1407 		&bcm281xx_pinctrl_regmap_config);
1408 	if (IS_ERR(pdata->regmap)) {
1409 		dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
1410 		return -ENODEV;
1411 	}
1412 
1413 	bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
1414 	bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins;
1415 	bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins;
1416 
1417 	pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata);
1418 	if (IS_ERR(pctl)) {
1419 		dev_err(&pdev->dev, "Failed to register pinctrl\n");
1420 		return PTR_ERR(pctl);
1421 	}
1422 
1423 	platform_set_drvdata(pdev, pdata);
1424 
1425 	return 0;
1426 }
1427 
1428 static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
1429 	{ .compatible = "brcm,bcm11351-pinctrl", },
1430 	{ },
1431 };
1432 
1433 static struct platform_driver bcm281xx_pinctrl_driver = {
1434 	.driver = {
1435 		.name = "bcm281xx-pinctrl",
1436 		.of_match_table = bcm281xx_pinctrl_of_match,
1437 	},
1438 };
1439 builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);
1440