1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Copyright (C) 2019 IBM Corp.  */
3 
4 #ifndef ASPEED_PINMUX_H
5 #define ASPEED_PINMUX_H
6 
7 #include <linux/regmap.h>
8 
9 /*
10  * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
11  * functions. The SoC function enabled on a pin is determined on a priority
12  * basis where a given pin can provide a number of different signal types.
13  *
14  * The signal active on a pin is described by both a priority level and
15  * compound logical expressions involving multiple operators, registers and
16  * bits. Some difficulty arises as the pin's function bit masks for each
17  * priority level are frequently not the same (i.e. cannot just flip a bit to
18  * change from a high to low priority signal), or even in the same register.
19  * Further, not all signals can be unmuxed, as some expressions depend on
20  * values in the hardware strapping register (which may be treated as
21  * read-only).
22  *
23  * SoC Multi-function Pin Expression Examples
24  * ------------------------------------------
25  *
26  * Here are some sample mux configurations from the AST2400 and AST2500
27  * datasheets to illustrate the corner cases, roughly in order of least to most
28  * corner. The signal priorities are in decending order from P0 (highest).
29  *
30  * D6 is a pin with a single function (beside GPIO); a high priority signal
31  * that participates in one function:
32  *
33  * Ball | Default | P0 Signal | P0 Expression               | P1 Signal | P1 Expression | Other
34  * -----+---------+-----------+-----------------------------+-----------+---------------+----------
35  *  D6    GPIOA0    MAC1LINK    SCU80[0]=1                                                GPIOA0
36  * -----+---------+-----------+-----------------------------+-----------+---------------+----------
37  *
38  * C5 is a multi-signal pin (high and low priority signals). Here we touch
39  * different registers for the different functions that enable each signal:
40  *
41  * -----+---------+-----------+-----------------------------+-----------+---------------+----------
42  *  C5    GPIOA4    SCL9        SCU90[22]=1                   TIMER5      SCU80[4]=1      GPIOA4
43  * -----+---------+-----------+-----------------------------+-----------+---------------+----------
44  *
45  * E19 is a single-signal pin with two functions that influence the active
46  * signal. In this case both bits have the same meaning - enable a dedicated
47  * LPC reset pin. However it's not always the case that the bits in the
48  * OR-relationship have the same meaning.
49  *
50  * -----+---------+-----------+-----------------------------+-----------+---------------+----------
51  *  E19   GPIOB4    LPCRST#     SCU80[12]=1 | Strap[14]=1                                 GPIOB4
52  * -----+---------+-----------+-----------------------------+-----------+---------------+----------
53  *
54  * For example, pin B19 has a low-priority signal that's enabled by two
55  * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
56  * bit in the STRAP register. The ACPI bit configures signals on pins in
57  * addition to B19. Both of the low priority functions as well as the high
58  * priority function must be disabled for GPIOF1 to be used.
59  *
60  * Ball | Default | P0 Signal | P0 Expression                           | P1 Signal | P1 Expression                          | Other
61  * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
62  *  B19   GPIOF1    NDCD4       SCU80[25]=1                               SIOPBI#     SCUA4[12]=1 | Strap[19]=0                GPIOF1
63  * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
64  *
65  * For pin E18, the SoC ANDs the expected state of three bits to determine the
66  * pin's active signal:
67  *
68  * * SCU3C[3]: Enable external SOC reset function
69  * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
70  * * SCU90[31]: Select SPI interface CS# output
71  *
72  * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
73  *  E18   GPIOB7    EXTRST#     SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0    SPICS1#     SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1   GPIOB7
74  * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
75  *
76  * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
77  * selecting the signals on pin E18)
78  *
79  * Pin T5 is a multi-signal pin with a more complex configuration:
80  *
81  * Ball | Default | P0 Signal | P0 Expression                | P1 Signal | P1 Expression | Other
82  * -----+---------+-----------+------------------------------+-----------+---------------+----------
83  *  T5    GPIOL1    VPIDE       SCU90[5:4]!=0 & SCU84[17]=1    NDCD1       SCU84[17]=1     GPIOL1
84  * -----+---------+-----------+------------------------------+-----------+---------------+----------
85  *
86  * The high priority signal configuration is best thought of in terms of its
87  * exploded form, with reference to the SCU90[5:4] bits:
88  *
89  * * SCU90[5:4]=00: disable
90  * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
91  * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
92  * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
93  *
94  * Re-writing:
95  *
96  * -----+---------+-----------+------------------------------+-----------+---------------+----------
97  *  T5    GPIOL1    VPIDE      (SCU90[5:4]=1 & SCU84[17]=1)    NDCD1       SCU84[17]=1     GPIOL1
98  *                             | (SCU90[5:4]=2 & SCU84[17]=1)
99  *                             | (SCU90[5:4]=3 & SCU84[17]=1)
100  * -----+---------+-----------+------------------------------+-----------+---------------+----------
101  *
102  * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
103  * function pin", where the signal itself is determined by whether SCU94[5:4]
104  * is disabled or in one of the 18, 24 or 30bit video modes.
105  *
106  * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
107  * W1 and U5:
108  *
109  * -----+---------+-----------+------------------------------+-----------+---------------+----------
110  *  W1    GPIOL6    VPIB0       SCU90[5:4]=3 & SCU84[22]=1     TXD1        SCU84[22]=1     GPIOL6
111  *  U5    GPIOL7    VPIB1       SCU90[5:4]=3 & SCU84[23]=1     RXD1        SCU84[23]=1     GPIOL7
112  * -----+---------+-----------+------------------------------+-----------+---------------+----------
113  *
114  * The examples of T5 and W1 are particularly fertile, as they also demonstrate
115  * that despite operating as part of the video input bus each signal needs to
116  * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
117  * register bit. This is a little crazy if the bus doesn't have optional
118  * signals, but is used to decent effect with some of the UARTs where not all
119  * signals are required. However, this isn't done consistently - UART1 is
120  * enabled on a per-pin basis, and by contrast, all signals for UART6 are
121  * enabled by a single bit.
122  *
123  * Further, the high and low priority signals listed in the table above share
124  * a configuration bit. The VPI signals should operate in concert in a single
125  * function, but the UART signals should retain the ability to be configured
126  * independently. This pushes the implementation down the path of tagging a
127  * signal's expressions with the function they participate in, rather than
128  * defining masks affecting multiple signals per function. The latter approach
129  * fails in this instance where applying the configuration for the UART pin of
130  * interest will stomp on the state of other UART signals when disabling the
131  * VPI functions on the current pin.
132  *
133  * Ball |  Default   | P0 Signal | P0 Expression             | P1 Signal | P1 Expression | Other
134  * -----+------------+-----------+---------------------------+-----------+---------------+------------
135  *  A12   RGMII1TXCK   GPIOT0      SCUA0[0]=1                  RMII1TXEN   Strap[6]=0      RGMII1TXCK
136  *  B12   RGMII1TXCTL  GPIOT1      SCUA0[1]=1                  –           Strap[6]=0      RGMII1TXCTL
137  * -----+------------+-----------+---------------------------+-----------+---------------+------------
138  *
139  * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
140  * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
141  * should be treated like any other signal type with full function expression
142  * requirements, and not assumed to be the default case. Separately, GPIOT0 and
143  * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
144  * pins in the function's group to disable the higher-priority signals such
145  * that the signal for the function of interest is correctly enabled.
146  *
147  * Finally, three priority levels aren't always enough; the AST2500 brings with
148  * it 18 pins of five priority levels, however the 18 pins only use three of
149  * the five priority levels.
150  *
151  * Ultimately the requirement to control pins in the examples above drive the
152  * design:
153  *
154  * * Pins provide signals according to functions activated in the mux
155  *   configuration
156  *
157  * * Pins provide up to five signal types in a priority order
158  *
159  * * For priorities levels defined on a pin, each priority provides one signal
160  *
161  * * Enabling lower priority signals requires higher priority signals be
162  *   disabled
163  *
164  * * A function represents a set of signals; functions are distinct if they
165  *   do not share a subset of signals (and may be distinct if they are a
166  *   strict subset).
167  *
168  * * Signals participate in one or more functions or groups
169  *
170  * * A function is described by an expression of one or more signal
171  *   descriptors, which compare bit values in a register
172  *
173  * * A signal expression is the smallest set of signal descriptors whose
174  *   comparisons must evaluate 'true' for a signal to be enabled on a pin.
175  *
176  * * A signal participating in a function is active on a pin if evaluating all
177  *   signal descriptors in the pin's signal expression for the function yields
178  *   a 'true' result
179  *
180  * * A signal at a given priority on a given pin is active if any of the
181  *   functions in which the signal participates are active, and no higher
182  *   priority signal on the pin is active
183  *
184  * * GPIO is configured per-pin
185  *
186  * And so:
187  *
188  * * To disable a signal, any function(s) activating the signal must be
189  *   disabled
190  *
191  * * Each pin must know the signal expressions of functions in which it
192  *   participates, for the purpose of enabling the Other function. This is done
193  *   by deactivating all functions that activate higher priority signals on the
194  *   pin.
195  *
196  * As a concrete example:
197  *
198  * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
199  *
200  * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
201  *
202  * * The NDCD1 signal participates in just its own NDCD1 function
203  *
204  * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
205  *   prioritised
206  *
207  * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
208  *   and VPI30 functions all be disabled
209  *
210  * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
211  *   to provide GPIOL6
212  *
213  * Considerations
214  * --------------
215  *
216  * If pinctrl allows us to allocate a pin we can configure a function without
217  * concern for the function of already allocated pins, if pin groups are
218  * created with respect to the SoC functions in which they participate. This is
219  * intuitive, but it did not feel obvious from the bit/pin relationships.
220  *
221  * Conversely, failing to allocate all pins in a group indicates some bits (as
222  * well as pins) required for the group's configuration will already be in use,
223  * likely in a way that's inconsistent with the requirements of the failed
224  * group.
225  *
226  * Implementation
227  * --------------
228  *
229  * Beyond the documentation below the various structures and helper macros that
230  * allow the implementation to hang together are defined. The macros are fairly
231  * dense, so below we walk through some raw examples of the configuration
232  * tables in an effort to clarify the concepts.
233  *
234  * The complexity of configuring the mux combined with the scale of the pins
235  * and functions was a concern, so the table design along with the macro jungle
236  * is an attempt to address it. The rough principles of the approach are:
237  *
238  * 1. Use a data-driven solution rather than embedding state into code
239  * 2. Minimise editing to the specifics of the given mux configuration
240  * 3. Detect as many errors as possible at compile time
241  *
242  * Addressing point 3 leads to naming of symbols in terms of the four
243  * properties associated with a given mux configuration: The pin, the signal,
244  * the group and the function. In this way copy/paste errors cause duplicate
245  * symbols to be defined, which prevents successful compilation. Failing to
246  * properly parent the tables leads to unused symbol warnings, and use of
247  * designated initialisers and additional warnings ensures that there are
248  * no override errors in the pin, group and function arrays.
249  *
250  * Addressing point 2 drives the development of the macro jungle, as it
251  * centralises the definition noise at the cost of taking some time to
252  * understand.
253  *
254  * Here's a complete, concrete "pre-processed" example of the table structures
255  * used to describe the D6 ball from the examples above:
256  *
257  * ```
258  * static const struct aspeed_sig_desc sig_descs_MAC1LINK_MAC1LINK[] = {
259  *     {
260  *         .ip = ASPEED_IP_SCU,
261  *         .reg = 0x80,
262  *         .mask = BIT(0),
263  *         .enable = 1,
264  *         .disable = 0
265  *     },
266  * };
267  *
268  * static const struct aspeed_sig_expr sig_expr_MAC1LINK_MAC1LINK = {
269  *     .signal = "MAC1LINK",
270  *     .function = "MAC1LINK",
271  *     .ndescs = ARRAY_SIZE(sig_descs_MAC1LINK_MAC1LINK),
272  *     .descs = &(sig_descs_MAC1LINK_MAC1LINK)[0],
273  * };
274  *
275  * static const struct aspeed_sig_expr *sig_exprs_MAC1LINK_MAC1LINK[] = {
276  *     &sig_expr_MAC1LINK_MAC1LINK,
277  *     NULL,
278  * };
279  *
280  * static const struct aspeed_sig_desc sig_descs_GPIOA0_GPIOA0[] = { };
281  *
282  * static const struct aspeed_sig_expr sig_expr_GPIOA0_GPIOA0 = {
283  *     .signal = "GPIOA0",
284  *     .function = "GPIOA0",
285  *     .ndescs = ARRAY_SIZE(sig_descs_GPIOA0_GPIOA0),
286  *     .descs = &(sig_descs_GPIOA0_GPIOA0)[0],
287  * };
288  *
289  * static const struct aspeed_sig_expr *sig_exprs_GPIOA0_GPIOA0[] = {
290  *     &sig_expr_GPIOA0_GPIOA0,
291  *     NULL
292  * };
293  *
294  * static const struct aspeed_sig_expr **pin_exprs_0[] = {
295  *     sig_exprs_MAC1LINK_MAC1LINK,
296  *     sig_exprs_GPIOA0_GPIOA0,
297  *     NULL
298  * };
299  *
300  * static const struct aspeed_pin_desc pin_0 = { "0", (&pin_exprs_0[0]) };
301  * static const int group_pins_MAC1LINK[] = { 0 };
302  * static const char *func_groups_MAC1LINK[] = { "MAC1LINK" };
303  *
304  * static struct pinctrl_pin_desc aspeed_g4_pins[] = {
305  *     [0] = { .number = 0, .name = "D6", .drv_data = &pin_0 },
306  * };
307  *
308  * static const struct aspeed_pin_group aspeed_g4_groups[] = {
309  *     {
310  *         .name = "MAC1LINK",
311  *         .pins = &(group_pins_MAC1LINK)[0],
312  *         .npins = ARRAY_SIZE(group_pins_MAC1LINK),
313  *     },
314  * };
315  *
316  * static const struct aspeed_pin_function aspeed_g4_functions[] = {
317  *     {
318  *         .name = "MAC1LINK",
319  *         .groups = &func_groups_MAC1LINK[0],
320  *         .ngroups = ARRAY_SIZE(func_groups_MAC1LINK),
321  *     },
322  * };
323  * ```
324  *
325  * At the end of the day much of the above code is compressed into the
326  * following two lines:
327  *
328  * ```
329  * #define D6 0
330  * SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
331  * ```
332  *
333  * The two examples below show just the differences from the example above.
334  *
335  * Ball E18 demonstrates a function, EXTRST, that requires multiple descriptors
336  * be set for it to be muxed:
337  *
338  * ```
339  * static const struct aspeed_sig_desc sig_descs_EXTRST_EXTRST[] = {
340  *     {
341  *         .ip = ASPEED_IP_SCU,
342  *         .reg = 0x3C,
343  *         .mask = BIT(3),
344  *         .enable = 1,
345  *         .disable = 0
346  *     },
347  *     {
348  *         .ip = ASPEED_IP_SCU,
349  *         .reg = 0x80,
350  *         .mask = BIT(15),
351  *         .enable = 1,
352  *         .disable = 0
353  *     },
354  *     {
355  *         .ip = ASPEED_IP_SCU,
356  *         .reg = 0x90,
357  *         .mask = BIT(31),
358  *         .enable = 0,
359  *         .disable = 1
360  *     },
361  * };
362  *
363  * static const struct aspeed_sig_expr sig_expr_EXTRST_EXTRST = {
364  *     .signal = "EXTRST",
365  *     .function = "EXTRST",
366  *     .ndescs = ARRAY_SIZE(sig_descs_EXTRST_EXTRST),
367  *     .descs = &(sig_descs_EXTRST_EXTRST)[0],
368  * };
369  * ...
370  * ```
371  *
372  * For ball E19, we have multiple functions enabling a single signal, LPCRST#.
373  * The data structures look like:
374  *
375  * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRST[] = {
376  *     {
377  *         .ip = ASPEED_IP_SCU,
378  *         .reg = 0x80,
379  *         .mask = BIT(12),
380  *         .enable = 1,
381  *         .disable = 0
382  *     },
383  * };
384  *
385  * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRST = {
386  *     .signal = "LPCRST",
387  *     .function = "LPCRST",
388  *     .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRST),
389  *     .descs = &(sig_descs_LPCRST_LPCRST)[0],
390  * };
391  *
392  * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRSTS[] = {
393  *     {
394  *         .ip = ASPEED_IP_SCU,
395  *         .reg = 0x70,
396  *         .mask = BIT(14),
397  *         .enable = 1,
398  *         .disable = 0
399  *     },
400  * };
401  *
402  * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRSTS = {
403  *     .signal = "LPCRST",
404  *     .function = "LPCRSTS",
405  *     .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRSTS),
406  *     .descs = &(sig_descs_LPCRST_LPCRSTS)[0],
407  * };
408  *
409  * static const struct aspeed_sig_expr *sig_exprs_LPCRST_LPCRST[] = {
410  *     &sig_expr_LPCRST_LPCRST,
411  *     &sig_expr_LPCRST_LPCRSTS,
412  *     NULL,
413  * };
414  * ...
415  * ```
416  *
417  * Both expressions listed in the sig_exprs_LPCRST_LPCRST array need to be set
418  * to disabled for the associated GPIO to be muxed.
419  *
420  */
421 
422 #define ASPEED_IP_SCU		0
423 #define ASPEED_IP_GFX		1
424 #define ASPEED_IP_LPC		2
425 #define ASPEED_NR_PINMUX_IPS	3
426 
427  /**
428   * A signal descriptor, which describes the register, bits and the
429   * enable/disable values that should be compared or written.
430   *
431   * @ip: The IP block identifier, used as an index into the regmap array in
432   *      struct aspeed_pinctrl_data
433   * @reg: The register offset with respect to the base address of the IP block
434   * @mask: The mask to apply to the register. The lowest set bit of the mask is
435   *        used to derive the shift value.
436   * @enable: The value that enables the function. Value should be in the LSBs,
437   *          not at the position of the mask.
438   * @disable: The value that disables the function. Value should be in the
439   *           LSBs, not at the position of the mask.
440   */
441 struct aspeed_sig_desc {
442 	unsigned int ip;
443 	unsigned int reg;
444 	u32 mask;
445 	u32 enable;
446 	u32 disable;
447 };
448 
449 /**
450  * Describes a signal expression. The expression is evaluated by ANDing the
451  * evaluation of the descriptors.
452  *
453  * @signal: The signal name for the priority level on the pin. If the signal
454  *          type is GPIO, then the signal name must begin with the
455  *          prefix "GPI", e.g. GPIOA0, GPIT0 etc.
456  * @function: The name of the function the signal participates in for the
457  *            associated expression. For pin-specific GPIO, the function
458  *            name must match the signal name.
459  * @ndescs: The number of signal descriptors in the expression
460  * @descs: Pointer to an array of signal descriptors that comprise the
461  *         function expression
462  */
463 struct aspeed_sig_expr {
464 	const char *signal;
465 	const char *function;
466 	int ndescs;
467 	const struct aspeed_sig_desc *descs;
468 };
469 
470 /**
471  * A struct capturing the list of expressions enabling signals at each priority
472  * for a given pin. The signal configuration for a priority level is evaluated
473  * by ORing the evaluation of the signal expressions in the respective
474  * priority's list.
475  *
476  * @name: A name for the pin
477  * @prios: A pointer to an array of expression list pointers
478  *
479  */
480 struct aspeed_pin_desc {
481 	const char *name;
482 	const struct aspeed_sig_expr ***prios;
483 };
484 
485 /* Macro hell */
486 
487 #define SIG_DESC_IP_BIT(ip, reg, idx, val) \
488 	{ ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
489 
490 /**
491  * Short-hand macro for describing an SCU descriptor enabled by the state of
492  * one bit. The disable value is derived.
493  *
494  * @reg: The signal's associated register, offset from base
495  * @idx: The signal's bit index in the register
496  * @val: The value (0 or 1) that enables the function
497  */
498 #define SIG_DESC_BIT(reg, idx, val) \
499 	SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
500 
501 #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
502 
503 /**
504  * A further short-hand macro expanding to an SCU descriptor enabled by a set
505  * bit.
506  *
507  * @reg: The register, offset from base
508  * @idx: The bit index in the register
509  */
510 #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
511 #define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
512 
513 #define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
514 #define SIG_DESC_LIST_DECL(sig, group, ...) \
515 	static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \
516 		{ __VA_ARGS__ }
517 
518 #define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group
519 #define SIG_EXPR_DECL_(sig, group, func) \
520 	static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \
521 	{ \
522 		.signal = #sig, \
523 		.function = #func, \
524 		.ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \
525 		.descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \
526 	}
527 
528 /**
529  * Declare a signal expression.
530  *
531  * @sig: A macro symbol name for the signal (is subjected to stringification
532  *        and token pasting)
533  * @func: The function in which the signal is participating
534  * @...: Signal descriptors that define the signal expression
535  *
536  * For example, the following declares the ROMD8 signal for the ROM16 function:
537  *
538  *     SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
539  *
540  * And with multiple signal descriptors:
541  *
542  *     SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
543  *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
544  */
545 #define SIG_EXPR_DECL(sig, group, func, ...) \
546 	SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
547 	SIG_EXPR_DECL_(sig, group, func)
548 
549 /**
550  * Declare a pointer to a signal expression
551  *
552  * @sig: The macro symbol name for the signal (subjected to token pasting)
553  * @func: The macro symbol name for the function (subjected to token pasting)
554  */
555 #define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group))
556 
557 #define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group
558 
559 /**
560  * Declare a signal expression list for reference in a struct aspeed_pin_prio.
561  *
562  * @sig: A macro symbol name for the signal (is subjected to token pasting)
563  * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
564  *
565  * For example, the 16-bit ROM bus can be enabled by one of two possible signal
566  * expressions:
567  *
568  *     SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
569  *     SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
570  *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
571  *     SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
572  *              SIG_EXPR_PTR(ROMD8, ROM16S));
573  */
574 #define SIG_EXPR_LIST_DECL(sig, group, ...) \
575 	static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\
576 		{ __VA_ARGS__, NULL }
577 
578 #define stringify(x) #x
579 #define istringify(x) stringify(x)
580 
581 /**
582  * Create an expression symbol alias from (signal, group) to (pin, signal).
583  *
584  * @pin: The pin number
585  * @sig: The signal name
586  * @group: The name of the group of which the pin is a member that is
587  *         associated with the function's signal
588  *
589  * Using an alias in this way enables detection of copy/paste errors (defining
590  * the signal for a group multiple times) whilst enabling multiple pin groups
591  * to exist for a signal without intrusive side-effects on defining the list of
592  * signals available on a pin.
593  */
594 #define SIG_EXPR_LIST_ALIAS(pin, sig, group) \
595 	static const struct aspeed_sig_expr *\
596 		SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \
597 		__attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group)))))
598 
599 /**
600  * A short-hand macro for declaring a function expression and an expression
601  * list with a single expression (SE) and a single group (SG) of pins.
602  *
603  * @pin: The pin the signal will be routed to
604  * @sig: The signal that will be routed to the pin for the function
605  * @func: A macro symbol name for the function
606  * @...: Function descriptors that define the function expression
607  *
608  * For example, signal NCTS6 participates in its own function with one group:
609  *
610  *     SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
611  */
612 #define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \
613 	SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
614 	SIG_EXPR_DECL_(sig, func, func); \
615 	SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \
616 	SIG_EXPR_LIST_ALIAS(pin, sig, func)
617 
618 /**
619  * Similar to the above, but for pins with a single expression (SE) and
620  * multiple groups (MG) of pins.
621  *
622  * @pin: The pin the signal will be routed to
623  * @sig: The signal that will be routed to the pin for the function
624  * @group: The name of the function's pin group in which the pin participates
625  * @func: A macro symbol name for the function
626  * @...: Function descriptors that define the function expression
627  */
628 #define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \
629 	SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
630 	SIG_EXPR_DECL_(sig, group, func); \
631 	SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \
632 	SIG_EXPR_LIST_ALIAS(pin, sig, group)
633 
634 /**
635  * Similar to the above, but for pins with a dual expressions (DE) and
636  * and a single group (SG) of pins.
637  *
638  * @pin: The pin the signal will be routed to
639  * @sig: The signal that will be routed to the pin for the function
640  * @group: The name of the function's pin group in which the pin participates
641  * @func: A macro symbol name for the function
642  * @...: Function descriptors that define the function expression
643  */
644 #define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \
645 	SIG_EXPR_LIST_DECL(sig, f0, \
646 			   SIG_EXPR_PTR(sig, f0), \
647 			   SIG_EXPR_PTR(sig, f1)); \
648 	SIG_EXPR_LIST_ALIAS(pin, sig, f0)
649 
650 #define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group)
651 
652 #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
653 #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
654 #define PIN_SYM(pin) pin_ ## pin
655 
656 #define PIN_DECL_(pin, ...) \
657 	static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
658 		{ __VA_ARGS__, NULL }; \
659 	static const struct aspeed_pin_desc PIN_SYM(pin) = \
660 		{ #pin, PIN_EXPRS_PTR(pin) }
661 
662 /**
663  * Declare a single signal pin
664  *
665  * @pin: The pin number
666  * @other: Macro name for "other" functionality (subjected to stringification)
667  * @sig: Macro name for the signal (subjected to stringification)
668  *
669  * For example:
670  *
671  *     #define E3 80
672  *     SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
673  *     PIN_DECL_1(E3, GPIOK0, SCL5);
674  */
675 #define PIN_DECL_1(pin, other, sig) \
676 	SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
677 	PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
678 		  SIG_EXPR_LIST_PTR(pin, other))
679 
680 /**
681  * Single signal, single function pin declaration
682  *
683  * @pin: The pin number
684  * @other: Macro name for "other" functionality (subjected to stringification)
685  * @sig: Macro name for the signal (subjected to stringification)
686  * @...: Signal descriptors that define the function expression
687  *
688  * For example:
689  *
690  *    SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
691  */
692 #define SSSF_PIN_DECL(pin, other, sig, ...) \
693 	SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \
694 	SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
695 	PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
696 		  SIG_EXPR_LIST_PTR(pin, other)); \
697 	FUNC_GROUP_DECL(sig, pin)
698 /**
699  * Declare a two-signal pin
700  *
701  * @pin: The pin number
702  * @other: Macro name for "other" functionality (subjected to stringification)
703  * @high: Macro name for the highest priority signal functions
704  * @low: Macro name for the low signal functions
705  *
706  * For example:
707  *
708  *     #define A8 56
709  *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
710  *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
711  *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
712  *     SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
713  *              SIG_EXPR_PTR(ROMD8, ROM16S));
714  *     SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
715  *     PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
716  */
717 #define PIN_DECL_2(pin, other, high, low) \
718 	SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
719 	PIN_DECL_(pin, \
720 			SIG_EXPR_LIST_PTR(pin, high), \
721 			SIG_EXPR_LIST_PTR(pin, low), \
722 			SIG_EXPR_LIST_PTR(pin, other))
723 
724 #define PIN_DECL_3(pin, other, high, medium, low) \
725 	SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
726 	PIN_DECL_(pin, \
727 			SIG_EXPR_LIST_PTR(pin, high), \
728 			SIG_EXPR_LIST_PTR(pin, medium), \
729 			SIG_EXPR_LIST_PTR(pin, low), \
730 			SIG_EXPR_LIST_PTR(pin, other))
731 
732 #define PIN_DECL_4(pin, other, prio1, prio2, prio3, prio4) \
733 	SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
734 	PIN_DECL_(pin, \
735 			SIG_EXPR_LIST_PTR(pin, prio1), \
736 			SIG_EXPR_LIST_PTR(pin, prio2), \
737 			SIG_EXPR_LIST_PTR(pin, prio3), \
738 			SIG_EXPR_LIST_PTR(pin, prio4), \
739 			SIG_EXPR_LIST_PTR(pin, other))
740 
741 #define GROUP_SYM(group) group_pins_ ## group
742 #define GROUP_DECL(group, ...) \
743 	static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
744 
745 #define FUNC_SYM(func) func_groups_ ## func
746 #define FUNC_DECL_(func, ...) \
747 	static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
748 
749 #define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group)
750 #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
751 #define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
752 
753 #define FUNC_GROUP_DECL(func, ...) \
754 	GROUP_DECL(func, __VA_ARGS__); \
755 	FUNC_DECL_(func, #func)
756 
757 
758 #define GPIO_PIN_DECL(pin, gpio) \
759 	SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \
760 	PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio))
761 
762 struct aspeed_pin_group {
763 	const char *name;
764 	const unsigned int *pins;
765 	const unsigned int npins;
766 };
767 
768 #define ASPEED_PINCTRL_GROUP(name_) { \
769 	.name = #name_, \
770 	.pins = &(GROUP_SYM(name_))[0], \
771 	.npins = ARRAY_SIZE(GROUP_SYM(name_)), \
772 }
773 
774 struct aspeed_pin_function {
775 	const char *name;
776 	const char *const *groups;
777 	unsigned int ngroups;
778 };
779 
780 #define ASPEED_PINCTRL_FUNC(name_, ...) { \
781 	.name = #name_, \
782 	.groups = &FUNC_SYM(name_)[0], \
783 	.ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \
784 }
785 
786 struct aspeed_pinmux_data;
787 
788 struct aspeed_pinmux_ops {
789 	int (*eval)(struct aspeed_pinmux_data *ctx,
790 		    const struct aspeed_sig_expr *expr, bool enabled);
791 	int (*set)(struct aspeed_pinmux_data *ctx,
792 		   const struct aspeed_sig_expr *expr, bool enabled);
793 };
794 
795 struct aspeed_pinmux_data {
796 	struct device *dev;
797 	struct regmap *maps[ASPEED_NR_PINMUX_IPS];
798 
799 	const struct aspeed_pinmux_ops *ops;
800 
801 	const struct aspeed_pin_group *groups;
802 	const unsigned int ngroups;
803 
804 	const struct aspeed_pin_function *functions;
805 	const unsigned int nfunctions;
806 };
807 
808 int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled,
809 			 struct regmap *map);
810 
811 int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx,
812 			 const struct aspeed_sig_expr *expr, bool enabled);
813 
814 static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx,
815 				      const struct aspeed_sig_expr *expr,
816 				      bool enabled)
817 {
818 	return ctx->ops->set(ctx, expr, enabled);
819 }
820 
821 #endif /* ASPEED_PINMUX_H */
822