1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* Copyright (C) 2019 IBM Corp. */ 3 4 #ifndef ASPEED_PINMUX_H 5 #define ASPEED_PINMUX_H 6 7 #include <linux/regmap.h> 8 #include <stdbool.h> 9 10 /* 11 * The ASPEED SoCs provide typically more than 200 pins for GPIO and other 12 * functions. The SoC function enabled on a pin is determined on a priority 13 * basis where a given pin can provide a number of different signal types. 14 * 15 * The signal active on a pin is described by both a priority level and 16 * compound logical expressions involving multiple operators, registers and 17 * bits. Some difficulty arises as the pin's function bit masks for each 18 * priority level are frequently not the same (i.e. cannot just flip a bit to 19 * change from a high to low priority signal), or even in the same register. 20 * Further, not all signals can be unmuxed, as some expressions depend on 21 * values in the hardware strapping register (which may be treated as 22 * read-only). 23 * 24 * SoC Multi-function Pin Expression Examples 25 * ------------------------------------------ 26 * 27 * Here are some sample mux configurations from the AST2400 and AST2500 28 * datasheets to illustrate the corner cases, roughly in order of least to most 29 * corner. The signal priorities are in decending order from P0 (highest). 30 * 31 * D6 is a pin with a single function (beside GPIO); a high priority signal 32 * that participates in one function: 33 * 34 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 35 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 36 * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0 37 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 38 * 39 * C5 is a multi-signal pin (high and low priority signals). Here we touch 40 * different registers for the different functions that enable each signal: 41 * 42 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 43 * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4 44 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 45 * 46 * E19 is a single-signal pin with two functions that influence the active 47 * signal. In this case both bits have the same meaning - enable a dedicated 48 * LPC reset pin. However it's not always the case that the bits in the 49 * OR-relationship have the same meaning. 50 * 51 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 52 * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4 53 * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 54 * 55 * For example, pin B19 has a low-priority signal that's enabled by two 56 * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI 57 * bit in the STRAP register. The ACPI bit configures signals on pins in 58 * addition to B19. Both of the low priority functions as well as the high 59 * priority function must be disabled for GPIOF1 to be used. 60 * 61 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 62 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 63 * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1 64 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 65 * 66 * For pin E18, the SoC ANDs the expected state of three bits to determine the 67 * pin's active signal: 68 * 69 * * SCU3C[3]: Enable external SOC reset function 70 * * SCU80[15]: Enable SPICS1# or EXTRST# function pin 71 * * SCU90[31]: Select SPI interface CS# output 72 * 73 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 74 * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7 75 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 76 * 77 * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for 78 * selecting the signals on pin E18) 79 * 80 * Pin T5 is a multi-signal pin with a more complex configuration: 81 * 82 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 83 * -----+---------+-----------+------------------------------+-----------+---------------+---------- 84 * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1 85 * -----+---------+-----------+------------------------------+-----------+---------------+---------- 86 * 87 * The high priority signal configuration is best thought of in terms of its 88 * exploded form, with reference to the SCU90[5:4] bits: 89 * 90 * * SCU90[5:4]=00: disable 91 * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode. 92 * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode. 93 * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode. 94 * 95 * Re-writing: 96 * 97 * -----+---------+-----------+------------------------------+-----------+---------------+---------- 98 * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1 99 * | (SCU90[5:4]=2 & SCU84[17]=1) 100 * | (SCU90[5:4]=3 & SCU84[17]=1) 101 * -----+---------+-----------+------------------------------+-----------+---------------+---------- 102 * 103 * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE 104 * function pin", where the signal itself is determined by whether SCU94[5:4] 105 * is disabled or in one of the 18, 24 or 30bit video modes. 106 * 107 * Other video-input-related pins require an explicit state in SCU90[5:4], e.g. 108 * W1 and U5: 109 * 110 * -----+---------+-----------+------------------------------+-----------+---------------+---------- 111 * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6 112 * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7 113 * -----+---------+-----------+------------------------------+-----------+---------------+---------- 114 * 115 * The examples of T5 and W1 are particularly fertile, as they also demonstrate 116 * that despite operating as part of the video input bus each signal needs to 117 * be enabled individually via it's own SCU84 (in the cases of T5 and W1) 118 * register bit. This is a little crazy if the bus doesn't have optional 119 * signals, but is used to decent effect with some of the UARTs where not all 120 * signals are required. However, this isn't done consistently - UART1 is 121 * enabled on a per-pin basis, and by contrast, all signals for UART6 are 122 * enabled by a single bit. 123 * 124 * Further, the high and low priority signals listed in the table above share 125 * a configuration bit. The VPI signals should operate in concert in a single 126 * function, but the UART signals should retain the ability to be configured 127 * independently. This pushes the implementation down the path of tagging a 128 * signal's expressions with the function they participate in, rather than 129 * defining masks affecting multiple signals per function. The latter approach 130 * fails in this instance where applying the configuration for the UART pin of 131 * interest will stomp on the state of other UART signals when disabling the 132 * VPI functions on the current pin. 133 * 134 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 135 * -----+------------+-----------+---------------------------+-----------+---------------+------------ 136 * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK 137 * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL 138 * -----+------------+-----------+---------------------------+-----------+---------------+------------ 139 * 140 * A12 demonstrates that the "Other" signal isn't always GPIO - in this case 141 * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO 142 * should be treated like any other signal type with full function expression 143 * requirements, and not assumed to be the default case. Separately, GPIOT0 and 144 * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all 145 * pins in the function's group to disable the higher-priority signals such 146 * that the signal for the function of interest is correctly enabled. 147 * 148 * Finally, three priority levels aren't always enough; the AST2500 brings with 149 * it 18 pins of five priority levels, however the 18 pins only use three of 150 * the five priority levels. 151 * 152 * Ultimately the requirement to control pins in the examples above drive the 153 * design: 154 * 155 * * Pins provide signals according to functions activated in the mux 156 * configuration 157 * 158 * * Pins provide up to five signal types in a priority order 159 * 160 * * For priorities levels defined on a pin, each priority provides one signal 161 * 162 * * Enabling lower priority signals requires higher priority signals be 163 * disabled 164 * 165 * * A function represents a set of signals; functions are distinct if their 166 * sets of signals are not equal 167 * 168 * * Signals participate in one or more functions 169 * 170 * * A function is described by an expression of one or more signal 171 * descriptors, which compare bit values in a register 172 * 173 * * A signal expression is the smallest set of signal descriptors whose 174 * comparisons must evaluate 'true' for a signal to be enabled on a pin. 175 * 176 * * A signal participating in a function is active on a pin if evaluating all 177 * signal descriptors in the pin's signal expression for the function yields 178 * a 'true' result 179 * 180 * * A signal at a given priority on a given pin is active if any of the 181 * functions in which the signal participates are active, and no higher 182 * priority signal on the pin is active 183 * 184 * * GPIO is configured per-pin 185 * 186 * And so: 187 * 188 * * To disable a signal, any function(s) activating the signal must be 189 * disabled 190 * 191 * * Each pin must know the signal expressions of functions in which it 192 * participates, for the purpose of enabling the Other function. This is done 193 * by deactivating all functions that activate higher priority signals on the 194 * pin. 195 * 196 * As a concrete example: 197 * 198 * * T5 provides three signals types: VPIDE, NDCD1 and GPIO 199 * 200 * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30 201 * 202 * * The NDCD1 signal participates in just its own NDCD1 function 203 * 204 * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least 205 * prioritised 206 * 207 * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24 208 * and VPI30 functions all be disabled 209 * 210 * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled 211 * to provide GPIOL6 212 * 213 * Considerations 214 * -------------- 215 * 216 * If pinctrl allows us to allocate a pin we can configure a function without 217 * concern for the function of already allocated pins, if pin groups are 218 * created with respect to the SoC functions in which they participate. This is 219 * intuitive, but it did not feel obvious from the bit/pin relationships. 220 * 221 * Conversely, failing to allocate all pins in a group indicates some bits (as 222 * well as pins) required for the group's configuration will already be in use, 223 * likely in a way that's inconsistent with the requirements of the failed 224 * group. 225 * 226 * Implementation 227 * -------------- 228 * 229 * Beyond the documentation below the various structures and helper macros that 230 * allow the implementation to hang together are defined. The macros are fairly 231 * dense, so below we walk through some raw examples of the configuration 232 * tables in an effort to clarify the concepts. 233 * 234 * The complexity of configuring the mux combined with the scale of the pins 235 * and functions was a concern, so the table design along with the macro jungle 236 * is an attempt to address it. The rough principles of the approach are: 237 * 238 * 1. Use a data-driven solution rather than embedding state into code 239 * 2. Minimise editing to the specifics of the given mux configuration 240 * 3. Detect as many errors as possible at compile time 241 * 242 * Addressing point 3 leads to naming of symbols in terms of the four 243 * properties associated with a given mux configuration: The pin, the signal, 244 * the group and the function. In this way copy/paste errors cause duplicate 245 * symbols to be defined, which prevents successful compilation. Failing to 246 * properly parent the tables leads to unused symbol warnings, and use of 247 * designated initialisers and additional warnings ensures that there are 248 * no override errors in the pin, group and function arrays. 249 * 250 * Addressing point 2 drives the development of the macro jungle, as it 251 * centralises the definition noise at the cost of taking some time to 252 * understand. 253 * 254 * Here's a complete, concrete "pre-processed" example of the table structures 255 * used to describe the D6 ball from the examples above: 256 * 257 * ``` 258 * static const struct aspeed_sig_desc sig_descs_MAC1LINK_MAC1LINK[] = { 259 * { 260 * .ip = ASPEED_IP_SCU, 261 * .reg = 0x80, 262 * .mask = BIT(0), 263 * .enable = 1, 264 * .disable = 0 265 * }, 266 * }; 267 * 268 * static const struct aspeed_sig_expr sig_expr_MAC1LINK_MAC1LINK = { 269 * .signal = "MAC1LINK", 270 * .function = "MAC1LINK", 271 * .ndescs = ARRAY_SIZE(sig_descs_MAC1LINK_MAC1LINK), 272 * .descs = &(sig_descs_MAC1LINK_MAC1LINK)[0], 273 * }; 274 * 275 * static const struct aspeed_sig_expr *sig_exprs_MAC1LINK_MAC1LINK[] = { 276 * &sig_expr_MAC1LINK_MAC1LINK, 277 * NULL, 278 * }; 279 * 280 * static const struct aspeed_sig_desc sig_descs_GPIOA0_GPIOA0[] = { }; 281 * 282 * static const struct aspeed_sig_expr sig_expr_GPIOA0_GPIOA0 = { 283 * .signal = "GPIOA0", 284 * .function = "GPIOA0", 285 * .ndescs = ARRAY_SIZE(sig_descs_GPIOA0_GPIOA0), 286 * .descs = &(sig_descs_GPIOA0_GPIOA0)[0], 287 * }; 288 * 289 * static const struct aspeed_sig_expr *sig_exprs_GPIOA0_GPIOA0[] = { 290 * &sig_expr_GPIOA0_GPIOA0, 291 * NULL 292 * }; 293 * 294 * static const struct aspeed_sig_expr **pin_exprs_0[] = { 295 * sig_exprs_MAC1LINK_MAC1LINK, 296 * sig_exprs_GPIOA0_GPIOA0, 297 * NULL 298 * }; 299 * 300 * static const struct aspeed_pin_desc pin_0 = { "0", (&pin_exprs_0[0]) }; 301 * static const int group_pins_MAC1LINK[] = { 0 }; 302 * static const char *func_groups_MAC1LINK[] = { "MAC1LINK" }; 303 * 304 * static struct pinctrl_pin_desc aspeed_g4_pins[] = { 305 * [0] = { .number = 0, .name = "D6", .drv_data = &pin_0 }, 306 * }; 307 * 308 * static const struct aspeed_pin_group aspeed_g4_groups[] = { 309 * { 310 * .name = "MAC1LINK", 311 * .pins = &(group_pins_MAC1LINK)[0], 312 * .npins = ARRAY_SIZE(group_pins_MAC1LINK), 313 * }, 314 * }; 315 * 316 * static const struct aspeed_pin_function aspeed_g4_functions[] = { 317 * { 318 * .name = "MAC1LINK", 319 * .groups = &func_groups_MAC1LINK[0], 320 * .ngroups = ARRAY_SIZE(func_groups_MAC1LINK), 321 * }, 322 * }; 323 * ``` 324 * 325 * At the end of the day much of the above code is compressed into the 326 * following two lines: 327 * 328 * ``` 329 * #define D6 0 330 * SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); 331 * ``` 332 * 333 * The two examples below show just the differences from the example above. 334 * 335 * Ball E18 demonstrates a function, EXTRST, that requires multiple descriptors 336 * be set for it to be muxed: 337 * 338 * ``` 339 * static const struct aspeed_sig_desc sig_descs_EXTRST_EXTRST[] = { 340 * { 341 * .ip = ASPEED_IP_SCU, 342 * .reg = 0x3C, 343 * .mask = BIT(3), 344 * .enable = 1, 345 * .disable = 0 346 * }, 347 * { 348 * .ip = ASPEED_IP_SCU, 349 * .reg = 0x80, 350 * .mask = BIT(15), 351 * .enable = 1, 352 * .disable = 0 353 * }, 354 * { 355 * .ip = ASPEED_IP_SCU, 356 * .reg = 0x90, 357 * .mask = BIT(31), 358 * .enable = 0, 359 * .disable = 1 360 * }, 361 * }; 362 * 363 * static const struct aspeed_sig_expr sig_expr_EXTRST_EXTRST = { 364 * .signal = "EXTRST", 365 * .function = "EXTRST", 366 * .ndescs = ARRAY_SIZE(sig_descs_EXTRST_EXTRST), 367 * .descs = &(sig_descs_EXTRST_EXTRST)[0], 368 * }; 369 * ... 370 * ``` 371 * 372 * For ball E19, we have multiple functions enabling a single signal, LPCRST#. 373 * The data structures look like: 374 * 375 * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRST[] = { 376 * { 377 * .ip = ASPEED_IP_SCU, 378 * .reg = 0x80, 379 * .mask = BIT(12), 380 * .enable = 1, 381 * .disable = 0 382 * }, 383 * }; 384 * 385 * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRST = { 386 * .signal = "LPCRST", 387 * .function = "LPCRST", 388 * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRST), 389 * .descs = &(sig_descs_LPCRST_LPCRST)[0], 390 * }; 391 * 392 * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRSTS[] = { 393 * { 394 * .ip = ASPEED_IP_SCU, 395 * .reg = 0x70, 396 * .mask = BIT(14), 397 * .enable = 1, 398 * .disable = 0 399 * }, 400 * }; 401 * 402 * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRSTS = { 403 * .signal = "LPCRST", 404 * .function = "LPCRSTS", 405 * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRSTS), 406 * .descs = &(sig_descs_LPCRST_LPCRSTS)[0], 407 * }; 408 * 409 * static const struct aspeed_sig_expr *sig_exprs_LPCRST_LPCRST[] = { 410 * &sig_expr_LPCRST_LPCRST, 411 * &sig_expr_LPCRST_LPCRSTS, 412 * NULL, 413 * }; 414 * ... 415 * ``` 416 * 417 * Both expressions listed in the sig_exprs_LPCRST_LPCRST array need to be set 418 * to disabled for the associated GPIO to be muxed. 419 * 420 */ 421 422 #define ASPEED_IP_SCU 0 423 #define ASPEED_IP_GFX 1 424 #define ASPEED_IP_LPC 2 425 #define ASPEED_NR_PINMUX_IPS 3 426 427 /** 428 * A signal descriptor, which describes the register, bits and the 429 * enable/disable values that should be compared or written. 430 * 431 * @ip: The IP block identifier, used as an index into the regmap array in 432 * struct aspeed_pinctrl_data 433 * @reg: The register offset with respect to the base address of the IP block 434 * @mask: The mask to apply to the register. The lowest set bit of the mask is 435 * used to derive the shift value. 436 * @enable: The value that enables the function. Value should be in the LSBs, 437 * not at the position of the mask. 438 * @disable: The value that disables the function. Value should be in the 439 * LSBs, not at the position of the mask. 440 */ 441 struct aspeed_sig_desc { 442 unsigned int ip; 443 unsigned int reg; 444 u32 mask; 445 u32 enable; 446 u32 disable; 447 }; 448 449 /** 450 * Describes a signal expression. The expression is evaluated by ANDing the 451 * evaluation of the descriptors. 452 * 453 * @signal: The signal name for the priority level on the pin. If the signal 454 * type is GPIO, then the signal name must begin with the string 455 * "GPIO", e.g. GPIOA0, GPIOT4 etc. 456 * @function: The name of the function the signal participates in for the 457 * associated expression 458 * @ndescs: The number of signal descriptors in the expression 459 * @descs: Pointer to an array of signal descriptors that comprise the 460 * function expression 461 */ 462 struct aspeed_sig_expr { 463 const char *signal; 464 const char *function; 465 int ndescs; 466 const struct aspeed_sig_desc *descs; 467 }; 468 469 /** 470 * A struct capturing the list of expressions enabling signals at each priority 471 * for a given pin. The signal configuration for a priority level is evaluated 472 * by ORing the evaluation of the signal expressions in the respective 473 * priority's list. 474 * 475 * @name: A name for the pin 476 * @prios: A pointer to an array of expression list pointers 477 * 478 */ 479 struct aspeed_pin_desc { 480 const char *name; 481 const struct aspeed_sig_expr ***prios; 482 }; 483 484 /* Macro hell */ 485 486 #define SIG_DESC_IP_BIT(ip, reg, idx, val) \ 487 { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } 488 489 /** 490 * Short-hand macro for describing an SCU descriptor enabled by the state of 491 * one bit. The disable value is derived. 492 * 493 * @reg: The signal's associated register, offset from base 494 * @idx: The signal's bit index in the register 495 * @val: The value (0 or 1) that enables the function 496 */ 497 #define SIG_DESC_BIT(reg, idx, val) \ 498 SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) 499 500 #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1) 501 502 /** 503 * A further short-hand macro expanding to an SCU descriptor enabled by a set 504 * bit. 505 * 506 * @reg: The register, offset from base 507 * @idx: The bit index in the register 508 */ 509 #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) 510 511 #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func 512 #define SIG_DESC_LIST_DECL(sig, func, ...) \ 513 static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \ 514 { __VA_ARGS__ } 515 516 #define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func 517 #define SIG_EXPR_DECL_(sig, func) \ 518 static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \ 519 { \ 520 .signal = #sig, \ 521 .function = #func, \ 522 .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \ 523 .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \ 524 } 525 526 /** 527 * Declare a signal expression. 528 * 529 * @sig: A macro symbol name for the signal (is subjected to stringification 530 * and token pasting) 531 * @func: The function in which the signal is participating 532 * @...: Signal descriptors that define the signal expression 533 * 534 * For example, the following declares the ROMD8 signal for the ROM16 function: 535 * 536 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); 537 * 538 * And with multiple signal descriptors: 539 * 540 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), 541 * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); 542 */ 543 #define SIG_EXPR_DECL(sig, func, ...) \ 544 SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ 545 SIG_EXPR_DECL_(sig, func) 546 547 /** 548 * Declare a pointer to a signal expression 549 * 550 * @sig: The macro symbol name for the signal (subjected to token pasting) 551 * @func: The macro symbol name for the function (subjected to token pasting) 552 */ 553 #define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func)) 554 555 #define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig 556 557 /** 558 * Declare a signal expression list for reference in a struct aspeed_pin_prio. 559 * 560 * @sig: A macro symbol name for the signal (is subjected to token pasting) 561 * @...: Signal expression structure pointers (use SIG_EXPR_PTR()) 562 * 563 * For example, the 16-bit ROM bus can be enabled by one of two possible signal 564 * expressions: 565 * 566 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); 567 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), 568 * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); 569 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), 570 * SIG_EXPR_PTR(ROMD8, ROM16S)); 571 */ 572 #define SIG_EXPR_LIST_DECL(sig, ...) \ 573 static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \ 574 { __VA_ARGS__, NULL } 575 576 /** 577 * A short-hand macro for declaring a function expression and an expression 578 * list with a single function. 579 * 580 * @func: A macro symbol name for the function (is subjected to token pasting) 581 * @...: Function descriptors that define the function expression 582 * 583 * For example, signal NCTS6 participates in its own function with one group: 584 * 585 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); 586 */ 587 #define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \ 588 SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ 589 SIG_EXPR_DECL_(sig, func); \ 590 SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func)) 591 592 #define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \ 593 SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1)) 594 595 #define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0]) 596 597 #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin 598 #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) 599 #define PIN_SYM(pin) pin_ ## pin 600 601 #define MS_PIN_DECL_(pin, ...) \ 602 static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \ 603 { __VA_ARGS__, NULL }; \ 604 static const struct aspeed_pin_desc PIN_SYM(pin) = \ 605 { #pin, PIN_EXPRS_PTR(pin) } 606 607 /** 608 * Declare a multi-signal pin 609 * 610 * @pin: The pin number 611 * @other: Macro name for "other" functionality (subjected to stringification) 612 * @high: Macro name for the highest priority signal functions 613 * @low: Macro name for the low signal functions 614 * 615 * For example: 616 * 617 * #define A8 56 618 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); 619 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), 620 * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); 621 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), 622 * SIG_EXPR_PTR(ROMD8, ROM16S)); 623 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); 624 * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); 625 */ 626 #define MS_PIN_DECL(pin, other, high, low) \ 627 SIG_EXPR_LIST_DECL_SINGLE(other, other); \ 628 MS_PIN_DECL_(pin, \ 629 SIG_EXPR_LIST_PTR(high), \ 630 SIG_EXPR_LIST_PTR(low), \ 631 SIG_EXPR_LIST_PTR(other)) 632 633 #define PIN_GROUP_SYM(func) pins_ ## func 634 #define FUNC_GROUP_SYM(func) groups_ ## func 635 #define FUNC_GROUP_DECL(func, ...) \ 636 static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \ 637 static const char *FUNC_GROUP_SYM(func)[] = { #func } 638 639 /** 640 * Declare a single signal pin 641 * 642 * @pin: The pin number 643 * @other: Macro name for "other" functionality (subjected to stringification) 644 * @sig: Macro name for the signal (subjected to stringification) 645 * 646 * For example: 647 * 648 * #define E3 80 649 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); 650 * SS_PIN_DECL(E3, GPIOK0, SCL5); 651 */ 652 #define SS_PIN_DECL(pin, other, sig) \ 653 SIG_EXPR_LIST_DECL_SINGLE(other, other); \ 654 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)) 655 656 /** 657 * Single signal, single function pin declaration 658 * 659 * @pin: The pin number 660 * @other: Macro name for "other" functionality (subjected to stringification) 661 * @sig: Macro name for the signal (subjected to stringification) 662 * @...: Signal descriptors that define the function expression 663 * 664 * For example: 665 * 666 * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); 667 */ 668 #define SSSF_PIN_DECL(pin, other, sig, ...) \ 669 SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \ 670 SIG_EXPR_LIST_DECL_SINGLE(other, other); \ 671 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \ 672 FUNC_GROUP_DECL(sig, pin) 673 674 #define GPIO_PIN_DECL(pin, gpio) \ 675 SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \ 676 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) 677 678 struct aspeed_pin_group { 679 const char *name; 680 const unsigned int *pins; 681 const unsigned int npins; 682 }; 683 684 #define ASPEED_PINCTRL_GROUP(name_) { \ 685 .name = #name_, \ 686 .pins = &(PIN_GROUP_SYM(name_))[0], \ 687 .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \ 688 } 689 690 struct aspeed_pin_function { 691 const char *name; 692 const char *const *groups; 693 unsigned int ngroups; 694 }; 695 696 #define ASPEED_PINCTRL_FUNC(name_, ...) { \ 697 .name = #name_, \ 698 .groups = &FUNC_GROUP_SYM(name_)[0], \ 699 .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \ 700 } 701 702 struct aspeed_pinmux_data; 703 704 struct aspeed_pinmux_ops { 705 int (*set)(const struct aspeed_pinmux_data *ctx, 706 const struct aspeed_sig_expr *expr, bool enabled); 707 }; 708 709 struct aspeed_pinmux_data { 710 struct regmap *maps[ASPEED_NR_PINMUX_IPS]; 711 712 const struct aspeed_pinmux_ops *ops; 713 714 const struct aspeed_pin_group *groups; 715 const unsigned int ngroups; 716 717 const struct aspeed_pin_function *functions; 718 const unsigned int nfunctions; 719 }; 720 721 int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled, 722 struct regmap *map); 723 724 int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx, 725 const struct aspeed_sig_expr *expr, 726 bool enabled); 727 728 static inline int aspeed_sig_expr_set(const struct aspeed_pinmux_data *ctx, 729 const struct aspeed_sig_expr *expr, 730 bool enabled) 731 { 732 return ctx->ops->set(ctx, expr, enabled); 733 } 734 735 #endif /* ASPEED_PINMUX_H */ 736