12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 24d3d0e42SAndrew Jeffery /* 34d3d0e42SAndrew Jeffery * Copyright (C) 2016 IBM Corp. 44d3d0e42SAndrew Jeffery */ 54d3d0e42SAndrew Jeffery 64d3d0e42SAndrew Jeffery #ifndef PINCTRL_ASPEED 74d3d0e42SAndrew Jeffery #define PINCTRL_ASPEED 84d3d0e42SAndrew Jeffery 94d3d0e42SAndrew Jeffery #include <linux/pinctrl/pinctrl.h> 104d3d0e42SAndrew Jeffery #include <linux/pinctrl/pinmux.h> 114d3d0e42SAndrew Jeffery #include <linux/pinctrl/pinconf.h> 124d3d0e42SAndrew Jeffery #include <linux/pinctrl/pinconf-generic.h> 134d3d0e42SAndrew Jeffery #include <linux/regmap.h> 144d3d0e42SAndrew Jeffery 154d3d0e42SAndrew Jeffery /* 164d3d0e42SAndrew Jeffery * The ASPEED SoCs provide typically more than 200 pins for GPIO and other 174d3d0e42SAndrew Jeffery * functions. The SoC function enabled on a pin is determined on a priority 184d3d0e42SAndrew Jeffery * basis where a given pin can provide a number of different signal types. 194d3d0e42SAndrew Jeffery * 204d3d0e42SAndrew Jeffery * The signal active on a pin is described by both a priority level and 214d3d0e42SAndrew Jeffery * compound logical expressions involving multiple operators, registers and 224d3d0e42SAndrew Jeffery * bits. Some difficulty arises as the pin's function bit masks for each 234d3d0e42SAndrew Jeffery * priority level are frequently not the same (i.e. cannot just flip a bit to 244d3d0e42SAndrew Jeffery * change from a high to low priority signal), or even in the same register. 254d3d0e42SAndrew Jeffery * Further, not all signals can be unmuxed, as some expressions depend on 264d3d0e42SAndrew Jeffery * values in the hardware strapping register (which is treated as read-only). 274d3d0e42SAndrew Jeffery * 284d3d0e42SAndrew Jeffery * SoC Multi-function Pin Expression Examples 294d3d0e42SAndrew Jeffery * ------------------------------------------ 304d3d0e42SAndrew Jeffery * 314d3d0e42SAndrew Jeffery * Here are some sample mux configurations from the AST2400 and AST2500 324d3d0e42SAndrew Jeffery * datasheets to illustrate the corner cases, roughly in order of least to most 334d3d0e42SAndrew Jeffery * corner. The signal priorities are in decending order from P0 (highest). 344d3d0e42SAndrew Jeffery * 354d3d0e42SAndrew Jeffery * D6 is a pin with a single function (beside GPIO); a high priority signal 364d3d0e42SAndrew Jeffery * that participates in one function: 374d3d0e42SAndrew Jeffery * 384d3d0e42SAndrew Jeffery * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 394d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 404d3d0e42SAndrew Jeffery * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0 414d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 424d3d0e42SAndrew Jeffery * 434d3d0e42SAndrew Jeffery * C5 is a multi-signal pin (high and low priority signals). Here we touch 444d3d0e42SAndrew Jeffery * different registers for the different functions that enable each signal: 454d3d0e42SAndrew Jeffery * 464d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 474d3d0e42SAndrew Jeffery * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4 484d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 494d3d0e42SAndrew Jeffery * 504d3d0e42SAndrew Jeffery * E19 is a single-signal pin with two functions that influence the active 514d3d0e42SAndrew Jeffery * signal. In this case both bits have the same meaning - enable a dedicated 524d3d0e42SAndrew Jeffery * LPC reset pin. However it's not always the case that the bits in the 534d3d0e42SAndrew Jeffery * OR-relationship have the same meaning. 544d3d0e42SAndrew Jeffery * 554d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 564d3d0e42SAndrew Jeffery * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4 574d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------+-----------+---------------+---------- 584d3d0e42SAndrew Jeffery * 594d3d0e42SAndrew Jeffery * For example, pin B19 has a low-priority signal that's enabled by two 604d3d0e42SAndrew Jeffery * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI 614d3d0e42SAndrew Jeffery * bit in the STRAP register. The ACPI bit configures signals on pins in 624d3d0e42SAndrew Jeffery * addition to B19. Both of the low priority functions as well as the high 634d3d0e42SAndrew Jeffery * priority function must be disabled for GPIOF1 to be used. 644d3d0e42SAndrew Jeffery * 654d3d0e42SAndrew Jeffery * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 664d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 674d3d0e42SAndrew Jeffery * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1 684d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 694d3d0e42SAndrew Jeffery * 704d3d0e42SAndrew Jeffery * For pin E18, the SoC ANDs the expected state of three bits to determine the 714d3d0e42SAndrew Jeffery * pin's active signal: 724d3d0e42SAndrew Jeffery * 734d3d0e42SAndrew Jeffery * * SCU3C[3]: Enable external SOC reset function 744d3d0e42SAndrew Jeffery * * SCU80[15]: Enable SPICS1# or EXTRST# function pin 754d3d0e42SAndrew Jeffery * * SCU90[31]: Select SPI interface CS# output 764d3d0e42SAndrew Jeffery * 774d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 784d3d0e42SAndrew Jeffery * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7 794d3d0e42SAndrew Jeffery * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+---------- 804d3d0e42SAndrew Jeffery * 814d3d0e42SAndrew Jeffery * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for 824d3d0e42SAndrew Jeffery * selecting the signals on pin E18) 834d3d0e42SAndrew Jeffery * 844d3d0e42SAndrew Jeffery * Pin T5 is a multi-signal pin with a more complex configuration: 854d3d0e42SAndrew Jeffery * 864d3d0e42SAndrew Jeffery * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 874d3d0e42SAndrew Jeffery * -----+---------+-----------+------------------------------+-----------+---------------+---------- 884d3d0e42SAndrew Jeffery * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1 894d3d0e42SAndrew Jeffery * -----+---------+-----------+------------------------------+-----------+---------------+---------- 904d3d0e42SAndrew Jeffery * 914d3d0e42SAndrew Jeffery * The high priority signal configuration is best thought of in terms of its 924d3d0e42SAndrew Jeffery * exploded form, with reference to the SCU90[5:4] bits: 934d3d0e42SAndrew Jeffery * 944d3d0e42SAndrew Jeffery * * SCU90[5:4]=00: disable 954d3d0e42SAndrew Jeffery * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode. 964d3d0e42SAndrew Jeffery * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode. 974d3d0e42SAndrew Jeffery * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode. 984d3d0e42SAndrew Jeffery * 994d3d0e42SAndrew Jeffery * Re-writing: 1004d3d0e42SAndrew Jeffery * 1014d3d0e42SAndrew Jeffery * -----+---------+-----------+------------------------------+-----------+---------------+---------- 1024d3d0e42SAndrew Jeffery * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1 1034d3d0e42SAndrew Jeffery * | (SCU90[5:4]=2 & SCU84[17]=1) 1044d3d0e42SAndrew Jeffery * | (SCU90[5:4]=3 & SCU84[17]=1) 1054d3d0e42SAndrew Jeffery * -----+---------+-----------+------------------------------+-----------+---------------+---------- 1064d3d0e42SAndrew Jeffery * 1074d3d0e42SAndrew Jeffery * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE 1084d3d0e42SAndrew Jeffery * function pin", where the signal itself is determined by whether SCU94[5:4] 1094d3d0e42SAndrew Jeffery * is disabled or in one of the 18, 24 or 30bit video modes. 1104d3d0e42SAndrew Jeffery * 1114d3d0e42SAndrew Jeffery * Other video-input-related pins require an explicit state in SCU90[5:4], e.g. 1124d3d0e42SAndrew Jeffery * W1 and U5: 1134d3d0e42SAndrew Jeffery * 1144d3d0e42SAndrew Jeffery * -----+---------+-----------+------------------------------+-----------+---------------+---------- 1154d3d0e42SAndrew Jeffery * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6 1164d3d0e42SAndrew Jeffery * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7 1174d3d0e42SAndrew Jeffery * -----+---------+-----------+------------------------------+-----------+---------------+---------- 1184d3d0e42SAndrew Jeffery * 1194d3d0e42SAndrew Jeffery * The examples of T5 and W1 are particularly fertile, as they also demonstrate 1204d3d0e42SAndrew Jeffery * that despite operating as part of the video input bus each signal needs to 1214d3d0e42SAndrew Jeffery * be enabled individually via it's own SCU84 (in the cases of T5 and W1) 1224d3d0e42SAndrew Jeffery * register bit. This is a little crazy if the bus doesn't have optional 1234d3d0e42SAndrew Jeffery * signals, but is used to decent effect with some of the UARTs where not all 1244d3d0e42SAndrew Jeffery * signals are required. However, this isn't done consistently - UART1 is 1254d3d0e42SAndrew Jeffery * enabled on a per-pin basis, and by contrast, all signals for UART6 are 1264d3d0e42SAndrew Jeffery * enabled by a single bit. 1274d3d0e42SAndrew Jeffery * 1284d3d0e42SAndrew Jeffery * Further, the high and low priority signals listed in the table above share 1294d3d0e42SAndrew Jeffery * a configuration bit. The VPI signals should operate in concert in a single 1304d3d0e42SAndrew Jeffery * function, but the UART signals should retain the ability to be configured 1314d3d0e42SAndrew Jeffery * independently. This pushes the implementation down the path of tagging a 1324d3d0e42SAndrew Jeffery * signal's expressions with the function they participate in, rather than 1334d3d0e42SAndrew Jeffery * defining masks affecting multiple signals per function. The latter approach 1344d3d0e42SAndrew Jeffery * fails in this instance where applying the configuration for the UART pin of 1354d3d0e42SAndrew Jeffery * interest will stomp on the state of other UART signals when disabling the 1364d3d0e42SAndrew Jeffery * VPI functions on the current pin. 1374d3d0e42SAndrew Jeffery * 1384d3d0e42SAndrew Jeffery * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other 1394d3d0e42SAndrew Jeffery * -----+------------+-----------+---------------------------+-----------+---------------+------------ 1404d3d0e42SAndrew Jeffery * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK 1414d3d0e42SAndrew Jeffery * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL 1424d3d0e42SAndrew Jeffery * -----+------------+-----------+---------------------------+-----------+---------------+------------ 1434d3d0e42SAndrew Jeffery * 1444d3d0e42SAndrew Jeffery * A12 demonstrates that the "Other" signal isn't always GPIO - in this case 1454d3d0e42SAndrew Jeffery * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO 1464d3d0e42SAndrew Jeffery * should be treated like any other signal type with full function expression 1474d3d0e42SAndrew Jeffery * requirements, and not assumed to be the default case. Separately, GPIOT0 and 1484d3d0e42SAndrew Jeffery * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all 1494d3d0e42SAndrew Jeffery * pins in the function's group to disable the higher-priority signals such 1504d3d0e42SAndrew Jeffery * that the signal for the function of interest is correctly enabled. 1514d3d0e42SAndrew Jeffery * 1524d3d0e42SAndrew Jeffery * Finally, three priority levels aren't always enough; the AST2500 brings with 1534d3d0e42SAndrew Jeffery * it 18 pins of five priority levels, however the 18 pins only use three of 1544d3d0e42SAndrew Jeffery * the five priority levels. 1554d3d0e42SAndrew Jeffery * 1564d3d0e42SAndrew Jeffery * Ultimately the requirement to control pins in the examples above drive the 1574d3d0e42SAndrew Jeffery * design: 1584d3d0e42SAndrew Jeffery * 1594d3d0e42SAndrew Jeffery * * Pins provide signals according to functions activated in the mux 1604d3d0e42SAndrew Jeffery * configuration 1614d3d0e42SAndrew Jeffery * 1624d3d0e42SAndrew Jeffery * * Pins provide up to five signal types in a priority order 1634d3d0e42SAndrew Jeffery * 1644d3d0e42SAndrew Jeffery * * For priorities levels defined on a pin, each priority provides one signal 1654d3d0e42SAndrew Jeffery * 1664d3d0e42SAndrew Jeffery * * Enabling lower priority signals requires higher priority signals be 1674d3d0e42SAndrew Jeffery * disabled 1684d3d0e42SAndrew Jeffery * 1694d3d0e42SAndrew Jeffery * * A function represents a set of signals; functions are distinct if their 1704d3d0e42SAndrew Jeffery * sets of signals are not equal 1714d3d0e42SAndrew Jeffery * 1724d3d0e42SAndrew Jeffery * * Signals participate in one or more functions 1734d3d0e42SAndrew Jeffery * 1744d3d0e42SAndrew Jeffery * * A function is described by an expression of one or more signal 1754d3d0e42SAndrew Jeffery * descriptors, which compare bit values in a register 1764d3d0e42SAndrew Jeffery * 1774d3d0e42SAndrew Jeffery * * A signal expression is the smallest set of signal descriptors whose 1784d3d0e42SAndrew Jeffery * comparisons must evaluate 'true' for a signal to be enabled on a pin. 1794d3d0e42SAndrew Jeffery * 1804d3d0e42SAndrew Jeffery * * A function's signal is active on a pin if evaluating all signal 1814d3d0e42SAndrew Jeffery * descriptors in the pin's signal expression for the function yields a 'true' 1824d3d0e42SAndrew Jeffery * result 1834d3d0e42SAndrew Jeffery * 1844d3d0e42SAndrew Jeffery * * A signal at a given priority on a given pin is active if any of the 1854d3d0e42SAndrew Jeffery * functions in which the signal participates are active, and no higher 1864d3d0e42SAndrew Jeffery * priority signal on the pin is active 1874d3d0e42SAndrew Jeffery * 1884d3d0e42SAndrew Jeffery * * GPIO is configured per-pin 1894d3d0e42SAndrew Jeffery * 1904d3d0e42SAndrew Jeffery * And so: 1914d3d0e42SAndrew Jeffery * 1924d3d0e42SAndrew Jeffery * * To disable a signal, any function(s) activating the signal must be 1934d3d0e42SAndrew Jeffery * disabled 1944d3d0e42SAndrew Jeffery * 1954d3d0e42SAndrew Jeffery * * Each pin must know the signal expressions of functions in which it 1964d3d0e42SAndrew Jeffery * participates, for the purpose of enabling the Other function. This is done 1974d3d0e42SAndrew Jeffery * by deactivating all functions that activate higher priority signals on the 1984d3d0e42SAndrew Jeffery * pin. 1994d3d0e42SAndrew Jeffery * 2004d3d0e42SAndrew Jeffery * As a concrete example: 2014d3d0e42SAndrew Jeffery * 2024d3d0e42SAndrew Jeffery * * T5 provides three signals types: VPIDE, NDCD1 and GPIO 2034d3d0e42SAndrew Jeffery * 2044d3d0e42SAndrew Jeffery * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30 2054d3d0e42SAndrew Jeffery * 2064d3d0e42SAndrew Jeffery * * The NDCD1 signal participates in just its own NDCD1 function 2074d3d0e42SAndrew Jeffery * 2084d3d0e42SAndrew Jeffery * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least 2094d3d0e42SAndrew Jeffery * prioritised 2104d3d0e42SAndrew Jeffery * 2114d3d0e42SAndrew Jeffery * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24 2124d3d0e42SAndrew Jeffery * and VPI30 functions all be disabled 2134d3d0e42SAndrew Jeffery * 2144d3d0e42SAndrew Jeffery * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled 2154d3d0e42SAndrew Jeffery * to provide GPIOL6 2164d3d0e42SAndrew Jeffery * 2174d3d0e42SAndrew Jeffery * Considerations 2184d3d0e42SAndrew Jeffery * -------------- 2194d3d0e42SAndrew Jeffery * 2204d3d0e42SAndrew Jeffery * If pinctrl allows us to allocate a pin we can configure a function without 2214d3d0e42SAndrew Jeffery * concern for the function of already allocated pins, if pin groups are 2224d3d0e42SAndrew Jeffery * created with respect to the SoC functions in which they participate. This is 2234d3d0e42SAndrew Jeffery * intuitive, but it did not feel obvious from the bit/pin relationships. 2244d3d0e42SAndrew Jeffery * 2254d3d0e42SAndrew Jeffery * Conversely, failing to allocate all pins in a group indicates some bits (as 2264d3d0e42SAndrew Jeffery * well as pins) required for the group's configuration will already be in use, 2274d3d0e42SAndrew Jeffery * likely in a way that's inconsistent with the requirements of the failed 2284d3d0e42SAndrew Jeffery * group. 2294d3d0e42SAndrew Jeffery */ 2304d3d0e42SAndrew Jeffery 2317d29ed88SAndrew Jeffery #define ASPEED_IP_SCU 0 2327d29ed88SAndrew Jeffery #define ASPEED_IP_GFX 1 2337d29ed88SAndrew Jeffery #define ASPEED_IP_LPC 2 2347d29ed88SAndrew Jeffery #define ASPEED_NR_PINMUX_IPS 3 2357d29ed88SAndrew Jeffery 2364d3d0e42SAndrew Jeffery /* 2374d3d0e42SAndrew Jeffery * The "Multi-function Pins Mapping and Control" table in the SoC datasheet 2384d3d0e42SAndrew Jeffery * references registers by the device/offset mnemonic. The register macros 2394d3d0e42SAndrew Jeffery * below are named the same way to ease transcription and verification (as 2404d3d0e42SAndrew Jeffery * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions 2414d3d0e42SAndrew Jeffery * reference registers beyond those dedicated to pinmux, such as the system 2424d3d0e42SAndrew Jeffery * reset control and MAC clock configuration registers. The AST2500 goes a step 2434d3d0e42SAndrew Jeffery * further and references registers in the graphics IP block, but that isn't 2444d3d0e42SAndrew Jeffery * handled yet. 2454d3d0e42SAndrew Jeffery */ 2464d3d0e42SAndrew Jeffery #define SCU2C 0x2C /* Misc. Control Register */ 2474d3d0e42SAndrew Jeffery #define SCU3C 0x3C /* System Reset Control/Status Register */ 2484d3d0e42SAndrew Jeffery #define SCU48 0x48 /* MAC Interface Clock Delay Setting */ 2494d3d0e42SAndrew Jeffery #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ 2501865af21SYong Li #define HW_REVISION_ID 0x7C /* Silicon revision ID register */ 2514d3d0e42SAndrew Jeffery #define SCU80 0x80 /* Multi-function Pin Control #1 */ 2524d3d0e42SAndrew Jeffery #define SCU84 0x84 /* Multi-function Pin Control #2 */ 2534d3d0e42SAndrew Jeffery #define SCU88 0x88 /* Multi-function Pin Control #3 */ 2544d3d0e42SAndrew Jeffery #define SCU8C 0x8C /* Multi-function Pin Control #4 */ 2554d3d0e42SAndrew Jeffery #define SCU90 0x90 /* Multi-function Pin Control #5 */ 2564d3d0e42SAndrew Jeffery #define SCU94 0x94 /* Multi-function Pin Control #6 */ 2574d3d0e42SAndrew Jeffery #define SCUA0 0xA0 /* Multi-function Pin Control #7 */ 2584d3d0e42SAndrew Jeffery #define SCUA4 0xA4 /* Multi-function Pin Control #8 */ 2594d3d0e42SAndrew Jeffery #define SCUA8 0xA8 /* Multi-function Pin Control #9 */ 260f1337856SAndrew Jeffery #define SCUAC 0xAC /* Multi-function Pin Control #10 */ 2614d3d0e42SAndrew Jeffery #define HW_STRAP2 0xD0 /* Strapping */ 2624d3d0e42SAndrew Jeffery 2634d3d0e42SAndrew Jeffery /** 2644d3d0e42SAndrew Jeffery * A signal descriptor, which describes the register, bits and the 2654d3d0e42SAndrew Jeffery * enable/disable values that should be compared or written. 2664d3d0e42SAndrew Jeffery * 2677d29ed88SAndrew Jeffery * @ip: The IP block identifier, used as an index into the regmap array in 2687d29ed88SAndrew Jeffery * struct aspeed_pinctrl_data 2697d29ed88SAndrew Jeffery * @reg: The register offset with respect to the base address of the IP block 2704d3d0e42SAndrew Jeffery * @mask: The mask to apply to the register. The lowest set bit of the mask is 2714d3d0e42SAndrew Jeffery * used to derive the shift value. 2724d3d0e42SAndrew Jeffery * @enable: The value that enables the function. Value should be in the LSBs, 2734d3d0e42SAndrew Jeffery * not at the position of the mask. 2744d3d0e42SAndrew Jeffery * @disable: The value that disables the function. Value should be in the 2754d3d0e42SAndrew Jeffery * LSBs, not at the position of the mask. 2764d3d0e42SAndrew Jeffery */ 2774d3d0e42SAndrew Jeffery struct aspeed_sig_desc { 2787d29ed88SAndrew Jeffery unsigned int ip; 2794d3d0e42SAndrew Jeffery unsigned int reg; 2804d3d0e42SAndrew Jeffery u32 mask; 2814d3d0e42SAndrew Jeffery u32 enable; 2824d3d0e42SAndrew Jeffery u32 disable; 2834d3d0e42SAndrew Jeffery }; 2844d3d0e42SAndrew Jeffery 2854d3d0e42SAndrew Jeffery /** 2864d3d0e42SAndrew Jeffery * Describes a signal expression. The expression is evaluated by ANDing the 2874d3d0e42SAndrew Jeffery * evaluation of the descriptors. 2884d3d0e42SAndrew Jeffery * 2894d3d0e42SAndrew Jeffery * @signal: The signal name for the priority level on the pin. If the signal 2904d3d0e42SAndrew Jeffery * type is GPIO, then the signal name must begin with the string 2914d3d0e42SAndrew Jeffery * "GPIO", e.g. GPIOA0, GPIOT4 etc. 2924d3d0e42SAndrew Jeffery * @function: The name of the function the signal participates in for the 2934d3d0e42SAndrew Jeffery * associated expression 2944d3d0e42SAndrew Jeffery * @ndescs: The number of signal descriptors in the expression 2954d3d0e42SAndrew Jeffery * @descs: Pointer to an array of signal descriptors that comprise the 2964d3d0e42SAndrew Jeffery * function expression 2974d3d0e42SAndrew Jeffery */ 2984d3d0e42SAndrew Jeffery struct aspeed_sig_expr { 2994d3d0e42SAndrew Jeffery const char *signal; 3004d3d0e42SAndrew Jeffery const char *function; 3014d3d0e42SAndrew Jeffery int ndescs; 3024d3d0e42SAndrew Jeffery const struct aspeed_sig_desc *descs; 3034d3d0e42SAndrew Jeffery }; 3044d3d0e42SAndrew Jeffery 3054d3d0e42SAndrew Jeffery /** 3064d3d0e42SAndrew Jeffery * A struct capturing the list of expressions enabling signals at each priority 3074d3d0e42SAndrew Jeffery * for a given pin. The signal configuration for a priority level is evaluated 3084d3d0e42SAndrew Jeffery * by ORing the evaluation of the signal expressions in the respective 3094d3d0e42SAndrew Jeffery * priority's list. 3104d3d0e42SAndrew Jeffery * 3114d3d0e42SAndrew Jeffery * @name: A name for the pin 3124d3d0e42SAndrew Jeffery * @prios: A pointer to an array of expression list pointers 3134d3d0e42SAndrew Jeffery * 3144d3d0e42SAndrew Jeffery */ 3154d3d0e42SAndrew Jeffery struct aspeed_pin_desc { 3164d3d0e42SAndrew Jeffery const char *name; 3174d3d0e42SAndrew Jeffery const struct aspeed_sig_expr ***prios; 3184d3d0e42SAndrew Jeffery }; 3194d3d0e42SAndrew Jeffery 3204d3d0e42SAndrew Jeffery /* Macro hell */ 3214d3d0e42SAndrew Jeffery 3227d29ed88SAndrew Jeffery #define SIG_DESC_IP_BIT(ip, reg, idx, val) \ 3237d29ed88SAndrew Jeffery { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } 3247d29ed88SAndrew Jeffery 3254d3d0e42SAndrew Jeffery /** 3267d29ed88SAndrew Jeffery * Short-hand macro for describing an SCU descriptor enabled by the state of 3277d29ed88SAndrew Jeffery * one bit. The disable value is derived. 3284d3d0e42SAndrew Jeffery * 3294d3d0e42SAndrew Jeffery * @reg: The signal's associated register, offset from base 3304d3d0e42SAndrew Jeffery * @idx: The signal's bit index in the register 3314d3d0e42SAndrew Jeffery * @val: The value (0 or 1) that enables the function 3324d3d0e42SAndrew Jeffery */ 3334d3d0e42SAndrew Jeffery #define SIG_DESC_BIT(reg, idx, val) \ 3347d29ed88SAndrew Jeffery SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) 3357d29ed88SAndrew Jeffery 3367d29ed88SAndrew Jeffery #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1) 3374d3d0e42SAndrew Jeffery 3384d3d0e42SAndrew Jeffery /** 3397d29ed88SAndrew Jeffery * A further short-hand macro expanding to an SCU descriptor enabled by a set 3407d29ed88SAndrew Jeffery * bit. 3414d3d0e42SAndrew Jeffery * 3427d29ed88SAndrew Jeffery * @reg: The register, offset from base 3437d29ed88SAndrew Jeffery * @idx: The bit index in the register 3444d3d0e42SAndrew Jeffery */ 3457d29ed88SAndrew Jeffery #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) 3464d3d0e42SAndrew Jeffery 3474d3d0e42SAndrew Jeffery #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func 3484d3d0e42SAndrew Jeffery #define SIG_DESC_LIST_DECL(sig, func, ...) \ 3494d3d0e42SAndrew Jeffery static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \ 3504d3d0e42SAndrew Jeffery { __VA_ARGS__ } 3514d3d0e42SAndrew Jeffery 3524d3d0e42SAndrew Jeffery #define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func 3534d3d0e42SAndrew Jeffery #define SIG_EXPR_DECL_(sig, func) \ 3544d3d0e42SAndrew Jeffery static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \ 3554d3d0e42SAndrew Jeffery { \ 3564d3d0e42SAndrew Jeffery .signal = #sig, \ 3574d3d0e42SAndrew Jeffery .function = #func, \ 3584d3d0e42SAndrew Jeffery .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \ 3594d3d0e42SAndrew Jeffery .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \ 3604d3d0e42SAndrew Jeffery } 3614d3d0e42SAndrew Jeffery 3624d3d0e42SAndrew Jeffery /** 3634d3d0e42SAndrew Jeffery * Declare a signal expression. 3644d3d0e42SAndrew Jeffery * 3654d3d0e42SAndrew Jeffery * @sig: A macro symbol name for the signal (is subjected to stringification 3664d3d0e42SAndrew Jeffery * and token pasting) 3674d3d0e42SAndrew Jeffery * @func: The function in which the signal is participating 3684d3d0e42SAndrew Jeffery * @...: Signal descriptors that define the signal expression 3694d3d0e42SAndrew Jeffery * 3704d3d0e42SAndrew Jeffery * For example, the following declares the ROMD8 signal for the ROM16 function: 3714d3d0e42SAndrew Jeffery * 3724d3d0e42SAndrew Jeffery * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); 3734d3d0e42SAndrew Jeffery * 3744d3d0e42SAndrew Jeffery * And with multiple signal descriptors: 3754d3d0e42SAndrew Jeffery * 3764d3d0e42SAndrew Jeffery * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), 3774d3d0e42SAndrew Jeffery * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); 3784d3d0e42SAndrew Jeffery */ 3794d3d0e42SAndrew Jeffery #define SIG_EXPR_DECL(sig, func, ...) \ 3804d3d0e42SAndrew Jeffery SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ 3814d3d0e42SAndrew Jeffery SIG_EXPR_DECL_(sig, func) 3824d3d0e42SAndrew Jeffery 3834d3d0e42SAndrew Jeffery /** 3844d3d0e42SAndrew Jeffery * Declare a pointer to a signal expression 3854d3d0e42SAndrew Jeffery * 3864d3d0e42SAndrew Jeffery * @sig: The macro symbol name for the signal (subjected to token pasting) 3874d3d0e42SAndrew Jeffery * @func: The macro symbol name for the function (subjected to token pasting) 3884d3d0e42SAndrew Jeffery */ 3894d3d0e42SAndrew Jeffery #define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func)) 3904d3d0e42SAndrew Jeffery 3914d3d0e42SAndrew Jeffery #define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig 3924d3d0e42SAndrew Jeffery 3934d3d0e42SAndrew Jeffery /** 3944d3d0e42SAndrew Jeffery * Declare a signal expression list for reference in a struct aspeed_pin_prio. 3954d3d0e42SAndrew Jeffery * 3964d3d0e42SAndrew Jeffery * @sig: A macro symbol name for the signal (is subjected to token pasting) 3974d3d0e42SAndrew Jeffery * @...: Signal expression structure pointers (use SIG_EXPR_PTR()) 3984d3d0e42SAndrew Jeffery * 3994d3d0e42SAndrew Jeffery * For example, the 16-bit ROM bus can be enabled by one of two possible signal 4004d3d0e42SAndrew Jeffery * expressions: 4014d3d0e42SAndrew Jeffery * 4024d3d0e42SAndrew Jeffery * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); 4034d3d0e42SAndrew Jeffery * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), 4044d3d0e42SAndrew Jeffery * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); 4054d3d0e42SAndrew Jeffery * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), 4064d3d0e42SAndrew Jeffery * SIG_EXPR_PTR(ROMD8, ROM16S)); 4074d3d0e42SAndrew Jeffery */ 4084d3d0e42SAndrew Jeffery #define SIG_EXPR_LIST_DECL(sig, ...) \ 4094d3d0e42SAndrew Jeffery static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \ 4104d3d0e42SAndrew Jeffery { __VA_ARGS__, NULL } 4114d3d0e42SAndrew Jeffery 4124d3d0e42SAndrew Jeffery /** 4134d3d0e42SAndrew Jeffery * A short-hand macro for declaring a function expression and an expression 4144d3d0e42SAndrew Jeffery * list with a single function. 4154d3d0e42SAndrew Jeffery * 4164d3d0e42SAndrew Jeffery * @func: A macro symbol name for the function (is subjected to token pasting) 4174d3d0e42SAndrew Jeffery * @...: Function descriptors that define the function expression 4184d3d0e42SAndrew Jeffery * 4194d3d0e42SAndrew Jeffery * For example, signal NCTS6 participates in its own function with one group: 4204d3d0e42SAndrew Jeffery * 4214d3d0e42SAndrew Jeffery * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); 4224d3d0e42SAndrew Jeffery */ 4234d3d0e42SAndrew Jeffery #define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \ 4244d3d0e42SAndrew Jeffery SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ 4254d3d0e42SAndrew Jeffery SIG_EXPR_DECL_(sig, func); \ 4264d3d0e42SAndrew Jeffery SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func)) 4274d3d0e42SAndrew Jeffery 4284d3d0e42SAndrew Jeffery #define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \ 4294d3d0e42SAndrew Jeffery SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1)) 4304d3d0e42SAndrew Jeffery 4314d3d0e42SAndrew Jeffery #define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0]) 4324d3d0e42SAndrew Jeffery 4334d3d0e42SAndrew Jeffery #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin 4344d3d0e42SAndrew Jeffery #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) 4354d3d0e42SAndrew Jeffery #define PIN_SYM(pin) pin_ ## pin 4364d3d0e42SAndrew Jeffery 4374d3d0e42SAndrew Jeffery #define MS_PIN_DECL_(pin, ...) \ 4384d3d0e42SAndrew Jeffery static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \ 4394d3d0e42SAndrew Jeffery { __VA_ARGS__, NULL }; \ 4404d3d0e42SAndrew Jeffery static const struct aspeed_pin_desc PIN_SYM(pin) = \ 4414d3d0e42SAndrew Jeffery { #pin, PIN_EXPRS_PTR(pin) } 4424d3d0e42SAndrew Jeffery 4434d3d0e42SAndrew Jeffery /** 4444d3d0e42SAndrew Jeffery * Declare a multi-signal pin 4454d3d0e42SAndrew Jeffery * 4464d3d0e42SAndrew Jeffery * @pin: The pin number 4474d3d0e42SAndrew Jeffery * @other: Macro name for "other" functionality (subjected to stringification) 4484d3d0e42SAndrew Jeffery * @high: Macro name for the highest priority signal functions 4494d3d0e42SAndrew Jeffery * @low: Macro name for the low signal functions 4504d3d0e42SAndrew Jeffery * 4514d3d0e42SAndrew Jeffery * For example: 4524d3d0e42SAndrew Jeffery * 4534d3d0e42SAndrew Jeffery * #define A8 56 4544d3d0e42SAndrew Jeffery * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); 4554d3d0e42SAndrew Jeffery * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), 4564d3d0e42SAndrew Jeffery * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); 4574d3d0e42SAndrew Jeffery * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), 4584d3d0e42SAndrew Jeffery * SIG_EXPR_PTR(ROMD8, ROM16S)); 4594d3d0e42SAndrew Jeffery * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); 4604d3d0e42SAndrew Jeffery * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); 4614d3d0e42SAndrew Jeffery */ 4624d3d0e42SAndrew Jeffery #define MS_PIN_DECL(pin, other, high, low) \ 4634d3d0e42SAndrew Jeffery SIG_EXPR_LIST_DECL_SINGLE(other, other); \ 4644d3d0e42SAndrew Jeffery MS_PIN_DECL_(pin, \ 4654d3d0e42SAndrew Jeffery SIG_EXPR_LIST_PTR(high), \ 4664d3d0e42SAndrew Jeffery SIG_EXPR_LIST_PTR(low), \ 4674d3d0e42SAndrew Jeffery SIG_EXPR_LIST_PTR(other)) 4684d3d0e42SAndrew Jeffery 4694d3d0e42SAndrew Jeffery #define PIN_GROUP_SYM(func) pins_ ## func 4704d3d0e42SAndrew Jeffery #define FUNC_GROUP_SYM(func) groups_ ## func 4714d3d0e42SAndrew Jeffery #define FUNC_GROUP_DECL(func, ...) \ 4724d3d0e42SAndrew Jeffery static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \ 4734d3d0e42SAndrew Jeffery static const char *FUNC_GROUP_SYM(func)[] = { #func } 4744d3d0e42SAndrew Jeffery 4754d3d0e42SAndrew Jeffery /** 4764d3d0e42SAndrew Jeffery * Declare a single signal pin 4774d3d0e42SAndrew Jeffery * 4784d3d0e42SAndrew Jeffery * @pin: The pin number 4794d3d0e42SAndrew Jeffery * @other: Macro name for "other" functionality (subjected to stringification) 4804d3d0e42SAndrew Jeffery * @sig: Macro name for the signal (subjected to stringification) 4814d3d0e42SAndrew Jeffery * 4824d3d0e42SAndrew Jeffery * For example: 4834d3d0e42SAndrew Jeffery * 4844d3d0e42SAndrew Jeffery * #define E3 80 4854d3d0e42SAndrew Jeffery * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); 4864d3d0e42SAndrew Jeffery * SS_PIN_DECL(E3, GPIOK0, SCL5); 4874d3d0e42SAndrew Jeffery */ 4884d3d0e42SAndrew Jeffery #define SS_PIN_DECL(pin, other, sig) \ 4894d3d0e42SAndrew Jeffery SIG_EXPR_LIST_DECL_SINGLE(other, other); \ 4904d3d0e42SAndrew Jeffery MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)) 4914d3d0e42SAndrew Jeffery 4924d3d0e42SAndrew Jeffery /** 4934d3d0e42SAndrew Jeffery * Single signal, single function pin declaration 4944d3d0e42SAndrew Jeffery * 4954d3d0e42SAndrew Jeffery * @pin: The pin number 4964d3d0e42SAndrew Jeffery * @other: Macro name for "other" functionality (subjected to stringification) 4974d3d0e42SAndrew Jeffery * @sig: Macro name for the signal (subjected to stringification) 4984d3d0e42SAndrew Jeffery * @...: Signal descriptors that define the function expression 4994d3d0e42SAndrew Jeffery * 5004d3d0e42SAndrew Jeffery * For example: 5014d3d0e42SAndrew Jeffery * 5024d3d0e42SAndrew Jeffery * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); 5034d3d0e42SAndrew Jeffery */ 5044d3d0e42SAndrew Jeffery #define SSSF_PIN_DECL(pin, other, sig, ...) \ 5054d3d0e42SAndrew Jeffery SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \ 5064d3d0e42SAndrew Jeffery SIG_EXPR_LIST_DECL_SINGLE(other, other); \ 5074d3d0e42SAndrew Jeffery MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \ 5084d3d0e42SAndrew Jeffery FUNC_GROUP_DECL(sig, pin) 5094d3d0e42SAndrew Jeffery 5104d3d0e42SAndrew Jeffery #define GPIO_PIN_DECL(pin, gpio) \ 5114d3d0e42SAndrew Jeffery SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \ 5124d3d0e42SAndrew Jeffery MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) 5134d3d0e42SAndrew Jeffery 5147f354fd1SAndrew Jeffery /** 5157f354fd1SAndrew Jeffery * @param The pinconf parameter type 5167f354fd1SAndrew Jeffery * @pins The pin range this config struct covers, [low, high] 5177f354fd1SAndrew Jeffery * @reg The register housing the configuration bits 5187f354fd1SAndrew Jeffery * @mask The mask to select the bits of interest in @reg 5197f354fd1SAndrew Jeffery */ 5207f354fd1SAndrew Jeffery struct aspeed_pin_config { 5217f354fd1SAndrew Jeffery enum pin_config_param param; 5227f354fd1SAndrew Jeffery unsigned int pins[2]; 5237f354fd1SAndrew Jeffery unsigned int reg; 5247f354fd1SAndrew Jeffery u8 bit; 5257f354fd1SAndrew Jeffery u8 value; 5267f354fd1SAndrew Jeffery }; 5277f354fd1SAndrew Jeffery 5284d3d0e42SAndrew Jeffery struct aspeed_pinctrl_data { 5297d29ed88SAndrew Jeffery struct regmap *maps[ASPEED_NR_PINMUX_IPS]; 5304d3d0e42SAndrew Jeffery 5314d3d0e42SAndrew Jeffery const struct pinctrl_pin_desc *pins; 5324d3d0e42SAndrew Jeffery const unsigned int npins; 5334d3d0e42SAndrew Jeffery 5344d3d0e42SAndrew Jeffery const struct aspeed_pin_group *groups; 5354d3d0e42SAndrew Jeffery const unsigned int ngroups; 5364d3d0e42SAndrew Jeffery 5374d3d0e42SAndrew Jeffery const struct aspeed_pin_function *functions; 5384d3d0e42SAndrew Jeffery const unsigned int nfunctions; 5397f354fd1SAndrew Jeffery 5407f354fd1SAndrew Jeffery const struct aspeed_pin_config *configs; 5417f354fd1SAndrew Jeffery const unsigned int nconfigs; 5424d3d0e42SAndrew Jeffery }; 5434d3d0e42SAndrew Jeffery 5444d3d0e42SAndrew Jeffery #define ASPEED_PINCTRL_PIN(name_) \ 5454d3d0e42SAndrew Jeffery [name_] = { \ 5464d3d0e42SAndrew Jeffery .number = name_, \ 5474d3d0e42SAndrew Jeffery .name = #name_, \ 5484d3d0e42SAndrew Jeffery .drv_data = (void *) &(PIN_SYM(name_)) \ 5494d3d0e42SAndrew Jeffery } 5504d3d0e42SAndrew Jeffery 5514d3d0e42SAndrew Jeffery struct aspeed_pin_group { 5524d3d0e42SAndrew Jeffery const char *name; 5534d3d0e42SAndrew Jeffery const unsigned int *pins; 5544d3d0e42SAndrew Jeffery const unsigned int npins; 5554d3d0e42SAndrew Jeffery }; 5564d3d0e42SAndrew Jeffery 5574d3d0e42SAndrew Jeffery #define ASPEED_PINCTRL_GROUP(name_) { \ 5584d3d0e42SAndrew Jeffery .name = #name_, \ 5594d3d0e42SAndrew Jeffery .pins = &(PIN_GROUP_SYM(name_))[0], \ 5604d3d0e42SAndrew Jeffery .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \ 5614d3d0e42SAndrew Jeffery } 5624d3d0e42SAndrew Jeffery 5634d3d0e42SAndrew Jeffery struct aspeed_pin_function { 5644d3d0e42SAndrew Jeffery const char *name; 5654d3d0e42SAndrew Jeffery const char *const *groups; 5664d3d0e42SAndrew Jeffery unsigned int ngroups; 5674d3d0e42SAndrew Jeffery }; 5684d3d0e42SAndrew Jeffery 5694d3d0e42SAndrew Jeffery #define ASPEED_PINCTRL_FUNC(name_, ...) { \ 5704d3d0e42SAndrew Jeffery .name = #name_, \ 5714d3d0e42SAndrew Jeffery .groups = &FUNC_GROUP_SYM(name_)[0], \ 5724d3d0e42SAndrew Jeffery .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \ 5734d3d0e42SAndrew Jeffery } 5744d3d0e42SAndrew Jeffery 5754d3d0e42SAndrew Jeffery int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev); 5764d3d0e42SAndrew Jeffery const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 5774d3d0e42SAndrew Jeffery unsigned int group); 5784d3d0e42SAndrew Jeffery int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 5794d3d0e42SAndrew Jeffery unsigned int group, const unsigned int **pins, 5804d3d0e42SAndrew Jeffery unsigned int *npins); 5814d3d0e42SAndrew Jeffery void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 5824d3d0e42SAndrew Jeffery struct seq_file *s, unsigned int offset); 5834d3d0e42SAndrew Jeffery int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev); 5844d3d0e42SAndrew Jeffery const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev, 5854d3d0e42SAndrew Jeffery unsigned int function); 5864d3d0e42SAndrew Jeffery int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, 5874d3d0e42SAndrew Jeffery unsigned int function, const char * const **groups, 5884d3d0e42SAndrew Jeffery unsigned int * const num_groups); 5894d3d0e42SAndrew Jeffery int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, 5904d3d0e42SAndrew Jeffery unsigned int group); 5914d3d0e42SAndrew Jeffery int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, 5924d3d0e42SAndrew Jeffery struct pinctrl_gpio_range *range, 5934d3d0e42SAndrew Jeffery unsigned int offset); 5944d3d0e42SAndrew Jeffery int aspeed_pinctrl_probe(struct platform_device *pdev, 5954d3d0e42SAndrew Jeffery struct pinctrl_desc *pdesc, 5964d3d0e42SAndrew Jeffery struct aspeed_pinctrl_data *pdata); 5977f354fd1SAndrew Jeffery int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, 5987f354fd1SAndrew Jeffery unsigned long *config); 5997f354fd1SAndrew Jeffery int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, 6007f354fd1SAndrew Jeffery unsigned long *configs, unsigned int num_configs); 6017f354fd1SAndrew Jeffery int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev, 6027f354fd1SAndrew Jeffery unsigned int selector, 6037f354fd1SAndrew Jeffery unsigned long *config); 6047f354fd1SAndrew Jeffery int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev, 6057f354fd1SAndrew Jeffery unsigned int selector, 6067f354fd1SAndrew Jeffery unsigned long *configs, 6077f354fd1SAndrew Jeffery unsigned int num_configs); 6084d3d0e42SAndrew Jeffery 6094d3d0e42SAndrew Jeffery #endif /* PINCTRL_ASPEED */ 610