1 /* 2 * Copyright (C) 2016 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 #include <linux/bitops.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/string.h> 21 #include <linux/types.h> 22 23 #include "../core.h" 24 #include "../pinctrl-utils.h" 25 #include "pinctrl-aspeed.h" 26 27 #define ASPEED_G5_NR_PINS 228 28 29 #define COND1 { SCU90, BIT(6), 0, 0 } 30 #define COND2 { SCU94, GENMASK(1, 0), 0, 0 } 31 32 #define B14 0 33 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); 34 35 #define E13 3 36 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); 37 38 #define I2C9_DESC SIG_DESC_SET(SCU90, 22) 39 40 #define C14 4 41 SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1); 42 SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); 43 MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5); 44 45 FUNC_GROUP_DECL(TIMER5, C14); 46 47 #define A13 5 48 SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1); 49 SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); 50 MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6); 51 52 FUNC_GROUP_DECL(TIMER6, A13); 53 54 FUNC_GROUP_DECL(I2C9, C14, A13); 55 56 #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) 57 58 #define C13 6 59 SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1); 60 SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); 61 MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7); 62 63 FUNC_GROUP_DECL(TIMER7, C13); 64 65 #define B13 7 66 SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1); 67 SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); 68 MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8); 69 70 FUNC_GROUP_DECL(TIMER8, B13); 71 72 FUNC_GROUP_DECL(MDIO2, C13, B13); 73 74 #define H20 15 75 GPIO_PIN_DECL(H20, GPIOB7); 76 77 #define SD1_DESC SIG_DESC_SET(SCU90, 0) 78 79 #define C12 16 80 #define I2C10_DESC SIG_DESC_SET(SCU90, 23) 81 SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); 82 SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); 83 MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10); 84 85 #define A12 17 86 SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); 87 SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); 88 MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10); 89 90 FUNC_GROUP_DECL(I2C10, C12, A12); 91 92 #define B12 18 93 #define I2C11_DESC SIG_DESC_SET(SCU90, 24) 94 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); 95 SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); 96 MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11); 97 98 #define D9 19 99 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); 100 SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); 101 MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11); 102 103 FUNC_GROUP_DECL(I2C11, B12, D9); 104 105 #define D10 20 106 #define I2C12_DESC SIG_DESC_SET(SCU90, 25) 107 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); 108 SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); 109 MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12); 110 111 #define E12 21 112 SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); 113 SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); 114 MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12); 115 116 FUNC_GROUP_DECL(I2C12, D10, E12); 117 118 #define C11 22 119 #define I2C13_DESC SIG_DESC_SET(SCU90, 26) 120 SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); 121 SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); 122 MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13); 123 124 #define B11 23 125 SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); 126 SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); 127 MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13); 128 129 FUNC_GROUP_DECL(I2C13, C11, B11); 130 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); 131 132 #define SD2_DESC SIG_DESC_SET(SCU90, 1) 133 #define GPID0_DESC SIG_DESC_SET(SCU8C, 8) 134 #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) 135 136 #define F19 24 137 SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); 138 SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); 139 SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); 140 SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); 141 MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN); 142 143 #define E21 25 144 SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); 145 SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); 146 SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); 147 SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); 148 MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT); 149 150 FUNC_GROUP_DECL(GPID0, F19, E21); 151 152 #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) 153 154 #define F20 26 155 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); 156 SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); 157 SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); 158 SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); 159 MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN); 160 161 #define D20 27 162 SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); 163 SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); 164 SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); 165 SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); 166 MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT); 167 168 FUNC_GROUP_DECL(GPID2, F20, D20); 169 170 #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21) 171 #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) 172 173 #define B20 32 174 SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); 175 SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); 176 SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); 177 SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); 178 MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); 179 180 #define C20 33 181 SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); 182 SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); 183 SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); 184 SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); 185 MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); 186 187 FUNC_GROUP_DECL(GPIE0, B20, C20); 188 189 #define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 } 190 #define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 } 191 #define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 } 192 193 #define C18 64 194 SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 195 SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 196 SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); 197 SS_PIN_DECL(C18, GPIOI0, SYSCS); 198 199 #define E15 65 200 SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 201 SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 202 SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); 203 SS_PIN_DECL(E15, GPIOI1, SYSCK); 204 205 #define B16 66 206 SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 207 SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 208 SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU); 209 SS_PIN_DECL(B16, GPIOI2, SYSMOSI); 210 211 #define C16 67 212 SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 213 SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 214 SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU); 215 SS_PIN_DECL(C16, GPIOI3, SYSMISO); 216 217 #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) 218 219 #define B15 68 220 SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC); 221 SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 222 SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 223 SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), 224 SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), 225 SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); 226 SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC); 227 MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS); 228 229 #define C15 69 230 SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC); 231 SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 232 SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 233 SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), 234 SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), 235 SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); 236 SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC); 237 MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK); 238 239 #define A14 70 240 SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC); 241 SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 242 SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 243 SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1), 244 SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG), 245 SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU)); 246 SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC); 247 MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI); 248 249 #define A15 71 250 SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC); 251 SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 252 SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 253 SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1), 254 SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG), 255 SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU)); 256 SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC); 257 MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO); 258 259 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15); 260 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15); 261 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15); 262 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15); 263 264 #define R2 72 265 SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); 266 SS_PIN_DECL(R2, GPIOJ0, SGPMCK); 267 268 #define L2 73 269 SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); 270 SS_PIN_DECL(L2, GPIOJ1, SGPMLD); 271 272 #define N3 74 273 SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); 274 SS_PIN_DECL(N3, GPIOJ2, SGPMO); 275 276 #define N4 75 277 SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); 278 SS_PIN_DECL(N4, GPIOJ3, SGPMI); 279 280 #define I2C5_DESC SIG_DESC_SET(SCU90, 18) 281 282 #define L3 80 283 SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); 284 SS_PIN_DECL(L3, GPIOK0, SCL5); 285 286 #define L4 81 287 SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); 288 SS_PIN_DECL(L4, GPIOK1, SDA5); 289 290 FUNC_GROUP_DECL(I2C5, L3, L4); 291 292 #define I2C6_DESC SIG_DESC_SET(SCU90, 19) 293 294 #define L1 82 295 SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); 296 SS_PIN_DECL(L1, GPIOK2, SCL6); 297 298 #define N2 83 299 SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); 300 SS_PIN_DECL(N2, GPIOK3, SDA6); 301 302 FUNC_GROUP_DECL(I2C6, L1, N2); 303 304 #define I2C7_DESC SIG_DESC_SET(SCU90, 20) 305 306 #define N1 84 307 SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); 308 SS_PIN_DECL(N1, GPIOK4, SCL7); 309 310 #define P1 85 311 SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); 312 SS_PIN_DECL(P1, GPIOK5, SDA7); 313 314 FUNC_GROUP_DECL(I2C7, N1, P1); 315 316 #define I2C8_DESC SIG_DESC_SET(SCU90, 21) 317 318 #define P2 86 319 SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); 320 SS_PIN_DECL(P2, GPIOK6, SCL8); 321 322 #define R1 87 323 SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); 324 SS_PIN_DECL(R1, GPIOK7, SDA8); 325 326 FUNC_GROUP_DECL(I2C8, P2, R1); 327 328 #define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 } 329 #define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 } 330 #define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } 331 #define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 } 332 333 #define V2 104 334 #define V2_DESC SIG_DESC_SET(SCU88, 0) 335 SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); 336 SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2); 337 MS_PIN_DECL(V2, GPION0, DASHN0, PWM0); 338 FUNC_GROUP_DECL(PWM0, V2); 339 340 #define W2 105 341 #define W2_DESC SIG_DESC_SET(SCU88, 1) 342 SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); 343 SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2); 344 MS_PIN_DECL(W2, GPION1, DASHN1, PWM1); 345 FUNC_GROUP_DECL(PWM1, W2); 346 347 #define V3 106 348 #define V3_DESC SIG_DESC_SET(SCU88, 2) 349 SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); 350 SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); 351 SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD); 352 SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2); 353 MS_PIN_DECL(V3, GPION2, VPIG2, PWM2); 354 FUNC_GROUP_DECL(PWM2, V3); 355 356 #define U3 107 357 #define U3_DESC SIG_DESC_SET(SCU88, 3) 358 SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); 359 SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); 360 SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD); 361 SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2); 362 MS_PIN_DECL(U3, GPION3, VPIG3, PWM3); 363 FUNC_GROUP_DECL(PWM3, U3); 364 365 #define W3 108 366 #define W3_DESC SIG_DESC_SET(SCU88, 4) 367 SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); 368 SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); 369 SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD); 370 SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2); 371 MS_PIN_DECL(W3, GPION4, VPIG4, PWM4); 372 FUNC_GROUP_DECL(PWM4, W3); 373 374 #define AA3 109 375 #define AA3_DESC SIG_DESC_SET(SCU88, 5) 376 SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); 377 SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); 378 SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD); 379 SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2); 380 MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5); 381 FUNC_GROUP_DECL(PWM5, AA3); 382 383 #define Y3 110 384 #define Y3_DESC SIG_DESC_SET(SCU88, 6) 385 SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC); 386 SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2); 387 MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6); 388 FUNC_GROUP_DECL(PWM6, Y3); 389 390 #define T4 111 391 #define T4_DESC SIG_DESC_SET(SCU88, 7) 392 SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC); 393 SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); 394 MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); 395 FUNC_GROUP_DECL(PWM7, T4); 396 397 #define V6 127 398 SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), 399 SIG_DESC_SET(SCU88, 23)); 400 SS_PIN_DECL(V6, GPIOP7, DASHV6); 401 402 #define I2C3_DESC SIG_DESC_SET(SCU90, 16) 403 404 #define A11 128 405 SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); 406 SS_PIN_DECL(A11, GPIOQ0, SCL3); 407 408 #define A10 129 409 SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); 410 SS_PIN_DECL(A10, GPIOQ1, SDA3); 411 412 FUNC_GROUP_DECL(I2C3, A11, A10); 413 414 #define I2C4_DESC SIG_DESC_SET(SCU90, 17) 415 416 #define A9 130 417 SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); 418 SS_PIN_DECL(A9, GPIOQ2, SCL4); 419 420 #define B9 131 421 SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); 422 SS_PIN_DECL(B9, GPIOQ3, SDA4); 423 424 FUNC_GROUP_DECL(I2C4, A9, B9); 425 426 #define I2C14_DESC SIG_DESC_SET(SCU90, 27) 427 428 #define N21 132 429 SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); 430 SS_PIN_DECL(N21, GPIOQ4, SCL14); 431 432 #define N22 133 433 SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); 434 SS_PIN_DECL(N22, GPIOQ5, SDA14); 435 436 FUNC_GROUP_DECL(I2C14, N21, N22); 437 438 #define B10 134 439 SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1)); 440 441 #define N20 135 442 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29)); 443 444 #define D8 142 445 SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); 446 SS_PIN_DECL(D8, GPIOR6, MDC1); 447 448 #define E10 143 449 SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); 450 SS_PIN_DECL(E10, GPIOR7, MDIO1); 451 452 FUNC_GROUP_DECL(MDIO1, D8, E10); 453 454 /* RGMII1/RMII1 */ 455 456 #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) 457 #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) 458 459 #define B5 152 460 SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); 461 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC, 462 SIG_DESC_SET(SCU48, 29)); 463 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); 464 MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO), 465 SIG_EXPR_LIST_PTR(RGMII1TXCK)); 466 467 #define E9 153 468 SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); 469 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); 470 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); 471 MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN), 472 SIG_EXPR_LIST_PTR(RGMII1TXCTL)); 473 474 #define F9 154 475 SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); 476 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); 477 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); 478 MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), 479 SIG_EXPR_LIST_PTR(RGMII1TXD0)); 480 481 #define A5 155 482 SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); 483 SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); 484 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); 485 MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), 486 SIG_EXPR_LIST_PTR(RGMII1TXD1)); 487 488 #define E7 156 489 SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); 490 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC); 491 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); 492 MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0), 493 SIG_EXPR_LIST_PTR(RGMII1TXD2)); 494 495 #define D7 157 496 SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); 497 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC); 498 SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); 499 MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1), 500 SIG_EXPR_LIST_PTR(RGMII1TXD3)); 501 502 #define B2 158 503 SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); 504 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC, 505 SIG_DESC_SET(SCU48, 30)); 506 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); 507 MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO), 508 SIG_EXPR_LIST_PTR(RGMII2TXCK)); 509 510 #define B1 159 511 SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); 512 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); 513 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); 514 MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN), 515 SIG_EXPR_LIST_PTR(RGMII2TXCTL)); 516 517 #define A2 160 518 SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); 519 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); 520 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); 521 MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), 522 SIG_EXPR_LIST_PTR(RGMII2TXD0)); 523 524 #define B3 161 525 SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); 526 SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); 527 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); 528 MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), 529 SIG_EXPR_LIST_PTR(RGMII2TXD1)); 530 531 #define D5 162 532 SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); 533 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC); 534 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); 535 MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0), 536 SIG_EXPR_LIST_PTR(RGMII2TXD2)); 537 538 #define D4 163 539 SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); 540 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC); 541 SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); 542 MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1), 543 SIG_EXPR_LIST_PTR(RGMII2TXD3)); 544 545 #define B4 164 546 SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); 547 SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC); 548 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); 549 MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI), 550 SIG_EXPR_LIST_PTR(RGMII1RXCK)); 551 552 #define A4 165 553 SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); 554 SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC); 555 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); 556 MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2), 557 SIG_EXPR_LIST_PTR(RGMII1RXCTL)); 558 559 #define A3 166 560 SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); 561 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); 562 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); 563 MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), 564 SIG_EXPR_LIST_PTR(RGMII1RXD0)); 565 566 #define D6 167 567 SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); 568 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); 569 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); 570 MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), 571 SIG_EXPR_LIST_PTR(RGMII1RXD1)); 572 573 #define C5 168 574 SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); 575 SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); 576 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); 577 MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), 578 SIG_EXPR_LIST_PTR(RGMII1RXD2)); 579 580 #define C4 169 581 SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); 582 SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); 583 SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); 584 MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), 585 SIG_EXPR_LIST_PTR(RGMII1RXD3)); 586 587 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7); 588 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5); 589 590 #define C2 170 591 SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); 592 SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC); 593 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); 594 MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI), 595 SIG_EXPR_LIST_PTR(RGMII2RXCK)); 596 597 #define C1 171 598 SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); 599 SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC); 600 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); 601 MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2), 602 SIG_EXPR_LIST_PTR(RGMII2RXCTL)); 603 604 #define C3 172 605 SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); 606 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); 607 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); 608 MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), 609 SIG_EXPR_LIST_PTR(RGMII2RXD0)); 610 611 #define D1 173 612 SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); 613 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); 614 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); 615 MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), 616 SIG_EXPR_LIST_PTR(RGMII2RXD1)); 617 618 #define D2 174 619 SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); 620 SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); 621 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); 622 MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), 623 SIG_EXPR_LIST_PTR(RGMII2RXD2)); 624 625 #define E6 175 626 SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); 627 SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); 628 SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); 629 MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), 630 SIG_EXPR_LIST_PTR(RGMII2RXD3)); 631 632 FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); 633 FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); 634 635 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ 636 637 static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { 638 ASPEED_PINCTRL_PIN(A10), 639 ASPEED_PINCTRL_PIN(A11), 640 ASPEED_PINCTRL_PIN(A12), 641 ASPEED_PINCTRL_PIN(A13), 642 ASPEED_PINCTRL_PIN(A14), 643 ASPEED_PINCTRL_PIN(A15), 644 ASPEED_PINCTRL_PIN(A2), 645 ASPEED_PINCTRL_PIN(A3), 646 ASPEED_PINCTRL_PIN(A4), 647 ASPEED_PINCTRL_PIN(A5), 648 ASPEED_PINCTRL_PIN(A9), 649 ASPEED_PINCTRL_PIN(AA3), 650 ASPEED_PINCTRL_PIN(B1), 651 ASPEED_PINCTRL_PIN(B10), 652 ASPEED_PINCTRL_PIN(B11), 653 ASPEED_PINCTRL_PIN(B12), 654 ASPEED_PINCTRL_PIN(B13), 655 ASPEED_PINCTRL_PIN(B14), 656 ASPEED_PINCTRL_PIN(B15), 657 ASPEED_PINCTRL_PIN(B16), 658 ASPEED_PINCTRL_PIN(B2), 659 ASPEED_PINCTRL_PIN(B20), 660 ASPEED_PINCTRL_PIN(B3), 661 ASPEED_PINCTRL_PIN(B4), 662 ASPEED_PINCTRL_PIN(B5), 663 ASPEED_PINCTRL_PIN(B9), 664 ASPEED_PINCTRL_PIN(C1), 665 ASPEED_PINCTRL_PIN(C11), 666 ASPEED_PINCTRL_PIN(C12), 667 ASPEED_PINCTRL_PIN(C13), 668 ASPEED_PINCTRL_PIN(C14), 669 ASPEED_PINCTRL_PIN(C15), 670 ASPEED_PINCTRL_PIN(C16), 671 ASPEED_PINCTRL_PIN(C18), 672 ASPEED_PINCTRL_PIN(C2), 673 ASPEED_PINCTRL_PIN(C20), 674 ASPEED_PINCTRL_PIN(C3), 675 ASPEED_PINCTRL_PIN(C4), 676 ASPEED_PINCTRL_PIN(C5), 677 ASPEED_PINCTRL_PIN(D1), 678 ASPEED_PINCTRL_PIN(D10), 679 ASPEED_PINCTRL_PIN(D2), 680 ASPEED_PINCTRL_PIN(D20), 681 ASPEED_PINCTRL_PIN(D4), 682 ASPEED_PINCTRL_PIN(D5), 683 ASPEED_PINCTRL_PIN(D6), 684 ASPEED_PINCTRL_PIN(D7), 685 ASPEED_PINCTRL_PIN(D8), 686 ASPEED_PINCTRL_PIN(D9), 687 ASPEED_PINCTRL_PIN(E10), 688 ASPEED_PINCTRL_PIN(E12), 689 ASPEED_PINCTRL_PIN(E13), 690 ASPEED_PINCTRL_PIN(E15), 691 ASPEED_PINCTRL_PIN(E21), 692 ASPEED_PINCTRL_PIN(E6), 693 ASPEED_PINCTRL_PIN(E7), 694 ASPEED_PINCTRL_PIN(E9), 695 ASPEED_PINCTRL_PIN(F19), 696 ASPEED_PINCTRL_PIN(F20), 697 ASPEED_PINCTRL_PIN(F9), 698 ASPEED_PINCTRL_PIN(H20), 699 ASPEED_PINCTRL_PIN(L1), 700 ASPEED_PINCTRL_PIN(L2), 701 ASPEED_PINCTRL_PIN(L3), 702 ASPEED_PINCTRL_PIN(L4), 703 ASPEED_PINCTRL_PIN(N1), 704 ASPEED_PINCTRL_PIN(N2), 705 ASPEED_PINCTRL_PIN(N20), 706 ASPEED_PINCTRL_PIN(N21), 707 ASPEED_PINCTRL_PIN(N22), 708 ASPEED_PINCTRL_PIN(N3), 709 ASPEED_PINCTRL_PIN(N4), 710 ASPEED_PINCTRL_PIN(P1), 711 ASPEED_PINCTRL_PIN(P2), 712 ASPEED_PINCTRL_PIN(R1), 713 ASPEED_PINCTRL_PIN(T4), 714 ASPEED_PINCTRL_PIN(U3), 715 ASPEED_PINCTRL_PIN(V2), 716 ASPEED_PINCTRL_PIN(V3), 717 ASPEED_PINCTRL_PIN(V6), 718 ASPEED_PINCTRL_PIN(W2), 719 ASPEED_PINCTRL_PIN(W3), 720 ASPEED_PINCTRL_PIN(Y3), 721 }; 722 723 static const struct aspeed_pin_group aspeed_g5_groups[] = { 724 ASPEED_PINCTRL_GROUP(GPID0), 725 ASPEED_PINCTRL_GROUP(GPID2), 726 ASPEED_PINCTRL_GROUP(GPIE0), 727 ASPEED_PINCTRL_GROUP(I2C10), 728 ASPEED_PINCTRL_GROUP(I2C11), 729 ASPEED_PINCTRL_GROUP(I2C12), 730 ASPEED_PINCTRL_GROUP(I2C13), 731 ASPEED_PINCTRL_GROUP(I2C14), 732 ASPEED_PINCTRL_GROUP(I2C3), 733 ASPEED_PINCTRL_GROUP(I2C4), 734 ASPEED_PINCTRL_GROUP(I2C5), 735 ASPEED_PINCTRL_GROUP(I2C6), 736 ASPEED_PINCTRL_GROUP(I2C7), 737 ASPEED_PINCTRL_GROUP(I2C8), 738 ASPEED_PINCTRL_GROUP(I2C9), 739 ASPEED_PINCTRL_GROUP(MAC1LINK), 740 ASPEED_PINCTRL_GROUP(MDIO1), 741 ASPEED_PINCTRL_GROUP(MDIO2), 742 ASPEED_PINCTRL_GROUP(OSCCLK), 743 ASPEED_PINCTRL_GROUP(PEWAKE), 744 ASPEED_PINCTRL_GROUP(PWM0), 745 ASPEED_PINCTRL_GROUP(PWM1), 746 ASPEED_PINCTRL_GROUP(PWM2), 747 ASPEED_PINCTRL_GROUP(PWM3), 748 ASPEED_PINCTRL_GROUP(PWM4), 749 ASPEED_PINCTRL_GROUP(PWM5), 750 ASPEED_PINCTRL_GROUP(PWM6), 751 ASPEED_PINCTRL_GROUP(PWM7), 752 ASPEED_PINCTRL_GROUP(RGMII1), 753 ASPEED_PINCTRL_GROUP(RGMII2), 754 ASPEED_PINCTRL_GROUP(RMII1), 755 ASPEED_PINCTRL_GROUP(RMII2), 756 ASPEED_PINCTRL_GROUP(SD1), 757 ASPEED_PINCTRL_GROUP(SPI1), 758 ASPEED_PINCTRL_GROUP(SPI1DEBUG), 759 ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), 760 ASPEED_PINCTRL_GROUP(TIMER4), 761 ASPEED_PINCTRL_GROUP(TIMER5), 762 ASPEED_PINCTRL_GROUP(TIMER6), 763 ASPEED_PINCTRL_GROUP(TIMER7), 764 ASPEED_PINCTRL_GROUP(TIMER8), 765 ASPEED_PINCTRL_GROUP(VGABIOSROM), 766 }; 767 768 static const struct aspeed_pin_function aspeed_g5_functions[] = { 769 ASPEED_PINCTRL_FUNC(GPID0), 770 ASPEED_PINCTRL_FUNC(GPID2), 771 ASPEED_PINCTRL_FUNC(GPIE0), 772 ASPEED_PINCTRL_FUNC(I2C10), 773 ASPEED_PINCTRL_FUNC(I2C11), 774 ASPEED_PINCTRL_FUNC(I2C12), 775 ASPEED_PINCTRL_FUNC(I2C13), 776 ASPEED_PINCTRL_FUNC(I2C14), 777 ASPEED_PINCTRL_FUNC(I2C3), 778 ASPEED_PINCTRL_FUNC(I2C4), 779 ASPEED_PINCTRL_FUNC(I2C5), 780 ASPEED_PINCTRL_FUNC(I2C6), 781 ASPEED_PINCTRL_FUNC(I2C7), 782 ASPEED_PINCTRL_FUNC(I2C8), 783 ASPEED_PINCTRL_FUNC(I2C9), 784 ASPEED_PINCTRL_FUNC(MAC1LINK), 785 ASPEED_PINCTRL_FUNC(MDIO1), 786 ASPEED_PINCTRL_FUNC(MDIO2), 787 ASPEED_PINCTRL_FUNC(OSCCLK), 788 ASPEED_PINCTRL_FUNC(PEWAKE), 789 ASPEED_PINCTRL_FUNC(PWM0), 790 ASPEED_PINCTRL_FUNC(PWM1), 791 ASPEED_PINCTRL_FUNC(PWM2), 792 ASPEED_PINCTRL_FUNC(PWM3), 793 ASPEED_PINCTRL_FUNC(PWM4), 794 ASPEED_PINCTRL_FUNC(PWM5), 795 ASPEED_PINCTRL_FUNC(PWM6), 796 ASPEED_PINCTRL_FUNC(PWM7), 797 ASPEED_PINCTRL_FUNC(RGMII1), 798 ASPEED_PINCTRL_FUNC(RGMII2), 799 ASPEED_PINCTRL_FUNC(RMII1), 800 ASPEED_PINCTRL_FUNC(RMII2), 801 ASPEED_PINCTRL_FUNC(SD1), 802 ASPEED_PINCTRL_FUNC(SPI1), 803 ASPEED_PINCTRL_FUNC(SPI1DEBUG), 804 ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), 805 ASPEED_PINCTRL_FUNC(TIMER4), 806 ASPEED_PINCTRL_FUNC(TIMER5), 807 ASPEED_PINCTRL_FUNC(TIMER6), 808 ASPEED_PINCTRL_FUNC(TIMER7), 809 ASPEED_PINCTRL_FUNC(TIMER8), 810 ASPEED_PINCTRL_FUNC(VGABIOSROM), 811 }; 812 813 static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { 814 .pins = aspeed_g5_pins, 815 .npins = ARRAY_SIZE(aspeed_g5_pins), 816 .groups = aspeed_g5_groups, 817 .ngroups = ARRAY_SIZE(aspeed_g5_groups), 818 .functions = aspeed_g5_functions, 819 .nfunctions = ARRAY_SIZE(aspeed_g5_functions), 820 }; 821 822 static struct pinmux_ops aspeed_g5_pinmux_ops = { 823 .get_functions_count = aspeed_pinmux_get_fn_count, 824 .get_function_name = aspeed_pinmux_get_fn_name, 825 .get_function_groups = aspeed_pinmux_get_fn_groups, 826 .set_mux = aspeed_pinmux_set_mux, 827 .gpio_request_enable = aspeed_gpio_request_enable, 828 .strict = true, 829 }; 830 831 static struct pinctrl_ops aspeed_g5_pinctrl_ops = { 832 .get_groups_count = aspeed_pinctrl_get_groups_count, 833 .get_group_name = aspeed_pinctrl_get_group_name, 834 .get_group_pins = aspeed_pinctrl_get_group_pins, 835 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, 836 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 837 .dt_free_map = pinctrl_utils_free_map, 838 }; 839 840 static struct pinctrl_desc aspeed_g5_pinctrl_desc = { 841 .name = "aspeed-g5-pinctrl", 842 .pins = aspeed_g5_pins, 843 .npins = ARRAY_SIZE(aspeed_g5_pins), 844 .pctlops = &aspeed_g5_pinctrl_ops, 845 .pmxops = &aspeed_g5_pinmux_ops, 846 }; 847 848 static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) 849 { 850 int i; 851 852 for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) 853 aspeed_g5_pins[i].number = i; 854 855 return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, 856 &aspeed_g5_pinctrl_data); 857 } 858 859 static const struct of_device_id aspeed_g5_pinctrl_of_match[] = { 860 { .compatible = "aspeed,ast2500-pinctrl", }, 861 { .compatible = "aspeed,g5-pinctrl", }, 862 { }, 863 }; 864 865 static struct platform_driver aspeed_g5_pinctrl_driver = { 866 .probe = aspeed_g5_pinctrl_probe, 867 .driver = { 868 .name = "aspeed-g5-pinctrl", 869 .of_match_table = aspeed_g5_pinctrl_of_match, 870 }, 871 }; 872 873 static int aspeed_g5_pinctrl_init(void) 874 { 875 return platform_driver_register(&aspeed_g5_pinctrl_driver); 876 } 877 878 arch_initcall(aspeed_g5_pinctrl_init); 879