1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 IBM Corp. 4 */ 5 #include <linux/bitops.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/mutex.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pinctrl/pinctrl.h> 14 #include <linux/pinctrl/pinmux.h> 15 #include <linux/pinctrl/pinconf.h> 16 #include <linux/pinctrl/pinconf-generic.h> 17 #include <linux/string.h> 18 #include <linux/types.h> 19 20 #include "../core.h" 21 #include "../pinctrl-utils.h" 22 #include "pinctrl-aspeed.h" 23 24 /* Wrap some of the common macros for clarity */ 25 #define SIG_EXPR_DECL_SINGLE(sig, func, ...) \ 26 SIG_EXPR_DECL(sig, func, func, __VA_ARGS__) 27 28 #define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG 29 #define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG 30 31 /* 32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet 33 * references registers by the device/offset mnemonic. The register macros 34 * below are named the same way to ease transcription and verification (as 35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions 36 * reference registers beyond those dedicated to pinmux, such as the system 37 * reset control and MAC clock configuration registers. The AST2500 goes a step 38 * further and references registers in the graphics IP block. 39 */ 40 #define SCU2C 0x2C /* Misc. Control Register */ 41 #define SCU3C 0x3C /* System Reset Control/Status Register */ 42 #define SCU48 0x48 /* MAC Interface Clock Delay Setting */ 43 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ 44 #define HW_REVISION_ID 0x7C /* Silicon revision ID register */ 45 #define SCU80 0x80 /* Multi-function Pin Control #1 */ 46 #define SCU84 0x84 /* Multi-function Pin Control #2 */ 47 #define SCU88 0x88 /* Multi-function Pin Control #3 */ 48 #define SCU8C 0x8C /* Multi-function Pin Control #4 */ 49 #define SCU90 0x90 /* Multi-function Pin Control #5 */ 50 #define SCU94 0x94 /* Multi-function Pin Control #6 */ 51 #define SCUA0 0xA0 /* Multi-function Pin Control #7 */ 52 #define SCUA4 0xA4 /* Multi-function Pin Control #8 */ 53 #define SCUA8 0xA8 /* Multi-function Pin Control #9 */ 54 #define SCUAC 0xAC /* Multi-function Pin Control #10 */ 55 #define HW_STRAP2 0xD0 /* Strapping */ 56 57 #define ASPEED_G5_NR_PINS 236 58 59 #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } 60 #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } 61 62 /* LHCR0 is offset from the end of the H8S/2168-compatible registers */ 63 #define LHCR0 0xa0 64 #define GFX064 0x64 65 66 #define B14 0 67 SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); 68 69 #define D14 1 70 SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); 71 72 #define D13 2 73 SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); 74 SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); 75 PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3); 76 FUNC_GROUP_DECL(SPI1CS1, D13); 77 FUNC_GROUP_DECL(TIMER3, D13); 78 79 #define E13 3 80 SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); 81 82 #define I2C9_DESC SIG_DESC_SET(SCU90, 22) 83 84 #define C14 4 85 SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1); 86 SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); 87 PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5); 88 89 FUNC_GROUP_DECL(TIMER5, C14); 90 91 #define A13 5 92 SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1); 93 SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); 94 PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6); 95 96 FUNC_GROUP_DECL(TIMER6, A13); 97 98 FUNC_GROUP_DECL(I2C9, C14, A13); 99 100 #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) 101 102 #define C13 6 103 SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1); 104 SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); 105 PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7); 106 107 FUNC_GROUP_DECL(TIMER7, C13); 108 109 #define B13 7 110 SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1); 111 SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); 112 PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8); 113 114 FUNC_GROUP_DECL(TIMER8, B13); 115 116 FUNC_GROUP_DECL(MDIO2, C13, B13); 117 118 #define K19 8 119 GPIO_PIN_DECL(K19, GPIOB0); 120 121 #define L19 9 122 GPIO_PIN_DECL(L19, GPIOB1); 123 124 #define L18 10 125 GPIO_PIN_DECL(L18, GPIOB2); 126 127 #define K18 11 128 GPIO_PIN_DECL(K18, GPIOB3); 129 130 #define J20 12 131 SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); 132 133 #define H21 13 134 #define H21_DESC SIG_DESC_SET(SCU80, 13) 135 SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC); 136 SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC); 137 PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI); 138 FUNC_GROUP_DECL(LPCPD, H21); 139 FUNC_GROUP_DECL(LPCSMI, H21); 140 141 #define H22 14 142 SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); 143 144 #define H20 15 145 GPIO_PIN_DECL(H20, GPIOB7); 146 147 #define SD1_DESC SIG_DESC_SET(SCU90, 0) 148 149 #define C12 16 150 #define I2C10_DESC SIG_DESC_SET(SCU90, 23) 151 SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC); 152 SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC); 153 PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10); 154 155 #define A12 17 156 SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC); 157 SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC); 158 PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10); 159 160 FUNC_GROUP_DECL(I2C10, C12, A12); 161 162 #define B12 18 163 #define I2C11_DESC SIG_DESC_SET(SCU90, 24) 164 SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC); 165 SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC); 166 PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11); 167 168 #define D9 19 169 SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC); 170 SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC); 171 PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11); 172 173 FUNC_GROUP_DECL(I2C11, B12, D9); 174 175 #define D10 20 176 #define I2C12_DESC SIG_DESC_SET(SCU90, 25) 177 SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC); 178 SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC); 179 PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12); 180 181 #define E12 21 182 SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC); 183 SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC); 184 PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12); 185 186 FUNC_GROUP_DECL(I2C12, D10, E12); 187 188 #define C11 22 189 #define I2C13_DESC SIG_DESC_SET(SCU90, 26) 190 SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC); 191 SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC); 192 PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13); 193 194 #define B11 23 195 SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC); 196 SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC); 197 PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13); 198 199 FUNC_GROUP_DECL(I2C13, C11, B11); 200 FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); 201 202 #define SD2_DESC SIG_DESC_SET(SCU90, 1) 203 #define GPID0_DESC SIG_DESC_SET(SCU8C, 8) 204 #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) 205 206 #define F19 24 207 SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC); 208 SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC); 209 SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC); 210 SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID); 211 PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN); 212 213 #define E21 25 214 SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC); 215 SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC); 216 SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC); 217 SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID); 218 PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT); 219 220 FUNC_GROUP_DECL(GPID0, F19, E21); 221 222 #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) 223 224 #define F20 26 225 SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC); 226 SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC); 227 SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC); 228 SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID); 229 PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN); 230 231 #define D20 27 232 SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC); 233 SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC); 234 SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC); 235 SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID); 236 PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT); 237 238 FUNC_GROUP_DECL(GPID2, F20, D20); 239 240 #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) 241 242 #define D21 28 243 SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC); 244 SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC); 245 SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC); 246 SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID); 247 PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN); 248 249 #define E20 29 250 SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC); 251 SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC); 252 SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC); 253 SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID); 254 PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT); 255 256 FUNC_GROUP_DECL(GPID4, D21, E20); 257 258 #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) 259 260 #define G18 30 261 SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC); 262 SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC); 263 SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC); 264 SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID); 265 PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN); 266 267 #define C21 31 268 SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC); 269 SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC); 270 SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC); 271 SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID); 272 PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT); 273 274 FUNC_GROUP_DECL(GPID6, G18, C21); 275 FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); 276 277 #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) 278 #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) 279 280 #define B20 32 281 SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); 282 SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC); 283 SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC); 284 SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE); 285 PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN); 286 FUNC_GROUP_DECL(NCTS3, B20); 287 288 #define C20 33 289 SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); 290 SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC); 291 SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC); 292 SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE); 293 PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT); 294 FUNC_GROUP_DECL(NDCD3, C20); 295 296 FUNC_GROUP_DECL(GPIE0, B20, C20); 297 298 #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) 299 300 #define F18 34 301 SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); 302 SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC); 303 SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC); 304 SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE); 305 PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN); 306 FUNC_GROUP_DECL(NDSR3, F18); 307 308 309 #define F17 35 310 SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); 311 SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC); 312 SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC); 313 SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE); 314 PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT); 315 FUNC_GROUP_DECL(NRI3, F17); 316 317 FUNC_GROUP_DECL(GPIE2, F18, F17); 318 319 #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) 320 321 #define E18 36 322 SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); 323 SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC); 324 SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC); 325 SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE); 326 PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN); 327 FUNC_GROUP_DECL(NDTR3, E18); 328 329 #define D19 37 330 SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); 331 SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC); 332 SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC); 333 SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE); 334 PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT); 335 FUNC_GROUP_DECL(NRTS3, D19); 336 337 FUNC_GROUP_DECL(GPIE4, E18, D19); 338 339 #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) 340 341 #define A20 38 342 SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); 343 SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC); 344 SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC); 345 SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE); 346 PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN); 347 FUNC_GROUP_DECL(TXD3, A20); 348 349 #define B19 39 350 SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); 351 SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC); 352 SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC); 353 SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE); 354 PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT); 355 FUNC_GROUP_DECL(RXD3, B19); 356 357 FUNC_GROUP_DECL(GPIE6, A20, B19); 358 359 #define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0) 360 #define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30) 361 362 #define J19 40 363 SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC); 364 SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC); 365 SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS); 366 SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); 367 PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4); 368 FUNC_GROUP_DECL(NCTS4, J19); 369 370 #define J18 41 371 SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC); 372 SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC); 373 SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS); 374 SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); 375 PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4); 376 FUNC_GROUP_DECL(NDCD4, J18); 377 378 #define B22 42 379 SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC); 380 SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC); 381 SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS); 382 SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); 383 PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4); 384 FUNC_GROUP_DECL(NDSR4, B22); 385 386 #define B21 43 387 SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC); 388 SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC); 389 SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS); 390 SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); 391 PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4); 392 FUNC_GROUP_DECL(NRI4, B21); 393 394 #define A21 44 395 SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC); 396 SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC); 397 SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS); 398 SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); 399 PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4); 400 FUNC_GROUP_DECL(NDTR4, A21); 401 402 #define H19 45 403 SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC); 404 SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC); 405 SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS); 406 SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); 407 PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4); 408 FUNC_GROUP_DECL(NRTS4, H19); 409 410 #define G17 46 411 SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC); 412 SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); 413 PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4); 414 FUNC_GROUP_DECL(TXD4, G17); 415 416 #define H18 47 417 SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC); 418 SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC); 419 SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS); 420 SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); 421 PIN_DECL_2(H18, GPIOF7, LHRST, RXD4); 422 FUNC_GROUP_DECL(RXD4, H18); 423 424 FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18); 425 FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18); 426 427 #define A19 48 428 SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); 429 PIN_DECL_1(A19, GPIOG0, SGPS1CK); 430 431 #define E19 49 432 SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); 433 PIN_DECL_1(E19, GPIOG1, SGPS1LD); 434 435 #define C19 50 436 SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); 437 PIN_DECL_1(C19, GPIOG2, SGPS1I0); 438 439 #define E16 51 440 SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); 441 PIN_DECL_1(E16, GPIOG3, SGPS1I1); 442 443 FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16); 444 445 #define SGPS2_DESC SIG_DESC_SET(SCU94, 12) 446 447 #define E17 52 448 SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC); 449 SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); 450 PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1); 451 FUNC_GROUP_DECL(SALT1, E17); 452 453 #define D16 53 454 SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC); 455 SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); 456 PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2); 457 FUNC_GROUP_DECL(SALT2, D16); 458 459 #define D15 54 460 SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC); 461 SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); 462 PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3); 463 FUNC_GROUP_DECL(SALT3, D15); 464 465 #define E14 55 466 SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC); 467 SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); 468 PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4); 469 FUNC_GROUP_DECL(SALT4, E14); 470 471 FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); 472 473 #define UART6_DESC SIG_DESC_SET(SCU90, 7) 474 475 #define A18 56 476 SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); 477 SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC); 478 PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6); 479 480 #define B18 57 481 SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); 482 SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC); 483 PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6); 484 485 #define D17 58 486 SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); 487 SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC); 488 PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6); 489 490 #define C17 59 491 SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); 492 SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC); 493 PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6); 494 495 #define A17 60 496 SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); 497 SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC); 498 PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6); 499 500 #define B17 61 501 SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); 502 SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC); 503 PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6); 504 505 #define A16 62 506 SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC); 507 PIN_DECL_1(A16, GPIOH6, TXD6); 508 509 #define D18 63 510 SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC); 511 PIN_DECL_1(D18, GPIOH7, RXD6); 512 513 FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); 514 515 #define SPI1_DESC \ 516 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 } 517 #define SPI1DEBUG_DESC \ 518 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 } 519 #define SPI1PASSTHRU_DESC \ 520 { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } 521 522 #define C18 64 523 SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 524 SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 525 SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU); 526 PIN_DECL_1(C18, GPIOI0, SYSCS); 527 528 #define E15 65 529 SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 530 SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 531 SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU); 532 PIN_DECL_1(E15, GPIOI1, SYSCK); 533 534 #define B16 66 535 SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 536 SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 537 SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU); 538 PIN_DECL_1(B16, GPIOI2, SYSMOSI); 539 540 #define C16 67 541 SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 542 SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 543 SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU); 544 PIN_DECL_1(C16, GPIOI3, SYSMISO); 545 546 #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) 547 548 #define B15 68 549 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC); 550 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 551 SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 552 SIG_EXPR_LIST_DECL(SPI1CS0, SPI1, 553 SIG_EXPR_PTR(SPI1CS0, SPI1), 554 SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), 555 SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); 556 SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1); 557 SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC); 558 PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS); 559 560 #define C15 69 561 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC); 562 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 563 SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 564 SIG_EXPR_LIST_DECL(SPI1CK, SPI1, 565 SIG_EXPR_PTR(SPI1CK, SPI1), 566 SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), 567 SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); 568 SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1); 569 SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC); 570 PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK); 571 572 #define A14 70 573 SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC); 574 SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 575 SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 576 SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1, 577 SIG_EXPR_PTR(SPI1MOSI, SPI1), 578 SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG), 579 SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU)); 580 SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1); 581 SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC); 582 PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI); 583 584 #define A15 71 585 SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC); 586 SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); 587 SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); 588 SIG_EXPR_LIST_DECL(SPI1MISO, SPI1, 589 SIG_EXPR_PTR(SPI1MISO, SPI1), 590 SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG), 591 SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU)); 592 SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1); 593 SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC); 594 PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO); 595 596 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15); 597 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15); 598 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15); 599 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15); 600 601 #define R2 72 602 SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); 603 PIN_DECL_1(R2, GPIOJ0, SGPMCK); 604 605 #define L2 73 606 SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); 607 PIN_DECL_1(L2, GPIOJ1, SGPMLD); 608 609 #define N3 74 610 SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); 611 PIN_DECL_1(N3, GPIOJ2, SGPMO); 612 613 #define N4 75 614 SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); 615 PIN_DECL_1(N4, GPIOJ3, SGPMI); 616 617 FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4); 618 619 #define N5 76 620 SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); 621 SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); 622 PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5); 623 FUNC_GROUP_DECL(VGAHS, N5); 624 625 #define R4 77 626 SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); 627 SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); 628 PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4); 629 FUNC_GROUP_DECL(VGAVS, R4); 630 631 #define R3 78 632 SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); 633 SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); 634 PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3); 635 FUNC_GROUP_DECL(DDCCLK, R3); 636 637 #define T3 79 638 SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); 639 SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); 640 PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3); 641 FUNC_GROUP_DECL(DDCDAT, T3); 642 643 #define I2C5_DESC SIG_DESC_SET(SCU90, 18) 644 645 #define L3 80 646 SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC); 647 PIN_DECL_1(L3, GPIOK0, SCL5); 648 649 #define L4 81 650 SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC); 651 PIN_DECL_1(L4, GPIOK1, SDA5); 652 653 FUNC_GROUP_DECL(I2C5, L3, L4); 654 655 #define I2C6_DESC SIG_DESC_SET(SCU90, 19) 656 657 #define L1 82 658 SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC); 659 PIN_DECL_1(L1, GPIOK2, SCL6); 660 661 #define N2 83 662 SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC); 663 PIN_DECL_1(N2, GPIOK3, SDA6); 664 665 FUNC_GROUP_DECL(I2C6, L1, N2); 666 667 #define I2C7_DESC SIG_DESC_SET(SCU90, 20) 668 669 #define N1 84 670 SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC); 671 PIN_DECL_1(N1, GPIOK4, SCL7); 672 673 #define P1 85 674 SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC); 675 PIN_DECL_1(P1, GPIOK5, SDA7); 676 677 FUNC_GROUP_DECL(I2C7, N1, P1); 678 679 #define I2C8_DESC SIG_DESC_SET(SCU90, 21) 680 681 #define P2 86 682 SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC); 683 PIN_DECL_1(P2, GPIOK6, SCL8); 684 685 #define R1 87 686 SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC); 687 PIN_DECL_1(R1, GPIOK7, SDA8); 688 689 FUNC_GROUP_DECL(I2C8, P2, R1); 690 691 #define T2 88 692 SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); 693 694 #define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 } 695 #define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 } 696 #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 } 697 #define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 } 698 #define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5) 699 700 #define T1 89 701 #define T1_DESC SIG_DESC_SET(SCU84, 17) 702 SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); 703 SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2); 704 PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1); 705 FUNC_GROUP_DECL(NDCD1, T1); 706 707 #define U1 90 708 #define U1_DESC SIG_DESC_SET(SCU84, 18) 709 SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); 710 SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC); 711 PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1); 712 FUNC_GROUP_DECL(NDSR1, U1); 713 714 #define U2 91 715 #define U2_DESC SIG_DESC_SET(SCU84, 19) 716 SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); 717 SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2); 718 PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1); 719 FUNC_GROUP_DECL(NRI1, U2); 720 721 #define P4 92 722 #define P4_DESC SIG_DESC_SET(SCU84, 20) 723 SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); 724 SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2); 725 PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1); 726 FUNC_GROUP_DECL(NDTR1, P4); 727 728 #define P3 93 729 #define P3_DESC SIG_DESC_SET(SCU84, 21) 730 SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); 731 SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2); 732 PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1); 733 FUNC_GROUP_DECL(NRTS1, P3); 734 735 #define V1 94 736 #define V1_DESC SIG_DESC_SET(SCU84, 22) 737 SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); 738 SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2); 739 PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1); 740 FUNC_GROUP_DECL(TXD1, V1); 741 742 #define W1 95 743 #define W1_DESC SIG_DESC_SET(SCU84, 23) 744 SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); 745 SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2); 746 PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1); 747 FUNC_GROUP_DECL(RXD1, W1); 748 749 #define Y1 96 750 #define Y1_DESC SIG_DESC_SET(SCU84, 24) 751 SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); 752 SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2); 753 PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2); 754 FUNC_GROUP_DECL(NCTS2, Y1); 755 756 #define AB2 97 757 #define AB2_DESC SIG_DESC_SET(SCU84, 25) 758 SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); 759 SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2); 760 PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2); 761 FUNC_GROUP_DECL(NDCD2, AB2); 762 763 #define AA1 98 764 #define AA1_DESC SIG_DESC_SET(SCU84, 26) 765 SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); 766 SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2); 767 PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2); 768 FUNC_GROUP_DECL(NDSR2, AA1); 769 770 #define Y2 99 771 #define Y2_DESC SIG_DESC_SET(SCU84, 27) 772 SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); 773 SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2); 774 PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2); 775 FUNC_GROUP_DECL(NRI2, Y2); 776 777 #define AA2 100 778 #define AA2_DESC SIG_DESC_SET(SCU84, 28) 779 SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); 780 SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2); 781 PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2); 782 FUNC_GROUP_DECL(NDTR2, AA2); 783 784 #define P5 101 785 #define P5_DESC SIG_DESC_SET(SCU84, 29) 786 SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); 787 SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2); 788 PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2); 789 FUNC_GROUP_DECL(NRTS2, P5); 790 791 #define R5 102 792 #define R5_DESC SIG_DESC_SET(SCU84, 30) 793 SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); 794 SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2); 795 PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2); 796 FUNC_GROUP_DECL(TXD2, R5); 797 798 #define T5 103 799 #define T5_DESC SIG_DESC_SET(SCU84, 31) 800 SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); 801 SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2); 802 PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2); 803 FUNC_GROUP_DECL(RXD2, T5); 804 805 #define V2 104 806 #define V2_DESC SIG_DESC_SET(SCU88, 0) 807 SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); 808 SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2); 809 PIN_DECL_2(V2, GPION0, DASHN0, PWM0); 810 FUNC_GROUP_DECL(PWM0, V2); 811 812 #define W2 105 813 #define W2_DESC SIG_DESC_SET(SCU88, 1) 814 SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); 815 SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2); 816 PIN_DECL_2(W2, GPION1, DASHN1, PWM1); 817 FUNC_GROUP_DECL(PWM1, W2); 818 819 #define V3 106 820 #define V3_DESC SIG_DESC_SET(SCU88, 2) 821 SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); 822 SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); 823 SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD); 824 SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2); 825 PIN_DECL_2(V3, GPION2, VPIG2, PWM2); 826 FUNC_GROUP_DECL(PWM2, V3); 827 828 #define U3 107 829 #define U3_DESC SIG_DESC_SET(SCU88, 3) 830 SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); 831 SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); 832 SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD); 833 SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2); 834 PIN_DECL_2(U3, GPION3, VPIG3, PWM3); 835 FUNC_GROUP_DECL(PWM3, U3); 836 837 #define W3 108 838 #define W3_DESC SIG_DESC_SET(SCU88, 4) 839 SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); 840 SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); 841 SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD); 842 SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2); 843 PIN_DECL_2(W3, GPION4, VPIG4, PWM4); 844 FUNC_GROUP_DECL(PWM4, W3); 845 846 #define AA3 109 847 #define AA3_DESC SIG_DESC_SET(SCU88, 5) 848 SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); 849 SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); 850 SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD); 851 SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2); 852 PIN_DECL_2(AA3, GPION5, VPIG5, PWM5); 853 FUNC_GROUP_DECL(PWM5, AA3); 854 855 #define Y3 110 856 #define Y3_DESC SIG_DESC_SET(SCU88, 6) 857 SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC); 858 SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2); 859 PIN_DECL_2(Y3, GPION6, VPIG6, PWM6); 860 FUNC_GROUP_DECL(PWM6, Y3); 861 862 #define T4 111 863 #define T4_DESC SIG_DESC_SET(SCU88, 7) 864 SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC); 865 SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2); 866 PIN_DECL_2(T4, GPION7, VPIG7, PWM7); 867 FUNC_GROUP_DECL(PWM7, T4); 868 869 #define U5 112 870 SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), 871 COND2); 872 PIN_DECL_1(U5, GPIOO0, VPIG8); 873 874 #define U4 113 875 SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), 876 COND2); 877 PIN_DECL_1(U4, GPIOO1, VPIG9); 878 879 #define V5 114 880 SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC, 881 SIG_DESC_SET(SCU88, 10)); 882 PIN_DECL_1(V5, GPIOO2, DASHV5); 883 884 #define AB4 115 885 SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC, 886 SIG_DESC_SET(SCU88, 11)); 887 PIN_DECL_1(AB4, GPIOO3, DASHAB4); 888 889 #define AB3 116 890 SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC, 891 SIG_DESC_SET(SCU88, 12), COND2); 892 PIN_DECL_1(AB3, GPIOO4, VPIR2); 893 894 #define Y4 117 895 SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC, 896 SIG_DESC_SET(SCU88, 13), COND2); 897 PIN_DECL_1(Y4, GPIOO5, VPIR3); 898 899 #define AA4 118 900 SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC, 901 SIG_DESC_SET(SCU88, 14), COND2); 902 PIN_DECL_1(AA4, GPIOO6, VPIR4); 903 904 #define W4 119 905 SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC, 906 SIG_DESC_SET(SCU88, 15), COND2); 907 PIN_DECL_1(W4, GPIOO7, VPIR5); 908 909 #define V4 120 910 SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC, 911 SIG_DESC_SET(SCU88, 16), COND2); 912 PIN_DECL_1(V4, GPIOP0, VPIR6); 913 914 #define W5 121 915 SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC, 916 SIG_DESC_SET(SCU88, 17), COND2); 917 PIN_DECL_1(W5, GPIOP1, VPIR7); 918 919 #define AA5 122 920 SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC, 921 SIG_DESC_SET(SCU88, 18), COND2); 922 PIN_DECL_1(AA5, GPIOP2, VPIR8); 923 924 #define AB5 123 925 SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC, 926 SIG_DESC_SET(SCU88, 19), COND2); 927 PIN_DECL_1(AB5, GPIOP3, VPIR9); 928 929 FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3, 930 U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5, 931 AB5); 932 933 #define Y6 124 934 SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), 935 SIG_DESC_SET(SCU88, 20)); 936 PIN_DECL_1(Y6, GPIOP4, DASHY6); 937 938 #define Y5 125 939 SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), 940 SIG_DESC_SET(SCU88, 21)); 941 PIN_DECL_1(Y5, GPIOP5, DASHY5); 942 943 #define W6 126 944 SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), 945 SIG_DESC_SET(SCU88, 22)); 946 PIN_DECL_1(W6, GPIOP6, DASHW6); 947 948 #define V6 127 949 SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), 950 SIG_DESC_SET(SCU88, 23)); 951 PIN_DECL_1(V6, GPIOP7, DASHV6); 952 953 #define I2C3_DESC SIG_DESC_SET(SCU90, 16) 954 955 #define A11 128 956 SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC); 957 PIN_DECL_1(A11, GPIOQ0, SCL3); 958 959 #define A10 129 960 SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC); 961 PIN_DECL_1(A10, GPIOQ1, SDA3); 962 963 FUNC_GROUP_DECL(I2C3, A11, A10); 964 965 #define I2C4_DESC SIG_DESC_SET(SCU90, 17) 966 967 #define A9 130 968 SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC); 969 PIN_DECL_1(A9, GPIOQ2, SCL4); 970 971 #define B9 131 972 SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC); 973 PIN_DECL_1(B9, GPIOQ3, SDA4); 974 975 FUNC_GROUP_DECL(I2C4, A9, B9); 976 977 #define I2C14_DESC SIG_DESC_SET(SCU90, 27) 978 979 #define N21 132 980 SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC); 981 PIN_DECL_1(N21, GPIOQ4, SCL14); 982 983 #define N22 133 984 SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC); 985 PIN_DECL_1(N22, GPIOQ5, SDA14); 986 987 FUNC_GROUP_DECL(I2C14, N21, N22); 988 989 #define B10 134 990 SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1)); 991 992 #define N20 135 993 SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29)); 994 995 #define AA19 136 996 SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2); 997 998 #define T19 137 999 SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2); 1000 1001 #define T17 138 1002 SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2); 1003 1004 #define Y19 139 1005 SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2); 1006 1007 #define W19 140 1008 SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2); 1009 1010 #define V19 141 1011 SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2); 1012 1013 #define D8 142 1014 SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); 1015 PIN_DECL_1(D8, GPIOR6, MDC1); 1016 1017 #define E10 143 1018 SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); 1019 PIN_DECL_1(E10, GPIOR7, MDIO1); 1020 1021 FUNC_GROUP_DECL(MDIO1, D8, E10); 1022 1023 #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } 1024 #define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 } 1025 #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 } 1026 #define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 } 1027 1028 #define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7) 1029 1030 #define V20 144 1031 #define V20_DESC SIG_DESC_SET(SCU8C, 0) 1032 SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1033 SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1034 SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1035 SIG_EXPR_LIST_DECL(VPOB2, VPO, 1036 SIG_EXPR_PTR(VPOB2, VPO), 1037 SIG_EXPR_PTR(VPOB2, VPOOFF1), 1038 SIG_EXPR_PTR(VPOB2, VPOOFF2)); 1039 SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO); 1040 SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC); 1041 PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1); 1042 FUNC_GROUP_DECL(SPI2CS1, V20); 1043 1044 #define U19 145 1045 #define U19_DESC SIG_DESC_SET(SCU8C, 1) 1046 SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1047 SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1048 SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1049 SIG_EXPR_LIST_DECL(VPOB3, VPO, 1050 SIG_EXPR_PTR(VPOB3, VPO), 1051 SIG_EXPR_PTR(VPOB3, VPOOFF1), 1052 SIG_EXPR_PTR(VPOB3, VPOOFF2)); 1053 SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO); 1054 SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC); 1055 PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT); 1056 FUNC_GROUP_DECL(BMCINT, U19); 1057 1058 #define R18 146 1059 #define R18_DESC SIG_DESC_SET(SCU8C, 2) 1060 SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1061 SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1062 SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1063 SIG_EXPR_LIST_DECL(VPOB4, VPO, 1064 SIG_EXPR_PTR(VPOB4, VPO), 1065 SIG_EXPR_PTR(VPOB4, VPOOFF1), 1066 SIG_EXPR_PTR(VPOB4, VPOOFF2)); 1067 SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO); 1068 SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC); 1069 PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5); 1070 FUNC_GROUP_DECL(SALT5, R18); 1071 1072 #define P18 147 1073 #define P18_DESC SIG_DESC_SET(SCU8C, 3) 1074 SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1075 SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1076 SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1077 SIG_EXPR_LIST_DECL(VPOB5, VPO, 1078 SIG_EXPR_PTR(VPOB5, VPO), 1079 SIG_EXPR_PTR(VPOB5, VPOOFF1), 1080 SIG_EXPR_PTR(VPOB5, VPOOFF2)); 1081 SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO); 1082 SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC); 1083 PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6); 1084 FUNC_GROUP_DECL(SALT6, P18); 1085 1086 #define R19 148 1087 #define R19_DESC SIG_DESC_SET(SCU8C, 4) 1088 SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1089 SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1090 SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1091 SIG_EXPR_LIST_DECL(VPOB6, VPO, 1092 SIG_EXPR_PTR(VPOB6, VPO), 1093 SIG_EXPR_PTR(VPOB6, VPOOFF1), 1094 SIG_EXPR_PTR(VPOB6, VPOOFF2)); 1095 SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO); 1096 PIN_DECL_1(R19, GPIOS4, VPOB6); 1097 1098 #define W20 149 1099 #define W20_DESC SIG_DESC_SET(SCU8C, 5) 1100 SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1101 SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1102 SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1103 SIG_EXPR_LIST_DECL(VPOB7, VPO, 1104 SIG_EXPR_PTR(VPOB7, VPO), 1105 SIG_EXPR_PTR(VPOB7, VPOOFF1), 1106 SIG_EXPR_PTR(VPOB7, VPOOFF2)); 1107 SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO); 1108 PIN_DECL_1(W20, GPIOS5, VPOB7); 1109 1110 #define U20 150 1111 #define U20_DESC SIG_DESC_SET(SCU8C, 6) 1112 SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1113 SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1114 SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1115 SIG_EXPR_LIST_DECL(VPOB8, VPO, 1116 SIG_EXPR_PTR(VPOB8, VPO), 1117 SIG_EXPR_PTR(VPOB8, VPOOFF1), 1118 SIG_EXPR_PTR(VPOB8, VPOOFF2)); 1119 SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO); 1120 PIN_DECL_1(U20, GPIOS6, VPOB8); 1121 1122 #define AA20 151 1123 #define AA20_DESC SIG_DESC_SET(SCU8C, 7) 1124 SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1125 SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1126 SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1127 SIG_EXPR_LIST_DECL(VPOB9, VPO, 1128 SIG_EXPR_PTR(VPOB9, VPO), 1129 SIG_EXPR_PTR(VPOB9, VPOOFF1), 1130 SIG_EXPR_PTR(VPOB9, VPOOFF2)); 1131 SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO); 1132 PIN_DECL_1(AA20, GPIOS7, VPOB9); 1133 1134 /* RGMII1/RMII1 */ 1135 1136 #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) 1137 #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) 1138 1139 #define B5 152 1140 SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); 1141 SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC, 1142 SIG_DESC_SET(SCU48, 29)); 1143 SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1); 1144 PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO), 1145 SIG_EXPR_LIST_PTR(B5, RGMII1TXCK)); 1146 1147 #define E9 153 1148 SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); 1149 SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC); 1150 SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1); 1151 PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN), 1152 SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL)); 1153 1154 #define F9 154 1155 SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); 1156 SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC); 1157 SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1); 1158 PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0), 1159 SIG_EXPR_LIST_PTR(F9, RGMII1TXD0)); 1160 1161 #define A5 155 1162 SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); 1163 SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC); 1164 SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1); 1165 PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1), 1166 SIG_EXPR_LIST_PTR(A5, RGMII1TXD1)); 1167 1168 #define E7 156 1169 SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); 1170 SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC); 1171 SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1); 1172 PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0), 1173 SIG_EXPR_LIST_PTR(E7, RGMII1TXD2)); 1174 1175 #define D7 157 1176 SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); 1177 SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC); 1178 SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1); 1179 PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1), 1180 SIG_EXPR_LIST_PTR(D7, RGMII1TXD3)); 1181 1182 #define B2 158 1183 SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); 1184 SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC, 1185 SIG_DESC_SET(SCU48, 30)); 1186 SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2); 1187 PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO), 1188 SIG_EXPR_LIST_PTR(B2, RGMII2TXCK)); 1189 1190 #define B1 159 1191 SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); 1192 SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC); 1193 SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2); 1194 PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN), 1195 SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL)); 1196 1197 #define A2 160 1198 SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); 1199 SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC); 1200 SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2); 1201 PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0), 1202 SIG_EXPR_LIST_PTR(A2, RGMII2TXD0)); 1203 1204 #define B3 161 1205 SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); 1206 SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC); 1207 SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2); 1208 PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1), 1209 SIG_EXPR_LIST_PTR(B3, RGMII2TXD1)); 1210 1211 #define D5 162 1212 SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); 1213 SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC); 1214 SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2); 1215 PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0), 1216 SIG_EXPR_LIST_PTR(D5, RGMII2TXD2)); 1217 1218 #define D4 163 1219 SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); 1220 SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC); 1221 SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2); 1222 PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1), 1223 SIG_EXPR_LIST_PTR(D4, RGMII2TXD3)); 1224 1225 #define B4 164 1226 SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); 1227 SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC); 1228 SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1); 1229 PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI), 1230 SIG_EXPR_LIST_PTR(B4, RGMII1RXCK)); 1231 1232 #define A4 165 1233 SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); 1234 SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC); 1235 SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1); 1236 PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2), 1237 SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL)); 1238 1239 #define A3 166 1240 SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); 1241 SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC); 1242 SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1); 1243 PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0), 1244 SIG_EXPR_LIST_PTR(A3, RGMII1RXD0)); 1245 1246 #define D6 167 1247 SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); 1248 SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC); 1249 SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1); 1250 PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1), 1251 SIG_EXPR_LIST_PTR(D6, RGMII1RXD1)); 1252 1253 #define C5 168 1254 SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); 1255 SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC); 1256 SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1); 1257 PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV), 1258 SIG_EXPR_LIST_PTR(C5, RGMII1RXD2)); 1259 1260 #define C4 169 1261 SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); 1262 SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC); 1263 SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1); 1264 PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER), 1265 SIG_EXPR_LIST_PTR(C4, RGMII1RXD3)); 1266 1267 FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7); 1268 FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5); 1269 1270 #define C2 170 1271 SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); 1272 SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC); 1273 SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2); 1274 PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI), 1275 SIG_EXPR_LIST_PTR(C2, RGMII2RXCK)); 1276 1277 #define C1 171 1278 SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); 1279 SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC); 1280 SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2); 1281 PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2), 1282 SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL)); 1283 1284 #define C3 172 1285 SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); 1286 SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC); 1287 SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2); 1288 PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0), 1289 SIG_EXPR_LIST_PTR(C3, RGMII2RXD0)); 1290 1291 #define D1 173 1292 SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); 1293 SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC); 1294 SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2); 1295 PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1), 1296 SIG_EXPR_LIST_PTR(D1, RGMII2RXD1)); 1297 1298 #define D2 174 1299 SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); 1300 SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC); 1301 SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2); 1302 PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV), 1303 SIG_EXPR_LIST_PTR(D2, RGMII2RXD2)); 1304 1305 #define E6 175 1306 SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); 1307 SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC); 1308 SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2); 1309 PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER), 1310 SIG_EXPR_LIST_PTR(E6, RGMII2RXD3)); 1311 1312 FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); 1313 FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); 1314 1315 #define F4 176 1316 SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); 1317 SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0); 1318 PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0)); 1319 FUNC_GROUP_DECL(ADC0, F4); 1320 1321 #define F5 177 1322 SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); 1323 SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1); 1324 PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1)); 1325 FUNC_GROUP_DECL(ADC1, F5); 1326 1327 #define E2 178 1328 SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); 1329 SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2); 1330 PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2)); 1331 FUNC_GROUP_DECL(ADC2, E2); 1332 1333 #define E1 179 1334 SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); 1335 SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3); 1336 PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3)); 1337 FUNC_GROUP_DECL(ADC3, E1); 1338 1339 #define F3 180 1340 SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); 1341 SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4); 1342 PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4)); 1343 FUNC_GROUP_DECL(ADC4, F3); 1344 1345 #define E3 181 1346 SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); 1347 SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5); 1348 PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5)); 1349 FUNC_GROUP_DECL(ADC5, E3); 1350 1351 #define G5 182 1352 SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); 1353 SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6); 1354 PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6)); 1355 FUNC_GROUP_DECL(ADC6, G5); 1356 1357 #define G4 183 1358 SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); 1359 SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7); 1360 PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7)); 1361 FUNC_GROUP_DECL(ADC7, G4); 1362 1363 #define F2 184 1364 SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); 1365 SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8); 1366 PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8)); 1367 FUNC_GROUP_DECL(ADC8, F2); 1368 1369 #define G3 185 1370 SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); 1371 SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9); 1372 PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9)); 1373 FUNC_GROUP_DECL(ADC9, G3); 1374 1375 #define G2 186 1376 SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); 1377 SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10); 1378 PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10)); 1379 FUNC_GROUP_DECL(ADC10, G2); 1380 1381 #define F1 187 1382 SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); 1383 SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11); 1384 PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11)); 1385 FUNC_GROUP_DECL(ADC11, F1); 1386 1387 #define H5 188 1388 SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); 1389 SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12); 1390 PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12)); 1391 FUNC_GROUP_DECL(ADC12, H5); 1392 1393 #define G1 189 1394 SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); 1395 SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13); 1396 PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13)); 1397 FUNC_GROUP_DECL(ADC13, G1); 1398 1399 #define H3 190 1400 SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); 1401 SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14); 1402 PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14)); 1403 FUNC_GROUP_DECL(ADC14, H3); 1404 1405 #define H4 191 1406 SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); 1407 SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15); 1408 PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15)); 1409 FUNC_GROUP_DECL(ADC15, H4); 1410 1411 #define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19) 1412 1413 #define R22 192 1414 SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); 1415 SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC); 1416 SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI); 1417 SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); 1418 PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22); 1419 FUNC_GROUP_DECL(SIOS3, R22); 1420 1421 #define R21 193 1422 SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); 1423 SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC); 1424 SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI); 1425 SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); 1426 PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21); 1427 FUNC_GROUP_DECL(SIOS5, R21); 1428 1429 #define P22 194 1430 SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); 1431 SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC); 1432 SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI); 1433 SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); 1434 PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22); 1435 FUNC_GROUP_DECL(SIOPWREQ, P22); 1436 1437 #define P21 195 1438 SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); 1439 SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC); 1440 SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI); 1441 SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); 1442 PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21); 1443 FUNC_GROUP_DECL(SIOONCTRL, P21); 1444 1445 #define M18 196 1446 SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12)); 1447 1448 #define M19 197 1449 SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13)); 1450 1451 #define M20 198 1452 SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14)); 1453 1454 #define P20 199 1455 SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15)); 1456 1457 #define PNOR_DESC SIG_DESC_SET(SCU90, 31) 1458 1459 #define Y20 200 1460 #define Y20_DESC SIG_DESC_SET(SCUA4, 16) 1461 SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1462 SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1463 SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1464 SIG_EXPR_LIST_DECL(VPOG2, VPO, 1465 SIG_EXPR_PTR(VPOG2, VPO), 1466 SIG_EXPR_PTR(VPOG2, VPOOFF1), 1467 SIG_EXPR_PTR(VPOG2, VPOOFF2)); 1468 SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO); 1469 SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC); 1470 SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC); 1471 SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI); 1472 SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC); 1473 SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0); 1474 PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI), 1475 SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0)); 1476 FUNC_GROUP_DECL(SIOPBI, Y20); 1477 1478 #define AB20 201 1479 #define AB20_DESC SIG_DESC_SET(SCUA4, 17) 1480 SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1481 SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1482 SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1483 SIG_EXPR_LIST_DECL(VPOG3, VPO, 1484 SIG_EXPR_PTR(VPOG3, VPO), 1485 SIG_EXPR_PTR(VPOG3, VPOOFF1), 1486 SIG_EXPR_PTR(VPOG3, VPOOFF2)); 1487 SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO); 1488 SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC); 1489 SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC); 1490 SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI); 1491 SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC); 1492 SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1); 1493 PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3), 1494 SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1), 1495 SIG_EXPR_LIST_PTR(AB20, GPIOZ1)); 1496 FUNC_GROUP_DECL(SIOPWRGD, AB20); 1497 1498 #define AB21 202 1499 #define AB21_DESC SIG_DESC_SET(SCUA4, 18) 1500 SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1501 SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1502 SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1503 SIG_EXPR_LIST_DECL(VPOG4, VPO, 1504 SIG_EXPR_PTR(VPOG4, VPO), 1505 SIG_EXPR_PTR(VPOG4, VPOOFF1), 1506 SIG_EXPR_PTR(VPOG4, VPOOFF2)); 1507 SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO); 1508 SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC); 1509 SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC); 1510 SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI); 1511 SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC); 1512 SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2); 1513 PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4), 1514 SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2), 1515 SIG_EXPR_LIST_PTR(AB21, GPIOZ2)); 1516 FUNC_GROUP_DECL(SIOPBO, AB21); 1517 1518 #define AA21 203 1519 #define AA21_DESC SIG_DESC_SET(SCUA4, 19) 1520 SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1521 SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1522 SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1523 SIG_EXPR_LIST_DECL(VPOG5, VPO, 1524 SIG_EXPR_PTR(VPOG5, VPO), 1525 SIG_EXPR_PTR(VPOG5, VPOOFF1), 1526 SIG_EXPR_PTR(VPOG5, VPOOFF2)); 1527 SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO); 1528 SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC); 1529 SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC); 1530 SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI); 1531 SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC); 1532 SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3); 1533 PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5), 1534 SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3), 1535 SIG_EXPR_LIST_PTR(AA21, GPIOZ3)); 1536 FUNC_GROUP_DECL(SIOSCI, AA21); 1537 1538 FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); 1539 1540 /* CRT DVO disabled, configured for single-edge mode */ 1541 #define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 } 1542 1543 /* CRT DVO disabled, configured for dual-edge mode */ 1544 #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 } 1545 1546 /* CRT DVO enabled, configured for single-edge mode */ 1547 #define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 } 1548 1549 /* CRT DVO enabled, configured for dual-edge mode */ 1550 #define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 } 1551 1552 #define U21 204 1553 #define U21_DESC SIG_DESC_SET(SCUA4, 20) 1554 SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1555 SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1556 SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1557 SIG_EXPR_LIST_DECL(VPOG6, VPO, 1558 SIG_EXPR_PTR(VPOG6, VPO), 1559 SIG_EXPR_PTR(VPOG6, VPOOFF1), 1560 SIG_EXPR_PTR(VPOG6, VPOOFF2)); 1561 SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO); 1562 SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC); 1563 PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4); 1564 1565 #define W22 205 1566 #define W22_DESC SIG_DESC_SET(SCUA4, 21) 1567 SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1568 SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1569 SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1570 SIG_EXPR_LIST_DECL(VPOG7, VPO, 1571 SIG_EXPR_PTR(VPOG7, VPO), 1572 SIG_EXPR_PTR(VPOG7, VPOOFF1), 1573 SIG_EXPR_PTR(VPOG7, VPOOFF2)); 1574 SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO); 1575 SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC); 1576 PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5); 1577 1578 #define V22 206 1579 #define V22_DESC SIG_DESC_SET(SCUA4, 22) 1580 SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1581 SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1582 SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1583 SIG_EXPR_LIST_DECL(VPOG8, VPO, 1584 SIG_EXPR_PTR(VPOG8, VPO), 1585 SIG_EXPR_PTR(VPOG8, VPOOFF1), 1586 SIG_EXPR_PTR(VPOG8, VPOOFF2)); 1587 SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO); 1588 SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC); 1589 PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6); 1590 1591 #define W21 207 1592 #define W21_DESC SIG_DESC_SET(SCUA4, 23) 1593 SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1594 SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1595 SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1596 SIG_EXPR_LIST_DECL(VPOG9, VPO, 1597 SIG_EXPR_PTR(VPOG9, VPO), 1598 SIG_EXPR_PTR(VPOG9, VPOOFF1), 1599 SIG_EXPR_PTR(VPOG9, VPOOFF2)); 1600 SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO); 1601 SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC); 1602 PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7); 1603 1604 #define Y21 208 1605 #define Y21_DESC SIG_DESC_SET(SCUA4, 24) 1606 SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1607 SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1608 SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1609 SIG_EXPR_LIST_DECL(VPOR2, VPO, 1610 SIG_EXPR_PTR(VPOR2, VPO), 1611 SIG_EXPR_PTR(VPOR2, VPOOFF1), 1612 SIG_EXPR_PTR(VPOR2, VPOOFF2)); 1613 SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO); 1614 SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC); 1615 SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC); 1616 SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0); 1617 PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7), 1618 SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0)); 1619 FUNC_GROUP_DECL(SALT7, Y21); 1620 1621 #define V21 209 1622 #define V21_DESC SIG_DESC_SET(SCUA4, 25) 1623 SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1624 SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1625 SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1626 SIG_EXPR_LIST_DECL(VPOR3, VPO, 1627 SIG_EXPR_PTR(VPOR3, VPO), 1628 SIG_EXPR_PTR(VPOR3, VPOOFF1), 1629 SIG_EXPR_PTR(VPOR3, VPOOFF2)); 1630 SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO); 1631 SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC); 1632 SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC); 1633 SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1); 1634 PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8), 1635 SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1)); 1636 FUNC_GROUP_DECL(SALT8, V21); 1637 1638 #define Y22 210 1639 #define Y22_DESC SIG_DESC_SET(SCUA4, 26) 1640 SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1641 SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1642 SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1643 SIG_EXPR_LIST_DECL(VPOR4, VPO, 1644 SIG_EXPR_PTR(VPOR4, VPO), 1645 SIG_EXPR_PTR(VPOR4, VPOOFF1), 1646 SIG_EXPR_PTR(VPOR4, VPOOFF2)); 1647 SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO); 1648 SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC); 1649 SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC); 1650 SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2); 1651 PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9), 1652 SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2)); 1653 FUNC_GROUP_DECL(SALT9, Y22); 1654 1655 #define AA22 211 1656 #define AA22_DESC SIG_DESC_SET(SCUA4, 27) 1657 SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1658 SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1659 SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1660 SIG_EXPR_LIST_DECL(VPOR5, VPO, 1661 SIG_EXPR_PTR(VPOR5, VPO), 1662 SIG_EXPR_PTR(VPOR5, VPOOFF1), 1663 SIG_EXPR_PTR(VPOR5, VPOOFF2)); 1664 SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO); 1665 SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC); 1666 SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC); 1667 SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3); 1668 PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5), 1669 SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3), 1670 SIG_EXPR_LIST_PTR(AA22, GPIOAA3)); 1671 FUNC_GROUP_DECL(SALT10, AA22); 1672 1673 #define U22 212 1674 #define U22_DESC SIG_DESC_SET(SCUA4, 28) 1675 SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1676 SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1677 SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1678 SIG_EXPR_LIST_DECL(VPOR6, VPO, 1679 SIG_EXPR_PTR(VPOR6, VPO), 1680 SIG_EXPR_PTR(VPOR6, VPOOFF1), 1681 SIG_EXPR_PTR(VPOR6, VPOOFF2)); 1682 SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO); 1683 SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC); 1684 SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC); 1685 SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4); 1686 PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11), 1687 SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4)); 1688 FUNC_GROUP_DECL(SALT11, U22); 1689 1690 #define T20 213 1691 #define T20_DESC SIG_DESC_SET(SCUA4, 29) 1692 SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1693 SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1694 SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1695 SIG_EXPR_LIST_DECL(VPOR7, VPO, 1696 SIG_EXPR_PTR(VPOR7, VPO), 1697 SIG_EXPR_PTR(VPOR7, VPOOFF1), 1698 SIG_EXPR_PTR(VPOR7, VPOOFF2)); 1699 SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO); 1700 SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC); 1701 SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC); 1702 SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5); 1703 PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12), 1704 SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5)); 1705 FUNC_GROUP_DECL(SALT12, T20); 1706 1707 #define N18 214 1708 #define N18_DESC SIG_DESC_SET(SCUA4, 30) 1709 SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1710 SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1711 SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1712 SIG_EXPR_LIST_DECL(VPOR8, VPO, 1713 SIG_EXPR_PTR(VPOR8, VPO), 1714 SIG_EXPR_PTR(VPOR8, VPOOFF1), 1715 SIG_EXPR_PTR(VPOR8, VPOOFF2)); 1716 SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO); 1717 SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC); 1718 SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC); 1719 SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6); 1720 PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13), 1721 SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6)); 1722 FUNC_GROUP_DECL(SALT13, N18); 1723 1724 #define P19 215 1725 #define P19_DESC SIG_DESC_SET(SCUA4, 31) 1726 SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); 1727 SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); 1728 SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); 1729 SIG_EXPR_LIST_DECL(VPOR9, VPO, 1730 SIG_EXPR_PTR(VPOR9, VPO), 1731 SIG_EXPR_PTR(VPOR9, VPOOFF1), 1732 SIG_EXPR_PTR(VPOR9, VPOOFF2)); 1733 SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO); 1734 SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC); 1735 SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC); 1736 SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7); 1737 PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14), 1738 SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7)); 1739 FUNC_GROUP_DECL(SALT14, P19); 1740 1741 #define N19 216 1742 #define N19_DESC SIG_DESC_SET(SCUA8, 0) 1743 SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1744 SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1745 SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1746 SIG_EXPR_LIST_DECL(VPODE, VPO, 1747 SIG_EXPR_PTR(VPODE, VPO), 1748 SIG_EXPR_PTR(VPODE, VPOOFF1), 1749 SIG_EXPR_PTR(VPODE, VPOOFF2)); 1750 SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO); 1751 SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC); 1752 PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE); 1753 1754 #define T21 217 1755 #define T21_DESC SIG_DESC_SET(SCUA8, 1) 1756 SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1757 SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1758 SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1759 SIG_EXPR_LIST_DECL(VPOHS, VPO, 1760 SIG_EXPR_PTR(VPOHS, VPO), 1761 SIG_EXPR_PTR(VPOHS, VPOOFF1), 1762 SIG_EXPR_PTR(VPOHS, VPOOFF2)); 1763 SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO); 1764 SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC); 1765 PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE); 1766 1767 FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, 1768 AA22, U22, T20, N18, P19, N19, T21); 1769 1770 #define T22 218 1771 #define T22_DESC SIG_DESC_SET(SCUA8, 2) 1772 SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1773 SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1774 SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1775 SIG_EXPR_LIST_DECL(VPOVS, VPO, 1776 SIG_EXPR_PTR(VPOVS, VPO), 1777 SIG_EXPR_PTR(VPOVS, VPOOFF1), 1778 SIG_EXPR_PTR(VPOVS, VPOOFF2)); 1779 SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO); 1780 SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC); 1781 PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1); 1782 FUNC_GROUP_DECL(WDTRST1, T22); 1783 1784 #define R20 219 1785 #define R20_DESC SIG_DESC_SET(SCUA8, 3) 1786 SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); 1787 SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); 1788 SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); 1789 SIG_EXPR_LIST_DECL(VPOCLK, VPO, 1790 SIG_EXPR_PTR(VPOCLK, VPO), 1791 SIG_EXPR_PTR(VPOCLK, VPOOFF1), 1792 SIG_EXPR_PTR(VPOCLK, VPOOFF2)); 1793 SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO); 1794 SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC); 1795 PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2); 1796 FUNC_GROUP_DECL(WDTRST2, R20); 1797 1798 FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, 1799 AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20, 1800 N18, P19, N19, T21, T22, R20); 1801 1802 #define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25) 1803 1804 #define G21 224 1805 SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC); 1806 SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); 1807 PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0); 1808 FUNC_GROUP_DECL(LAD0, G21); 1809 1810 #define G20 225 1811 SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC); 1812 SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); 1813 PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1); 1814 FUNC_GROUP_DECL(LAD1, G20); 1815 1816 #define D22 226 1817 SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC); 1818 SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); 1819 PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2); 1820 FUNC_GROUP_DECL(LAD2, D22); 1821 1822 #define E22 227 1823 SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC); 1824 SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); 1825 PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3); 1826 FUNC_GROUP_DECL(LAD3, E22); 1827 1828 #define C22 228 1829 SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC); 1830 SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); 1831 PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK); 1832 FUNC_GROUP_DECL(LCLK, C22); 1833 1834 #define F21 229 1835 SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC); 1836 SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); 1837 PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME); 1838 FUNC_GROUP_DECL(LFRAME, F21); 1839 1840 #define F22 230 1841 SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC); 1842 SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); 1843 PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ); 1844 FUNC_GROUP_DECL(LSIRQ, F22); 1845 1846 #define G22 231 1847 SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC); 1848 SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); 1849 PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST); 1850 FUNC_GROUP_DECL(LPCRST, G22); 1851 1852 FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); 1853 1854 #define A7 232 1855 SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); 1856 SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); 1857 PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP)); 1858 1859 #define A8 233 1860 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); 1861 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); 1862 PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN)); 1863 1864 FUNC_GROUP_DECL(USB2AH, A7, A8); 1865 FUNC_GROUP_DECL(USB2AD, A7, A8); 1866 1867 #define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 } 1868 #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 } 1869 #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 } 1870 #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 } 1871 1872 #define B6 234 1873 SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC); 1874 SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC); 1875 SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC); 1876 SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC); 1877 SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH, 1878 SIG_EXPR_PTR(USB2BHDP1, USB2BH), 1879 SIG_EXPR_PTR(USB2BHDP2, USB2BH)); 1880 SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH); 1881 PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP), 1882 SIG_EXPR_LIST_PTR(B6, USB2BHDP)); 1883 1884 #define A6 235 1885 SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC); 1886 SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC); 1887 SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC); 1888 SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC); 1889 SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH, 1890 SIG_EXPR_PTR(USB2BHDN1, USB2BH), 1891 SIG_EXPR_PTR(USB2BHDN2, USB2BH)); 1892 SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH); 1893 PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN), 1894 SIG_EXPR_LIST_PTR(A6, USB2BHDN)); 1895 1896 FUNC_GROUP_DECL(USB11BHID, B6, A6); 1897 FUNC_GROUP_DECL(USB2BD, B6, A6); 1898 FUNC_GROUP_DECL(USB2BH, B6, A6); 1899 1900 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ 1901 1902 static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { 1903 ASPEED_PINCTRL_PIN(A10), 1904 ASPEED_PINCTRL_PIN(A11), 1905 ASPEED_PINCTRL_PIN(A12), 1906 ASPEED_PINCTRL_PIN(A13), 1907 ASPEED_PINCTRL_PIN(A14), 1908 ASPEED_PINCTRL_PIN(A15), 1909 ASPEED_PINCTRL_PIN(A16), 1910 ASPEED_PINCTRL_PIN(A17), 1911 ASPEED_PINCTRL_PIN(A18), 1912 ASPEED_PINCTRL_PIN(A19), 1913 ASPEED_PINCTRL_PIN(A2), 1914 ASPEED_PINCTRL_PIN(A20), 1915 ASPEED_PINCTRL_PIN(A21), 1916 ASPEED_PINCTRL_PIN(A3), 1917 ASPEED_PINCTRL_PIN(A4), 1918 ASPEED_PINCTRL_PIN(A5), 1919 ASPEED_PINCTRL_PIN(A6), 1920 ASPEED_PINCTRL_PIN(A7), 1921 ASPEED_PINCTRL_PIN(A8), 1922 ASPEED_PINCTRL_PIN(A9), 1923 ASPEED_PINCTRL_PIN(AA1), 1924 ASPEED_PINCTRL_PIN(AA19), 1925 ASPEED_PINCTRL_PIN(AA2), 1926 ASPEED_PINCTRL_PIN(AA20), 1927 ASPEED_PINCTRL_PIN(AA21), 1928 ASPEED_PINCTRL_PIN(AA22), 1929 ASPEED_PINCTRL_PIN(AA3), 1930 ASPEED_PINCTRL_PIN(AA4), 1931 ASPEED_PINCTRL_PIN(AA5), 1932 ASPEED_PINCTRL_PIN(AB2), 1933 ASPEED_PINCTRL_PIN(AB20), 1934 ASPEED_PINCTRL_PIN(AB21), 1935 ASPEED_PINCTRL_PIN(AB3), 1936 ASPEED_PINCTRL_PIN(AB4), 1937 ASPEED_PINCTRL_PIN(AB5), 1938 ASPEED_PINCTRL_PIN(B1), 1939 ASPEED_PINCTRL_PIN(B10), 1940 ASPEED_PINCTRL_PIN(B11), 1941 ASPEED_PINCTRL_PIN(B12), 1942 ASPEED_PINCTRL_PIN(B13), 1943 ASPEED_PINCTRL_PIN(B14), 1944 ASPEED_PINCTRL_PIN(B15), 1945 ASPEED_PINCTRL_PIN(B16), 1946 ASPEED_PINCTRL_PIN(B17), 1947 ASPEED_PINCTRL_PIN(B18), 1948 ASPEED_PINCTRL_PIN(B19), 1949 ASPEED_PINCTRL_PIN(B2), 1950 ASPEED_PINCTRL_PIN(B20), 1951 ASPEED_PINCTRL_PIN(B21), 1952 ASPEED_PINCTRL_PIN(B22), 1953 ASPEED_PINCTRL_PIN(B3), 1954 ASPEED_PINCTRL_PIN(B4), 1955 ASPEED_PINCTRL_PIN(B5), 1956 ASPEED_PINCTRL_PIN(B6), 1957 ASPEED_PINCTRL_PIN(B9), 1958 ASPEED_PINCTRL_PIN(C1), 1959 ASPEED_PINCTRL_PIN(C11), 1960 ASPEED_PINCTRL_PIN(C12), 1961 ASPEED_PINCTRL_PIN(C13), 1962 ASPEED_PINCTRL_PIN(C14), 1963 ASPEED_PINCTRL_PIN(C15), 1964 ASPEED_PINCTRL_PIN(C16), 1965 ASPEED_PINCTRL_PIN(C17), 1966 ASPEED_PINCTRL_PIN(C18), 1967 ASPEED_PINCTRL_PIN(C19), 1968 ASPEED_PINCTRL_PIN(C2), 1969 ASPEED_PINCTRL_PIN(C20), 1970 ASPEED_PINCTRL_PIN(C21), 1971 ASPEED_PINCTRL_PIN(C22), 1972 ASPEED_PINCTRL_PIN(C3), 1973 ASPEED_PINCTRL_PIN(C4), 1974 ASPEED_PINCTRL_PIN(C5), 1975 ASPEED_PINCTRL_PIN(D1), 1976 ASPEED_PINCTRL_PIN(D10), 1977 ASPEED_PINCTRL_PIN(D13), 1978 ASPEED_PINCTRL_PIN(D14), 1979 ASPEED_PINCTRL_PIN(D15), 1980 ASPEED_PINCTRL_PIN(D16), 1981 ASPEED_PINCTRL_PIN(D17), 1982 ASPEED_PINCTRL_PIN(D18), 1983 ASPEED_PINCTRL_PIN(D19), 1984 ASPEED_PINCTRL_PIN(D2), 1985 ASPEED_PINCTRL_PIN(D20), 1986 ASPEED_PINCTRL_PIN(D21), 1987 ASPEED_PINCTRL_PIN(D22), 1988 ASPEED_PINCTRL_PIN(D4), 1989 ASPEED_PINCTRL_PIN(D5), 1990 ASPEED_PINCTRL_PIN(D6), 1991 ASPEED_PINCTRL_PIN(D7), 1992 ASPEED_PINCTRL_PIN(D8), 1993 ASPEED_PINCTRL_PIN(D9), 1994 ASPEED_PINCTRL_PIN(E1), 1995 ASPEED_PINCTRL_PIN(E10), 1996 ASPEED_PINCTRL_PIN(E12), 1997 ASPEED_PINCTRL_PIN(E13), 1998 ASPEED_PINCTRL_PIN(E14), 1999 ASPEED_PINCTRL_PIN(E15), 2000 ASPEED_PINCTRL_PIN(E16), 2001 ASPEED_PINCTRL_PIN(E17), 2002 ASPEED_PINCTRL_PIN(E18), 2003 ASPEED_PINCTRL_PIN(E19), 2004 ASPEED_PINCTRL_PIN(E2), 2005 ASPEED_PINCTRL_PIN(E20), 2006 ASPEED_PINCTRL_PIN(E21), 2007 ASPEED_PINCTRL_PIN(E22), 2008 ASPEED_PINCTRL_PIN(E3), 2009 ASPEED_PINCTRL_PIN(E6), 2010 ASPEED_PINCTRL_PIN(E7), 2011 ASPEED_PINCTRL_PIN(E9), 2012 ASPEED_PINCTRL_PIN(F1), 2013 ASPEED_PINCTRL_PIN(F17), 2014 ASPEED_PINCTRL_PIN(F18), 2015 ASPEED_PINCTRL_PIN(F19), 2016 ASPEED_PINCTRL_PIN(F2), 2017 ASPEED_PINCTRL_PIN(F20), 2018 ASPEED_PINCTRL_PIN(F21), 2019 ASPEED_PINCTRL_PIN(F22), 2020 ASPEED_PINCTRL_PIN(F3), 2021 ASPEED_PINCTRL_PIN(F4), 2022 ASPEED_PINCTRL_PIN(F5), 2023 ASPEED_PINCTRL_PIN(F9), 2024 ASPEED_PINCTRL_PIN(G1), 2025 ASPEED_PINCTRL_PIN(G17), 2026 ASPEED_PINCTRL_PIN(G18), 2027 ASPEED_PINCTRL_PIN(G2), 2028 ASPEED_PINCTRL_PIN(G20), 2029 ASPEED_PINCTRL_PIN(G21), 2030 ASPEED_PINCTRL_PIN(G22), 2031 ASPEED_PINCTRL_PIN(G3), 2032 ASPEED_PINCTRL_PIN(G4), 2033 ASPEED_PINCTRL_PIN(G5), 2034 ASPEED_PINCTRL_PIN(H18), 2035 ASPEED_PINCTRL_PIN(H19), 2036 ASPEED_PINCTRL_PIN(H20), 2037 ASPEED_PINCTRL_PIN(H21), 2038 ASPEED_PINCTRL_PIN(H22), 2039 ASPEED_PINCTRL_PIN(H3), 2040 ASPEED_PINCTRL_PIN(H4), 2041 ASPEED_PINCTRL_PIN(H5), 2042 ASPEED_PINCTRL_PIN(J18), 2043 ASPEED_PINCTRL_PIN(J19), 2044 ASPEED_PINCTRL_PIN(J20), 2045 ASPEED_PINCTRL_PIN(K18), 2046 ASPEED_PINCTRL_PIN(K19), 2047 ASPEED_PINCTRL_PIN(L1), 2048 ASPEED_PINCTRL_PIN(L18), 2049 ASPEED_PINCTRL_PIN(L19), 2050 ASPEED_PINCTRL_PIN(L2), 2051 ASPEED_PINCTRL_PIN(L3), 2052 ASPEED_PINCTRL_PIN(L4), 2053 ASPEED_PINCTRL_PIN(M18), 2054 ASPEED_PINCTRL_PIN(M19), 2055 ASPEED_PINCTRL_PIN(M20), 2056 ASPEED_PINCTRL_PIN(N1), 2057 ASPEED_PINCTRL_PIN(N18), 2058 ASPEED_PINCTRL_PIN(N19), 2059 ASPEED_PINCTRL_PIN(N2), 2060 ASPEED_PINCTRL_PIN(N20), 2061 ASPEED_PINCTRL_PIN(N21), 2062 ASPEED_PINCTRL_PIN(N22), 2063 ASPEED_PINCTRL_PIN(N3), 2064 ASPEED_PINCTRL_PIN(N4), 2065 ASPEED_PINCTRL_PIN(N5), 2066 ASPEED_PINCTRL_PIN(P1), 2067 ASPEED_PINCTRL_PIN(P18), 2068 ASPEED_PINCTRL_PIN(P19), 2069 ASPEED_PINCTRL_PIN(P2), 2070 ASPEED_PINCTRL_PIN(P20), 2071 ASPEED_PINCTRL_PIN(P21), 2072 ASPEED_PINCTRL_PIN(P22), 2073 ASPEED_PINCTRL_PIN(P3), 2074 ASPEED_PINCTRL_PIN(P4), 2075 ASPEED_PINCTRL_PIN(P5), 2076 ASPEED_PINCTRL_PIN(R1), 2077 ASPEED_PINCTRL_PIN(R18), 2078 ASPEED_PINCTRL_PIN(R19), 2079 ASPEED_PINCTRL_PIN(R2), 2080 ASPEED_PINCTRL_PIN(R20), 2081 ASPEED_PINCTRL_PIN(R21), 2082 ASPEED_PINCTRL_PIN(R22), 2083 ASPEED_PINCTRL_PIN(R3), 2084 ASPEED_PINCTRL_PIN(R4), 2085 ASPEED_PINCTRL_PIN(R5), 2086 ASPEED_PINCTRL_PIN(T1), 2087 ASPEED_PINCTRL_PIN(T17), 2088 ASPEED_PINCTRL_PIN(T19), 2089 ASPEED_PINCTRL_PIN(T2), 2090 ASPEED_PINCTRL_PIN(T20), 2091 ASPEED_PINCTRL_PIN(T21), 2092 ASPEED_PINCTRL_PIN(T22), 2093 ASPEED_PINCTRL_PIN(T3), 2094 ASPEED_PINCTRL_PIN(T4), 2095 ASPEED_PINCTRL_PIN(T5), 2096 ASPEED_PINCTRL_PIN(U1), 2097 ASPEED_PINCTRL_PIN(U19), 2098 ASPEED_PINCTRL_PIN(U2), 2099 ASPEED_PINCTRL_PIN(U20), 2100 ASPEED_PINCTRL_PIN(U21), 2101 ASPEED_PINCTRL_PIN(U22), 2102 ASPEED_PINCTRL_PIN(U3), 2103 ASPEED_PINCTRL_PIN(U4), 2104 ASPEED_PINCTRL_PIN(U5), 2105 ASPEED_PINCTRL_PIN(V1), 2106 ASPEED_PINCTRL_PIN(V19), 2107 ASPEED_PINCTRL_PIN(V2), 2108 ASPEED_PINCTRL_PIN(V20), 2109 ASPEED_PINCTRL_PIN(V21), 2110 ASPEED_PINCTRL_PIN(V22), 2111 ASPEED_PINCTRL_PIN(V3), 2112 ASPEED_PINCTRL_PIN(V4), 2113 ASPEED_PINCTRL_PIN(V5), 2114 ASPEED_PINCTRL_PIN(V6), 2115 ASPEED_PINCTRL_PIN(W1), 2116 ASPEED_PINCTRL_PIN(W19), 2117 ASPEED_PINCTRL_PIN(W2), 2118 ASPEED_PINCTRL_PIN(W20), 2119 ASPEED_PINCTRL_PIN(W21), 2120 ASPEED_PINCTRL_PIN(W22), 2121 ASPEED_PINCTRL_PIN(W3), 2122 ASPEED_PINCTRL_PIN(W4), 2123 ASPEED_PINCTRL_PIN(W5), 2124 ASPEED_PINCTRL_PIN(W6), 2125 ASPEED_PINCTRL_PIN(Y1), 2126 ASPEED_PINCTRL_PIN(Y19), 2127 ASPEED_PINCTRL_PIN(Y2), 2128 ASPEED_PINCTRL_PIN(Y20), 2129 ASPEED_PINCTRL_PIN(Y21), 2130 ASPEED_PINCTRL_PIN(Y22), 2131 ASPEED_PINCTRL_PIN(Y3), 2132 ASPEED_PINCTRL_PIN(Y4), 2133 ASPEED_PINCTRL_PIN(Y5), 2134 ASPEED_PINCTRL_PIN(Y6), 2135 }; 2136 2137 static const struct aspeed_pin_group aspeed_g5_groups[] = { 2138 ASPEED_PINCTRL_GROUP(ACPI), 2139 ASPEED_PINCTRL_GROUP(ADC0), 2140 ASPEED_PINCTRL_GROUP(ADC1), 2141 ASPEED_PINCTRL_GROUP(ADC10), 2142 ASPEED_PINCTRL_GROUP(ADC11), 2143 ASPEED_PINCTRL_GROUP(ADC12), 2144 ASPEED_PINCTRL_GROUP(ADC13), 2145 ASPEED_PINCTRL_GROUP(ADC14), 2146 ASPEED_PINCTRL_GROUP(ADC15), 2147 ASPEED_PINCTRL_GROUP(ADC2), 2148 ASPEED_PINCTRL_GROUP(ADC3), 2149 ASPEED_PINCTRL_GROUP(ADC4), 2150 ASPEED_PINCTRL_GROUP(ADC5), 2151 ASPEED_PINCTRL_GROUP(ADC6), 2152 ASPEED_PINCTRL_GROUP(ADC7), 2153 ASPEED_PINCTRL_GROUP(ADC8), 2154 ASPEED_PINCTRL_GROUP(ADC9), 2155 ASPEED_PINCTRL_GROUP(BMCINT), 2156 ASPEED_PINCTRL_GROUP(DDCCLK), 2157 ASPEED_PINCTRL_GROUP(DDCDAT), 2158 ASPEED_PINCTRL_GROUP(ESPI), 2159 ASPEED_PINCTRL_GROUP(FWSPICS1), 2160 ASPEED_PINCTRL_GROUP(FWSPICS2), 2161 ASPEED_PINCTRL_GROUP(GPID0), 2162 ASPEED_PINCTRL_GROUP(GPID2), 2163 ASPEED_PINCTRL_GROUP(GPID4), 2164 ASPEED_PINCTRL_GROUP(GPID6), 2165 ASPEED_PINCTRL_GROUP(GPIE0), 2166 ASPEED_PINCTRL_GROUP(GPIE2), 2167 ASPEED_PINCTRL_GROUP(GPIE4), 2168 ASPEED_PINCTRL_GROUP(GPIE6), 2169 ASPEED_PINCTRL_GROUP(I2C10), 2170 ASPEED_PINCTRL_GROUP(I2C11), 2171 ASPEED_PINCTRL_GROUP(I2C12), 2172 ASPEED_PINCTRL_GROUP(I2C13), 2173 ASPEED_PINCTRL_GROUP(I2C14), 2174 ASPEED_PINCTRL_GROUP(I2C3), 2175 ASPEED_PINCTRL_GROUP(I2C4), 2176 ASPEED_PINCTRL_GROUP(I2C5), 2177 ASPEED_PINCTRL_GROUP(I2C6), 2178 ASPEED_PINCTRL_GROUP(I2C7), 2179 ASPEED_PINCTRL_GROUP(I2C8), 2180 ASPEED_PINCTRL_GROUP(I2C9), 2181 ASPEED_PINCTRL_GROUP(LAD0), 2182 ASPEED_PINCTRL_GROUP(LAD1), 2183 ASPEED_PINCTRL_GROUP(LAD2), 2184 ASPEED_PINCTRL_GROUP(LAD3), 2185 ASPEED_PINCTRL_GROUP(LCLK), 2186 ASPEED_PINCTRL_GROUP(LFRAME), 2187 ASPEED_PINCTRL_GROUP(LPCHC), 2188 ASPEED_PINCTRL_GROUP(LPCPD), 2189 ASPEED_PINCTRL_GROUP(LPCPLUS), 2190 ASPEED_PINCTRL_GROUP(LPCPME), 2191 ASPEED_PINCTRL_GROUP(LPCRST), 2192 ASPEED_PINCTRL_GROUP(LPCSMI), 2193 ASPEED_PINCTRL_GROUP(LSIRQ), 2194 ASPEED_PINCTRL_GROUP(MAC1LINK), 2195 ASPEED_PINCTRL_GROUP(MAC2LINK), 2196 ASPEED_PINCTRL_GROUP(MDIO1), 2197 ASPEED_PINCTRL_GROUP(MDIO2), 2198 ASPEED_PINCTRL_GROUP(NCTS1), 2199 ASPEED_PINCTRL_GROUP(NCTS2), 2200 ASPEED_PINCTRL_GROUP(NCTS3), 2201 ASPEED_PINCTRL_GROUP(NCTS4), 2202 ASPEED_PINCTRL_GROUP(NDCD1), 2203 ASPEED_PINCTRL_GROUP(NDCD2), 2204 ASPEED_PINCTRL_GROUP(NDCD3), 2205 ASPEED_PINCTRL_GROUP(NDCD4), 2206 ASPEED_PINCTRL_GROUP(NDSR1), 2207 ASPEED_PINCTRL_GROUP(NDSR2), 2208 ASPEED_PINCTRL_GROUP(NDSR3), 2209 ASPEED_PINCTRL_GROUP(NDSR4), 2210 ASPEED_PINCTRL_GROUP(NDTR1), 2211 ASPEED_PINCTRL_GROUP(NDTR2), 2212 ASPEED_PINCTRL_GROUP(NDTR3), 2213 ASPEED_PINCTRL_GROUP(NDTR4), 2214 ASPEED_PINCTRL_GROUP(NRI1), 2215 ASPEED_PINCTRL_GROUP(NRI2), 2216 ASPEED_PINCTRL_GROUP(NRI3), 2217 ASPEED_PINCTRL_GROUP(NRI4), 2218 ASPEED_PINCTRL_GROUP(NRTS1), 2219 ASPEED_PINCTRL_GROUP(NRTS2), 2220 ASPEED_PINCTRL_GROUP(NRTS3), 2221 ASPEED_PINCTRL_GROUP(NRTS4), 2222 ASPEED_PINCTRL_GROUP(OSCCLK), 2223 ASPEED_PINCTRL_GROUP(PEWAKE), 2224 ASPEED_PINCTRL_GROUP(PNOR), 2225 ASPEED_PINCTRL_GROUP(PWM0), 2226 ASPEED_PINCTRL_GROUP(PWM1), 2227 ASPEED_PINCTRL_GROUP(PWM2), 2228 ASPEED_PINCTRL_GROUP(PWM3), 2229 ASPEED_PINCTRL_GROUP(PWM4), 2230 ASPEED_PINCTRL_GROUP(PWM5), 2231 ASPEED_PINCTRL_GROUP(PWM6), 2232 ASPEED_PINCTRL_GROUP(PWM7), 2233 ASPEED_PINCTRL_GROUP(RGMII1), 2234 ASPEED_PINCTRL_GROUP(RGMII2), 2235 ASPEED_PINCTRL_GROUP(RMII1), 2236 ASPEED_PINCTRL_GROUP(RMII2), 2237 ASPEED_PINCTRL_GROUP(RXD1), 2238 ASPEED_PINCTRL_GROUP(RXD2), 2239 ASPEED_PINCTRL_GROUP(RXD3), 2240 ASPEED_PINCTRL_GROUP(RXD4), 2241 ASPEED_PINCTRL_GROUP(SALT1), 2242 ASPEED_PINCTRL_GROUP(SALT10), 2243 ASPEED_PINCTRL_GROUP(SALT11), 2244 ASPEED_PINCTRL_GROUP(SALT12), 2245 ASPEED_PINCTRL_GROUP(SALT13), 2246 ASPEED_PINCTRL_GROUP(SALT14), 2247 ASPEED_PINCTRL_GROUP(SALT2), 2248 ASPEED_PINCTRL_GROUP(SALT3), 2249 ASPEED_PINCTRL_GROUP(SALT4), 2250 ASPEED_PINCTRL_GROUP(SALT5), 2251 ASPEED_PINCTRL_GROUP(SALT6), 2252 ASPEED_PINCTRL_GROUP(SALT7), 2253 ASPEED_PINCTRL_GROUP(SALT8), 2254 ASPEED_PINCTRL_GROUP(SALT9), 2255 ASPEED_PINCTRL_GROUP(SCL1), 2256 ASPEED_PINCTRL_GROUP(SCL2), 2257 ASPEED_PINCTRL_GROUP(SD1), 2258 ASPEED_PINCTRL_GROUP(SD2), 2259 ASPEED_PINCTRL_GROUP(SDA1), 2260 ASPEED_PINCTRL_GROUP(SDA2), 2261 ASPEED_PINCTRL_GROUP(SGPM), 2262 ASPEED_PINCTRL_GROUP(SGPS1), 2263 ASPEED_PINCTRL_GROUP(SGPS2), 2264 ASPEED_PINCTRL_GROUP(SIOONCTRL), 2265 ASPEED_PINCTRL_GROUP(SIOPBI), 2266 ASPEED_PINCTRL_GROUP(SIOPBO), 2267 ASPEED_PINCTRL_GROUP(SIOPWREQ), 2268 ASPEED_PINCTRL_GROUP(SIOPWRGD), 2269 ASPEED_PINCTRL_GROUP(SIOS3), 2270 ASPEED_PINCTRL_GROUP(SIOS5), 2271 ASPEED_PINCTRL_GROUP(SIOSCI), 2272 ASPEED_PINCTRL_GROUP(SPI1), 2273 ASPEED_PINCTRL_GROUP(SPI1CS1), 2274 ASPEED_PINCTRL_GROUP(SPI1DEBUG), 2275 ASPEED_PINCTRL_GROUP(SPI1PASSTHRU), 2276 ASPEED_PINCTRL_GROUP(SPI2CK), 2277 ASPEED_PINCTRL_GROUP(SPI2CS0), 2278 ASPEED_PINCTRL_GROUP(SPI2CS1), 2279 ASPEED_PINCTRL_GROUP(SPI2MISO), 2280 ASPEED_PINCTRL_GROUP(SPI2MOSI), 2281 ASPEED_PINCTRL_GROUP(TIMER3), 2282 ASPEED_PINCTRL_GROUP(TIMER4), 2283 ASPEED_PINCTRL_GROUP(TIMER5), 2284 ASPEED_PINCTRL_GROUP(TIMER6), 2285 ASPEED_PINCTRL_GROUP(TIMER7), 2286 ASPEED_PINCTRL_GROUP(TIMER8), 2287 ASPEED_PINCTRL_GROUP(TXD1), 2288 ASPEED_PINCTRL_GROUP(TXD2), 2289 ASPEED_PINCTRL_GROUP(TXD3), 2290 ASPEED_PINCTRL_GROUP(TXD4), 2291 ASPEED_PINCTRL_GROUP(UART6), 2292 ASPEED_PINCTRL_GROUP(USB11BHID), 2293 ASPEED_PINCTRL_GROUP(USB2AD), 2294 ASPEED_PINCTRL_GROUP(USB2AH), 2295 ASPEED_PINCTRL_GROUP(USB2BD), 2296 ASPEED_PINCTRL_GROUP(USB2BH), 2297 ASPEED_PINCTRL_GROUP(USBCKI), 2298 ASPEED_PINCTRL_GROUP(VGABIOSROM), 2299 ASPEED_PINCTRL_GROUP(VGAHS), 2300 ASPEED_PINCTRL_GROUP(VGAVS), 2301 ASPEED_PINCTRL_GROUP(VPI24), 2302 ASPEED_PINCTRL_GROUP(VPO), 2303 ASPEED_PINCTRL_GROUP(WDTRST1), 2304 ASPEED_PINCTRL_GROUP(WDTRST2), 2305 }; 2306 2307 static const struct aspeed_pin_function aspeed_g5_functions[] = { 2308 ASPEED_PINCTRL_FUNC(ACPI), 2309 ASPEED_PINCTRL_FUNC(ADC0), 2310 ASPEED_PINCTRL_FUNC(ADC1), 2311 ASPEED_PINCTRL_FUNC(ADC10), 2312 ASPEED_PINCTRL_FUNC(ADC11), 2313 ASPEED_PINCTRL_FUNC(ADC12), 2314 ASPEED_PINCTRL_FUNC(ADC13), 2315 ASPEED_PINCTRL_FUNC(ADC14), 2316 ASPEED_PINCTRL_FUNC(ADC15), 2317 ASPEED_PINCTRL_FUNC(ADC2), 2318 ASPEED_PINCTRL_FUNC(ADC3), 2319 ASPEED_PINCTRL_FUNC(ADC4), 2320 ASPEED_PINCTRL_FUNC(ADC5), 2321 ASPEED_PINCTRL_FUNC(ADC6), 2322 ASPEED_PINCTRL_FUNC(ADC7), 2323 ASPEED_PINCTRL_FUNC(ADC8), 2324 ASPEED_PINCTRL_FUNC(ADC9), 2325 ASPEED_PINCTRL_FUNC(BMCINT), 2326 ASPEED_PINCTRL_FUNC(DDCCLK), 2327 ASPEED_PINCTRL_FUNC(DDCDAT), 2328 ASPEED_PINCTRL_FUNC(ESPI), 2329 ASPEED_PINCTRL_FUNC(FWSPICS1), 2330 ASPEED_PINCTRL_FUNC(FWSPICS2), 2331 ASPEED_PINCTRL_FUNC(GPID0), 2332 ASPEED_PINCTRL_FUNC(GPID2), 2333 ASPEED_PINCTRL_FUNC(GPID4), 2334 ASPEED_PINCTRL_FUNC(GPID6), 2335 ASPEED_PINCTRL_FUNC(GPIE0), 2336 ASPEED_PINCTRL_FUNC(GPIE2), 2337 ASPEED_PINCTRL_FUNC(GPIE4), 2338 ASPEED_PINCTRL_FUNC(GPIE6), 2339 ASPEED_PINCTRL_FUNC(I2C10), 2340 ASPEED_PINCTRL_FUNC(I2C11), 2341 ASPEED_PINCTRL_FUNC(I2C12), 2342 ASPEED_PINCTRL_FUNC(I2C13), 2343 ASPEED_PINCTRL_FUNC(I2C14), 2344 ASPEED_PINCTRL_FUNC(I2C3), 2345 ASPEED_PINCTRL_FUNC(I2C4), 2346 ASPEED_PINCTRL_FUNC(I2C5), 2347 ASPEED_PINCTRL_FUNC(I2C6), 2348 ASPEED_PINCTRL_FUNC(I2C7), 2349 ASPEED_PINCTRL_FUNC(I2C8), 2350 ASPEED_PINCTRL_FUNC(I2C9), 2351 ASPEED_PINCTRL_FUNC(LAD0), 2352 ASPEED_PINCTRL_FUNC(LAD1), 2353 ASPEED_PINCTRL_FUNC(LAD2), 2354 ASPEED_PINCTRL_FUNC(LAD3), 2355 ASPEED_PINCTRL_FUNC(LCLK), 2356 ASPEED_PINCTRL_FUNC(LFRAME), 2357 ASPEED_PINCTRL_FUNC(LPCHC), 2358 ASPEED_PINCTRL_FUNC(LPCPD), 2359 ASPEED_PINCTRL_FUNC(LPCPLUS), 2360 ASPEED_PINCTRL_FUNC(LPCPME), 2361 ASPEED_PINCTRL_FUNC(LPCRST), 2362 ASPEED_PINCTRL_FUNC(LPCSMI), 2363 ASPEED_PINCTRL_FUNC(LSIRQ), 2364 ASPEED_PINCTRL_FUNC(MAC1LINK), 2365 ASPEED_PINCTRL_FUNC(MAC2LINK), 2366 ASPEED_PINCTRL_FUNC(MDIO1), 2367 ASPEED_PINCTRL_FUNC(MDIO2), 2368 ASPEED_PINCTRL_FUNC(NCTS1), 2369 ASPEED_PINCTRL_FUNC(NCTS2), 2370 ASPEED_PINCTRL_FUNC(NCTS3), 2371 ASPEED_PINCTRL_FUNC(NCTS4), 2372 ASPEED_PINCTRL_FUNC(NDCD1), 2373 ASPEED_PINCTRL_FUNC(NDCD2), 2374 ASPEED_PINCTRL_FUNC(NDCD3), 2375 ASPEED_PINCTRL_FUNC(NDCD4), 2376 ASPEED_PINCTRL_FUNC(NDSR1), 2377 ASPEED_PINCTRL_FUNC(NDSR2), 2378 ASPEED_PINCTRL_FUNC(NDSR3), 2379 ASPEED_PINCTRL_FUNC(NDSR4), 2380 ASPEED_PINCTRL_FUNC(NDTR1), 2381 ASPEED_PINCTRL_FUNC(NDTR2), 2382 ASPEED_PINCTRL_FUNC(NDTR3), 2383 ASPEED_PINCTRL_FUNC(NDTR4), 2384 ASPEED_PINCTRL_FUNC(NRI1), 2385 ASPEED_PINCTRL_FUNC(NRI2), 2386 ASPEED_PINCTRL_FUNC(NRI3), 2387 ASPEED_PINCTRL_FUNC(NRI4), 2388 ASPEED_PINCTRL_FUNC(NRTS1), 2389 ASPEED_PINCTRL_FUNC(NRTS2), 2390 ASPEED_PINCTRL_FUNC(NRTS3), 2391 ASPEED_PINCTRL_FUNC(NRTS4), 2392 ASPEED_PINCTRL_FUNC(OSCCLK), 2393 ASPEED_PINCTRL_FUNC(PEWAKE), 2394 ASPEED_PINCTRL_FUNC(PNOR), 2395 ASPEED_PINCTRL_FUNC(PWM0), 2396 ASPEED_PINCTRL_FUNC(PWM1), 2397 ASPEED_PINCTRL_FUNC(PWM2), 2398 ASPEED_PINCTRL_FUNC(PWM3), 2399 ASPEED_PINCTRL_FUNC(PWM4), 2400 ASPEED_PINCTRL_FUNC(PWM5), 2401 ASPEED_PINCTRL_FUNC(PWM6), 2402 ASPEED_PINCTRL_FUNC(PWM7), 2403 ASPEED_PINCTRL_FUNC(RGMII1), 2404 ASPEED_PINCTRL_FUNC(RGMII2), 2405 ASPEED_PINCTRL_FUNC(RMII1), 2406 ASPEED_PINCTRL_FUNC(RMII2), 2407 ASPEED_PINCTRL_FUNC(RXD1), 2408 ASPEED_PINCTRL_FUNC(RXD2), 2409 ASPEED_PINCTRL_FUNC(RXD3), 2410 ASPEED_PINCTRL_FUNC(RXD4), 2411 ASPEED_PINCTRL_FUNC(SALT1), 2412 ASPEED_PINCTRL_FUNC(SALT10), 2413 ASPEED_PINCTRL_FUNC(SALT11), 2414 ASPEED_PINCTRL_FUNC(SALT12), 2415 ASPEED_PINCTRL_FUNC(SALT13), 2416 ASPEED_PINCTRL_FUNC(SALT14), 2417 ASPEED_PINCTRL_FUNC(SALT2), 2418 ASPEED_PINCTRL_FUNC(SALT3), 2419 ASPEED_PINCTRL_FUNC(SALT4), 2420 ASPEED_PINCTRL_FUNC(SALT5), 2421 ASPEED_PINCTRL_FUNC(SALT6), 2422 ASPEED_PINCTRL_FUNC(SALT7), 2423 ASPEED_PINCTRL_FUNC(SALT8), 2424 ASPEED_PINCTRL_FUNC(SALT9), 2425 ASPEED_PINCTRL_FUNC(SCL1), 2426 ASPEED_PINCTRL_FUNC(SCL2), 2427 ASPEED_PINCTRL_FUNC(SD1), 2428 ASPEED_PINCTRL_FUNC(SD2), 2429 ASPEED_PINCTRL_FUNC(SDA1), 2430 ASPEED_PINCTRL_FUNC(SDA2), 2431 ASPEED_PINCTRL_FUNC(SGPM), 2432 ASPEED_PINCTRL_FUNC(SGPS1), 2433 ASPEED_PINCTRL_FUNC(SGPS2), 2434 ASPEED_PINCTRL_FUNC(SIOONCTRL), 2435 ASPEED_PINCTRL_FUNC(SIOPBI), 2436 ASPEED_PINCTRL_FUNC(SIOPBO), 2437 ASPEED_PINCTRL_FUNC(SIOPWREQ), 2438 ASPEED_PINCTRL_FUNC(SIOPWRGD), 2439 ASPEED_PINCTRL_FUNC(SIOS3), 2440 ASPEED_PINCTRL_FUNC(SIOS5), 2441 ASPEED_PINCTRL_FUNC(SIOSCI), 2442 ASPEED_PINCTRL_FUNC(SPI1), 2443 ASPEED_PINCTRL_FUNC(SPI1CS1), 2444 ASPEED_PINCTRL_FUNC(SPI1DEBUG), 2445 ASPEED_PINCTRL_FUNC(SPI1PASSTHRU), 2446 ASPEED_PINCTRL_FUNC(SPI2CK), 2447 ASPEED_PINCTRL_FUNC(SPI2CS0), 2448 ASPEED_PINCTRL_FUNC(SPI2CS1), 2449 ASPEED_PINCTRL_FUNC(SPI2MISO), 2450 ASPEED_PINCTRL_FUNC(SPI2MOSI), 2451 ASPEED_PINCTRL_FUNC(TIMER3), 2452 ASPEED_PINCTRL_FUNC(TIMER4), 2453 ASPEED_PINCTRL_FUNC(TIMER5), 2454 ASPEED_PINCTRL_FUNC(TIMER6), 2455 ASPEED_PINCTRL_FUNC(TIMER7), 2456 ASPEED_PINCTRL_FUNC(TIMER8), 2457 ASPEED_PINCTRL_FUNC(TXD1), 2458 ASPEED_PINCTRL_FUNC(TXD2), 2459 ASPEED_PINCTRL_FUNC(TXD3), 2460 ASPEED_PINCTRL_FUNC(TXD4), 2461 ASPEED_PINCTRL_FUNC(UART6), 2462 ASPEED_PINCTRL_FUNC(USB11BHID), 2463 ASPEED_PINCTRL_FUNC(USB2AD), 2464 ASPEED_PINCTRL_FUNC(USB2AH), 2465 ASPEED_PINCTRL_FUNC(USB2BD), 2466 ASPEED_PINCTRL_FUNC(USB2BH), 2467 ASPEED_PINCTRL_FUNC(USBCKI), 2468 ASPEED_PINCTRL_FUNC(VGABIOSROM), 2469 ASPEED_PINCTRL_FUNC(VGAHS), 2470 ASPEED_PINCTRL_FUNC(VGAVS), 2471 ASPEED_PINCTRL_FUNC(VPI24), 2472 ASPEED_PINCTRL_FUNC(VPO), 2473 ASPEED_PINCTRL_FUNC(WDTRST1), 2474 ASPEED_PINCTRL_FUNC(WDTRST2), 2475 }; 2476 2477 static struct aspeed_pin_config aspeed_g5_configs[] = { 2478 /* GPIOA, GPIOQ */ 2479 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16), 2480 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16), 2481 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16), 2482 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16), 2483 2484 /* GPIOB, GPIOR */ 2485 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17), 2486 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17), 2487 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17), 2488 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17), 2489 2490 /* GPIOC, GPIOS*/ 2491 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18), 2492 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18), 2493 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18), 2494 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18), 2495 2496 /* GPIOD, GPIOY */ 2497 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19), 2498 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19), 2499 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19), 2500 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19), 2501 2502 /* GPIOE, GPIOZ */ 2503 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20), 2504 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20), 2505 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20), 2506 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20), 2507 2508 /* GPIOF, GPIOAA */ 2509 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21), 2510 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21), 2511 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21), 2512 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21), 2513 2514 /* GPIOG, GPIOAB */ 2515 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22), 2516 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22), 2517 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22), 2518 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22), 2519 2520 /* GPIOH, GPIOAC */ 2521 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23), 2522 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23), 2523 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23), 2524 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23), 2525 2526 /* GPIOs [I, P] */ 2527 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24), 2528 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24), 2529 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25), 2530 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25), 2531 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26), 2532 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26), 2533 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27), 2534 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27), 2535 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28), 2536 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28), 2537 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29), 2538 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29), 2539 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30), 2540 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30), 2541 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31), 2542 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31), 2543 2544 /* GPIOs T[0-5] (RGMII1 Tx pins) */ 2545 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8), 2546 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9), 2547 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12), 2548 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12), 2549 2550 /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ 2551 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10), 2552 ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11), 2553 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14), 2554 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14), 2555 2556 /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ 2557 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13), 2558 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13), 2559 2560 /* GPIOs V[2-7] (RGMII2 Rx pins) */ 2561 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15), 2562 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15), 2563 2564 /* ADC pull-downs (SCUA8[19:4]) */ 2565 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4), 2566 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4), 2567 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5), 2568 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5), 2569 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6), 2570 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6), 2571 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7), 2572 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7), 2573 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8), 2574 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8), 2575 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9), 2576 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9), 2577 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10), 2578 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10), 2579 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11), 2580 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11), 2581 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12), 2582 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12), 2583 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13), 2584 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13), 2585 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14), 2586 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14), 2587 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15), 2588 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15), 2589 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16), 2590 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16), 2591 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17), 2592 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17), 2593 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18), 2594 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18), 2595 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19), 2596 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19), 2597 2598 /* 2599 * Debounce settings for GPIOs D and E passthrough mode are in 2600 * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for 2601 * banks D and E is handled by the GPIO driver - GPIO passthrough is 2602 * treated like any other non-GPIO mux function. There is a catch 2603 * however, in that the debounce period is configured in the GPIO 2604 * controller. Due to this tangle between GPIO and pinctrl we don't yet 2605 * fully support pass-through debounce. 2606 */ 2607 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20), 2608 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21), 2609 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22), 2610 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23), 2611 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24), 2612 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25), 2613 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26), 2614 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27), 2615 }; 2616 2617 static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx, 2618 int ip) 2619 { 2620 if (ip == ASPEED_IP_SCU) { 2621 WARN(!ctx->maps[ip], "Missing SCU syscon!"); 2622 return ctx->maps[ip]; 2623 } 2624 2625 if (ip >= ASPEED_NR_PINMUX_IPS) 2626 return ERR_PTR(-EINVAL); 2627 2628 if (likely(ctx->maps[ip])) 2629 return ctx->maps[ip]; 2630 2631 if (ip == ASPEED_IP_GFX) { 2632 struct device_node *node; 2633 struct regmap *map; 2634 2635 node = of_parse_phandle(ctx->dev->of_node, 2636 "aspeed,external-nodes", 0); 2637 if (node) { 2638 map = syscon_node_to_regmap(node); 2639 of_node_put(node); 2640 if (IS_ERR(map)) 2641 return map; 2642 } else 2643 return ERR_PTR(-ENODEV); 2644 2645 ctx->maps[ASPEED_IP_GFX] = map; 2646 dev_dbg(ctx->dev, "Acquired GFX regmap"); 2647 return map; 2648 } 2649 2650 if (ip == ASPEED_IP_LPC) { 2651 struct device_node *np; 2652 struct regmap *map; 2653 2654 np = of_parse_phandle(ctx->dev->of_node, 2655 "aspeed,external-nodes", 1); 2656 if (np) { 2657 if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") && 2658 !of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") && 2659 !of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2")) 2660 return ERR_PTR(-ENODEV); 2661 2662 map = syscon_node_to_regmap(np->parent); 2663 of_node_put(np); 2664 if (IS_ERR(map)) 2665 return map; 2666 } else 2667 return ERR_PTR(-ENODEV); 2668 2669 ctx->maps[ASPEED_IP_LPC] = map; 2670 dev_dbg(ctx->dev, "Acquired LPC regmap"); 2671 return map; 2672 } 2673 2674 return ERR_PTR(-EINVAL); 2675 } 2676 2677 static int aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data *ctx, 2678 const struct aspeed_sig_expr *expr, 2679 bool enabled) 2680 { 2681 int ret; 2682 int i; 2683 2684 for (i = 0; i < expr->ndescs; i++) { 2685 const struct aspeed_sig_desc *desc = &expr->descs[i]; 2686 struct regmap *map; 2687 2688 map = aspeed_g5_acquire_regmap(ctx, desc->ip); 2689 if (IS_ERR(map)) { 2690 dev_err(ctx->dev, 2691 "Failed to acquire regmap for IP block %d\n", 2692 desc->ip); 2693 return PTR_ERR(map); 2694 } 2695 2696 ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]); 2697 if (ret <= 0) 2698 return ret; 2699 } 2700 2701 return 1; 2702 } 2703 2704 /** 2705 * aspeed_g5_sig_expr_set() - Configure a pin's signal by applying an 2706 * expression's descriptor state for all descriptors in the expression. 2707 * 2708 * @ctx: The pinmux context 2709 * @expr: The expression associated with the function whose signal is to be 2710 * configured 2711 * @enable: true to enable an function's signal through a pin's signal 2712 * expression, false to disable the function's signal 2713 * 2714 * Return: 0 if the expression is configured as requested and a negative error 2715 * code otherwise 2716 */ 2717 static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, 2718 const struct aspeed_sig_expr *expr, 2719 bool enable) 2720 { 2721 int ret; 2722 int i; 2723 2724 for (i = 0; i < expr->ndescs; i++) { 2725 const struct aspeed_sig_desc *desc = &expr->descs[i]; 2726 u32 pattern = enable ? desc->enable : desc->disable; 2727 u32 val = (pattern << __ffs(desc->mask)); 2728 struct regmap *map; 2729 2730 map = aspeed_g5_acquire_regmap(ctx, desc->ip); 2731 if (IS_ERR(map)) { 2732 dev_err(ctx->dev, 2733 "Failed to acquire regmap for IP block %d\n", 2734 desc->ip); 2735 return PTR_ERR(map); 2736 } 2737 2738 /* 2739 * Strap registers are configured in hardware or by early-boot 2740 * firmware. Treat them as read-only despite that we can write 2741 * them. This may mean that certain functions cannot be 2742 * deconfigured and is the reason we re-evaluate after writing 2743 * all descriptor bits. 2744 * 2745 * Port D and port E GPIO loopback modes are the only exception 2746 * as those are commonly used with front-panel buttons to allow 2747 * normal operation of the host when the BMC is powered off or 2748 * fails to boot. Once the BMC has booted, the loopback mode 2749 * must be disabled for the BMC to control host power-on and 2750 * reset. 2751 */ 2752 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && 2753 !(desc->mask & (BIT(21) | BIT(22)))) 2754 continue; 2755 2756 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) 2757 continue; 2758 2759 /* On AST2500, Set bits in SCU70 are cleared from SCU7C */ 2760 if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) { 2761 u32 value = ~val & desc->mask; 2762 2763 if (value) { 2764 ret = regmap_write(ctx->maps[desc->ip], 2765 HW_REVISION_ID, value); 2766 if (ret < 0) 2767 return ret; 2768 } 2769 } 2770 2771 ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, 2772 desc->mask, val); 2773 2774 if (ret) 2775 return ret; 2776 } 2777 2778 ret = aspeed_sig_expr_eval(ctx, expr, enable); 2779 if (ret < 0) 2780 return ret; 2781 2782 if (!ret) 2783 return -EPERM; 2784 2785 return 0; 2786 } 2787 2788 static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { 2789 { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, 2790 { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, 2791 { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, 2792 { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, 2793 { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, 2794 }; 2795 2796 static const struct aspeed_pinmux_ops aspeed_g5_ops = { 2797 .eval = aspeed_g5_sig_expr_eval, 2798 .set = aspeed_g5_sig_expr_set, 2799 }; 2800 2801 static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { 2802 .pins = aspeed_g5_pins, 2803 .npins = ARRAY_SIZE(aspeed_g5_pins), 2804 .pinmux = { 2805 .ops = &aspeed_g5_ops, 2806 .groups = aspeed_g5_groups, 2807 .ngroups = ARRAY_SIZE(aspeed_g5_groups), 2808 .functions = aspeed_g5_functions, 2809 .nfunctions = ARRAY_SIZE(aspeed_g5_functions), 2810 }, 2811 .configs = aspeed_g5_configs, 2812 .nconfigs = ARRAY_SIZE(aspeed_g5_configs), 2813 .confmaps = aspeed_g5_pin_config_map, 2814 .nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map), 2815 }; 2816 2817 static const struct pinmux_ops aspeed_g5_pinmux_ops = { 2818 .get_functions_count = aspeed_pinmux_get_fn_count, 2819 .get_function_name = aspeed_pinmux_get_fn_name, 2820 .get_function_groups = aspeed_pinmux_get_fn_groups, 2821 .set_mux = aspeed_pinmux_set_mux, 2822 .gpio_request_enable = aspeed_gpio_request_enable, 2823 .strict = true, 2824 }; 2825 2826 static const struct pinctrl_ops aspeed_g5_pinctrl_ops = { 2827 .get_groups_count = aspeed_pinctrl_get_groups_count, 2828 .get_group_name = aspeed_pinctrl_get_group_name, 2829 .get_group_pins = aspeed_pinctrl_get_group_pins, 2830 .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, 2831 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2832 .dt_free_map = pinctrl_utils_free_map, 2833 }; 2834 2835 static const struct pinconf_ops aspeed_g5_conf_ops = { 2836 .is_generic = true, 2837 .pin_config_get = aspeed_pin_config_get, 2838 .pin_config_set = aspeed_pin_config_set, 2839 .pin_config_group_get = aspeed_pin_config_group_get, 2840 .pin_config_group_set = aspeed_pin_config_group_set, 2841 }; 2842 2843 static struct pinctrl_desc aspeed_g5_pinctrl_desc = { 2844 .name = "aspeed-g5-pinctrl", 2845 .pins = aspeed_g5_pins, 2846 .npins = ARRAY_SIZE(aspeed_g5_pins), 2847 .pctlops = &aspeed_g5_pinctrl_ops, 2848 .pmxops = &aspeed_g5_pinmux_ops, 2849 .confops = &aspeed_g5_conf_ops, 2850 }; 2851 2852 static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) 2853 { 2854 int i; 2855 2856 for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++) 2857 aspeed_g5_pins[i].number = i; 2858 2859 aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev; 2860 2861 return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc, 2862 &aspeed_g5_pinctrl_data); 2863 } 2864 2865 static const struct of_device_id aspeed_g5_pinctrl_of_match[] = { 2866 { .compatible = "aspeed,ast2500-pinctrl", }, 2867 /* 2868 * The aspeed,g5-pinctrl compatible has been removed the from the 2869 * bindings, but keep the match in case of old devicetrees. 2870 */ 2871 { .compatible = "aspeed,g5-pinctrl", }, 2872 { }, 2873 }; 2874 2875 static struct platform_driver aspeed_g5_pinctrl_driver = { 2876 .probe = aspeed_g5_pinctrl_probe, 2877 .driver = { 2878 .name = "aspeed-g5-pinctrl", 2879 .of_match_table = aspeed_g5_pinctrl_of_match, 2880 }, 2881 }; 2882 2883 static int aspeed_g5_pinctrl_init(void) 2884 { 2885 return platform_driver_register(&aspeed_g5_pinctrl_driver); 2886 } 2887 2888 arch_initcall(aspeed_g5_pinctrl_init); 2889