1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OWL SoC's Pinctrl definitions 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #ifndef __PINCTRL_OWL_H__ 13 #define __PINCTRL_OWL_H__ 14 15 #define OWL_PINCONF_SLEW_SLOW 0 16 #define OWL_PINCONF_SLEW_FAST 1 17 18 enum owl_pinconf_pull { 19 OWL_PINCONF_PULL_HIZ, 20 OWL_PINCONF_PULL_DOWN, 21 OWL_PINCONF_PULL_UP, 22 OWL_PINCONF_PULL_HOLD, 23 }; 24 25 enum owl_pinconf_drv { 26 OWL_PINCONF_DRV_2MA, 27 OWL_PINCONF_DRV_4MA, 28 OWL_PINCONF_DRV_8MA, 29 OWL_PINCONF_DRV_12MA, 30 }; 31 32 /** 33 * struct owl_pullctl - Actions pad pull control register 34 * @reg: offset to the pull control register 35 * @shift: shift value of the register 36 * @width: width of the register 37 */ 38 struct owl_pullctl { 39 int reg; 40 unsigned int shift; 41 unsigned int width; 42 }; 43 44 /** 45 * struct owl_st - Actions pad schmitt trigger enable register 46 * @reg: offset to the schmitt trigger enable register 47 * @shift: shift value of the register 48 * @width: width of the register 49 */ 50 struct owl_st { 51 int reg; 52 unsigned int shift; 53 unsigned int width; 54 }; 55 56 /** 57 * struct owl_pingroup - Actions pingroup definition 58 * @name: name of the pin group 59 * @pads: list of pins assigned to this pingroup 60 * @npads: size of @pads array 61 * @funcs: list of pinmux functions for this pingroup 62 * @nfuncs: size of @funcs array 63 * @mfpctl_reg: multiplexing control register offset 64 * @mfpctl_shift: multiplexing control register bit mask 65 * @mfpctl_width: multiplexing control register width 66 * @drv_reg: drive control register offset 67 * @drv_shift: drive control register bit mask 68 * @drv_width: driver control register width 69 * @sr_reg: slew rate control register offset 70 * @sr_shift: slew rate control register bit mask 71 * @sr_width: slew rate control register width 72 */ 73 struct owl_pingroup { 74 const char *name; 75 unsigned int *pads; 76 unsigned int npads; 77 unsigned int *funcs; 78 unsigned int nfuncs; 79 80 int mfpctl_reg; 81 unsigned int mfpctl_shift; 82 unsigned int mfpctl_width; 83 84 int drv_reg; 85 unsigned int drv_shift; 86 unsigned int drv_width; 87 88 int sr_reg; 89 unsigned int sr_shift; 90 unsigned int sr_width; 91 }; 92 93 /** 94 * struct owl_padinfo - Actions pinctrl pad info 95 * @pad: pad name of the SoC 96 * @pullctl: pull control register info 97 * @st: schmitt trigger register info 98 */ 99 struct owl_padinfo { 100 int pad; 101 struct owl_pullctl *pullctl; 102 struct owl_st *st; 103 }; 104 105 /** 106 * struct owl_pinmux_func - Actions pinctrl mux functions 107 * @name: name of the pinmux function. 108 * @groups: array of pin groups that may select this function. 109 * @ngroups: number of entries in @groups. 110 */ 111 struct owl_pinmux_func { 112 const char *name; 113 const char * const *groups; 114 unsigned int ngroups; 115 }; 116 117 /** 118 * struct owl_gpio_port - Actions GPIO port info 119 * @offset: offset of the GPIO port. 120 * @pins: number of pins belongs to the GPIO port. 121 * @outen: offset of the output enable register. 122 * @inen: offset of the input enable register. 123 * @dat: offset of the data register. 124 */ 125 struct owl_gpio_port { 126 unsigned int offset; 127 unsigned int pins; 128 unsigned int outen; 129 unsigned int inen; 130 unsigned int dat; 131 }; 132 133 /** 134 * struct owl_pinctrl_soc_data - Actions pin controller driver configuration 135 * @pins: array describing all pins of the pin controller. 136 * @npins: number of entries in @pins. 137 * @functions: array describing all mux functions of this SoC. 138 * @nfunction: number of entries in @functions. 139 * @groups: array describing all pin groups of this SoC. 140 * @ngroups: number of entries in @groups. 141 * @padinfo: array describing the pad info of this SoC. 142 * @ngpios: number of pingroups the driver should expose as GPIOs. 143 * @port: array describing all GPIO ports of this SoC. 144 * @nports: number of GPIO ports in this SoC. 145 */ 146 struct owl_pinctrl_soc_data { 147 const struct pinctrl_pin_desc *pins; 148 unsigned int npins; 149 const struct owl_pinmux_func *functions; 150 unsigned int nfunctions; 151 const struct owl_pingroup *groups; 152 unsigned int ngroups; 153 const struct owl_padinfo *padinfo; 154 unsigned int ngpios; 155 const struct owl_gpio_port *ports; 156 unsigned int nports; 157 }; 158 159 int owl_pinctrl_probe(struct platform_device *pdev, 160 struct owl_pinctrl_soc_data *soc_data); 161 162 #endif /* __PINCTRL_OWL_H__ */ 163