1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OWL SoC's Pinctrl definitions 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #ifndef __PINCTRL_OWL_H__ 13 #define __PINCTRL_OWL_H__ 14 15 #define OWL_PINCONF_SLEW_SLOW 0 16 #define OWL_PINCONF_SLEW_FAST 1 17 18 enum owl_pinconf_pull { 19 OWL_PINCONF_PULL_HIZ, 20 OWL_PINCONF_PULL_DOWN, 21 OWL_PINCONF_PULL_UP, 22 OWL_PINCONF_PULL_HOLD, 23 }; 24 25 enum owl_pinconf_drv { 26 OWL_PINCONF_DRV_2MA, 27 OWL_PINCONF_DRV_4MA, 28 OWL_PINCONF_DRV_8MA, 29 OWL_PINCONF_DRV_12MA, 30 }; 31 32 /* GPIO CTRL Bit Definition */ 33 #define OWL_GPIO_CTLR_PENDING 0 34 #define OWL_GPIO_CTLR_ENABLE 1 35 #define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2 36 37 /* GPIO TYPE Bit Definition */ 38 #define OWL_GPIO_INT_LEVEL_HIGH 0 39 #define OWL_GPIO_INT_LEVEL_LOW 1 40 #define OWL_GPIO_INT_EDGE_RISING 2 41 #define OWL_GPIO_INT_EDGE_FALLING 3 42 #define OWL_GPIO_INT_MASK 3 43 44 /** 45 * struct owl_pullctl - Actions pad pull control register 46 * @reg: offset to the pull control register 47 * @shift: shift value of the register 48 * @width: width of the register 49 */ 50 struct owl_pullctl { 51 int reg; 52 unsigned int shift; 53 unsigned int width; 54 }; 55 56 /** 57 * struct owl_st - Actions pad schmitt trigger enable register 58 * @reg: offset to the schmitt trigger enable register 59 * @shift: shift value of the register 60 * @width: width of the register 61 */ 62 struct owl_st { 63 int reg; 64 unsigned int shift; 65 unsigned int width; 66 }; 67 68 /** 69 * struct owl_pingroup - Actions pingroup definition 70 * @name: name of the pin group 71 * @pads: list of pins assigned to this pingroup 72 * @npads: size of @pads array 73 * @funcs: list of pinmux functions for this pingroup 74 * @nfuncs: size of @funcs array 75 * @mfpctl_reg: multiplexing control register offset 76 * @mfpctl_shift: multiplexing control register bit mask 77 * @mfpctl_width: multiplexing control register width 78 * @drv_reg: drive control register offset 79 * @drv_shift: drive control register bit mask 80 * @drv_width: driver control register width 81 * @sr_reg: slew rate control register offset 82 * @sr_shift: slew rate control register bit mask 83 * @sr_width: slew rate control register width 84 */ 85 struct owl_pingroup { 86 const char *name; 87 unsigned int *pads; 88 unsigned int npads; 89 unsigned int *funcs; 90 unsigned int nfuncs; 91 92 int mfpctl_reg; 93 unsigned int mfpctl_shift; 94 unsigned int mfpctl_width; 95 96 int drv_reg; 97 unsigned int drv_shift; 98 unsigned int drv_width; 99 100 int sr_reg; 101 unsigned int sr_shift; 102 unsigned int sr_width; 103 }; 104 105 /** 106 * struct owl_padinfo - Actions pinctrl pad info 107 * @pad: pad name of the SoC 108 * @pullctl: pull control register info 109 * @st: schmitt trigger register info 110 */ 111 struct owl_padinfo { 112 int pad; 113 struct owl_pullctl *pullctl; 114 struct owl_st *st; 115 }; 116 117 /** 118 * struct owl_pinmux_func - Actions pinctrl mux functions 119 * @name: name of the pinmux function. 120 * @groups: array of pin groups that may select this function. 121 * @ngroups: number of entries in @groups. 122 */ 123 struct owl_pinmux_func { 124 const char *name; 125 const char * const *groups; 126 unsigned int ngroups; 127 }; 128 129 /** 130 * struct owl_gpio_port - Actions GPIO port info 131 * @offset: offset of the GPIO port. 132 * @pins: number of pins belongs to the GPIO port. 133 * @outen: offset of the output enable register. 134 * @inen: offset of the input enable register. 135 * @dat: offset of the data register. 136 * @intc_ctl: offset of the interrupt control register. 137 * @intc_pd: offset of the interrupt pending register. 138 * @intc_msk: offset of the interrupt mask register. 139 * @intc_type: offset of the interrupt type register. 140 */ 141 struct owl_gpio_port { 142 unsigned int offset; 143 unsigned int pins; 144 unsigned int outen; 145 unsigned int inen; 146 unsigned int dat; 147 unsigned int intc_ctl; 148 unsigned int intc_pd; 149 unsigned int intc_msk; 150 unsigned int intc_type; 151 }; 152 153 /** 154 * struct owl_pinctrl_soc_data - Actions pin controller driver configuration 155 * @pins: array describing all pins of the pin controller. 156 * @npins: number of entries in @pins. 157 * @functions: array describing all mux functions of this SoC. 158 * @nfunction: number of entries in @functions. 159 * @groups: array describing all pin groups of this SoC. 160 * @ngroups: number of entries in @groups. 161 * @padinfo: array describing the pad info of this SoC. 162 * @ngpios: number of pingroups the driver should expose as GPIOs. 163 * @ports: array describing all GPIO ports of this SoC. 164 * @nports: number of GPIO ports in this SoC. 165 */ 166 struct owl_pinctrl_soc_data { 167 const struct pinctrl_pin_desc *pins; 168 unsigned int npins; 169 const struct owl_pinmux_func *functions; 170 unsigned int nfunctions; 171 const struct owl_pingroup *groups; 172 unsigned int ngroups; 173 const struct owl_padinfo *padinfo; 174 unsigned int ngpios; 175 const struct owl_gpio_port *ports; 176 unsigned int nports; 177 }; 178 179 int owl_pinctrl_probe(struct platform_device *pdev, 180 struct owl_pinctrl_soc_data *soc_data); 181 182 #endif /* __PINCTRL_OWL_H__ */ 183