1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OWL SoC's Pinctrl driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pinctrl/machine.h> 21 #include <linux/pinctrl/pinctrl.h> 22 #include <linux/pinctrl/pinmux.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinconf-generic.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 28 #include "../core.h" 29 #include "../pinctrl-utils.h" 30 #include "pinctrl-owl.h" 31 32 /** 33 * struct owl_pinctrl - pinctrl state of the device 34 * @dev: device handle 35 * @pctrldev: pinctrl handle 36 * @chip: gpio chip 37 * @lock: spinlock to protect registers 38 * @clk: clock control 39 * @soc: reference to soc_data 40 * @base: pinctrl register base address 41 * @irq_chip: IRQ chip information 42 * @num_irq: number of possible interrupts 43 * @irq: interrupt numbers 44 */ 45 struct owl_pinctrl { 46 struct device *dev; 47 struct pinctrl_dev *pctrldev; 48 struct gpio_chip chip; 49 raw_spinlock_t lock; 50 struct clk *clk; 51 const struct owl_pinctrl_soc_data *soc; 52 void __iomem *base; 53 struct irq_chip irq_chip; 54 unsigned int num_irq; 55 unsigned int *irq; 56 }; 57 58 static void owl_update_bits(void __iomem *base, u32 mask, u32 val) 59 { 60 u32 reg_val; 61 62 reg_val = readl_relaxed(base); 63 64 reg_val = (reg_val & ~mask) | (val & mask); 65 66 writel_relaxed(reg_val, base); 67 } 68 69 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg, 70 u32 bit, u32 width) 71 { 72 u32 tmp, mask; 73 74 tmp = readl_relaxed(pctrl->base + reg); 75 mask = (1 << width) - 1; 76 77 return (tmp >> bit) & mask; 78 } 79 80 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg, 81 u32 bit, u32 width) 82 { 83 u32 mask; 84 85 mask = (1 << width) - 1; 86 mask = mask << bit; 87 88 owl_update_bits(pctrl->base + reg, mask, (arg << bit)); 89 } 90 91 static int owl_get_groups_count(struct pinctrl_dev *pctrldev) 92 { 93 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 94 95 return pctrl->soc->ngroups; 96 } 97 98 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev, 99 unsigned int group) 100 { 101 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 102 103 return pctrl->soc->groups[group].name; 104 } 105 106 static int owl_get_group_pins(struct pinctrl_dev *pctrldev, 107 unsigned int group, 108 const unsigned int **pins, 109 unsigned int *num_pins) 110 { 111 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 112 113 *pins = pctrl->soc->groups[group].pads; 114 *num_pins = pctrl->soc->groups[group].npads; 115 116 return 0; 117 } 118 119 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev, 120 struct seq_file *s, 121 unsigned int offset) 122 { 123 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 124 125 seq_printf(s, "%s", dev_name(pctrl->dev)); 126 } 127 128 static const struct pinctrl_ops owl_pinctrl_ops = { 129 .get_groups_count = owl_get_groups_count, 130 .get_group_name = owl_get_group_name, 131 .get_group_pins = owl_get_group_pins, 132 .pin_dbg_show = owl_pin_dbg_show, 133 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 134 .dt_free_map = pinctrl_utils_free_map, 135 }; 136 137 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev) 138 { 139 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 140 141 return pctrl->soc->nfunctions; 142 } 143 144 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev, 145 unsigned int function) 146 { 147 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 148 149 return pctrl->soc->functions[function].name; 150 } 151 152 static int owl_get_func_groups(struct pinctrl_dev *pctrldev, 153 unsigned int function, 154 const char * const **groups, 155 unsigned int * const num_groups) 156 { 157 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 158 159 *groups = pctrl->soc->functions[function].groups; 160 *num_groups = pctrl->soc->functions[function].ngroups; 161 162 return 0; 163 } 164 165 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g, 166 int function, 167 u32 *mask, 168 u32 *val) 169 { 170 int id; 171 u32 option_num; 172 u32 option_mask; 173 174 for (id = 0; id < g->nfuncs; id++) { 175 if (g->funcs[id] == function) 176 break; 177 } 178 if (WARN_ON(id == g->nfuncs)) 179 return -EINVAL; 180 181 option_num = (1 << g->mfpctl_width); 182 if (id > option_num) 183 id -= option_num; 184 185 option_mask = option_num - 1; 186 *mask = (option_mask << g->mfpctl_shift); 187 *val = (id << g->mfpctl_shift); 188 189 return 0; 190 } 191 192 static int owl_set_mux(struct pinctrl_dev *pctrldev, 193 unsigned int function, 194 unsigned int group) 195 { 196 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 197 const struct owl_pingroup *g; 198 unsigned long flags; 199 u32 val, mask; 200 201 g = &pctrl->soc->groups[group]; 202 203 if (get_group_mfp_mask_val(g, function, &mask, &val)) 204 return -EINVAL; 205 206 raw_spin_lock_irqsave(&pctrl->lock, flags); 207 208 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val); 209 210 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 211 212 return 0; 213 } 214 215 static const struct pinmux_ops owl_pinmux_ops = { 216 .get_functions_count = owl_get_funcs_count, 217 .get_function_name = owl_get_func_name, 218 .get_function_groups = owl_get_func_groups, 219 .set_mux = owl_set_mux, 220 }; 221 222 static int owl_pad_pinconf_reg(const struct owl_padinfo *info, 223 unsigned int param, 224 u32 *reg, 225 u32 *bit, 226 u32 *width) 227 { 228 switch (param) { 229 case PIN_CONFIG_BIAS_BUS_HOLD: 230 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 231 case PIN_CONFIG_BIAS_PULL_DOWN: 232 case PIN_CONFIG_BIAS_PULL_UP: 233 if (!info->pullctl) 234 return -EINVAL; 235 *reg = info->pullctl->reg; 236 *bit = info->pullctl->shift; 237 *width = info->pullctl->width; 238 break; 239 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 240 if (!info->st) 241 return -EINVAL; 242 *reg = info->st->reg; 243 *bit = info->st->shift; 244 *width = info->st->width; 245 break; 246 default: 247 return -ENOTSUPP; 248 } 249 250 return 0; 251 } 252 253 static int owl_pin_config_get(struct pinctrl_dev *pctrldev, 254 unsigned int pin, 255 unsigned long *config) 256 { 257 int ret = 0; 258 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 259 const struct owl_padinfo *info; 260 unsigned int param = pinconf_to_config_param(*config); 261 u32 reg, bit, width, arg; 262 263 info = &pctrl->soc->padinfo[pin]; 264 265 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); 266 if (ret) 267 return ret; 268 269 arg = owl_read_field(pctrl, reg, bit, width); 270 271 if (!pctrl->soc->padctl_val2arg) 272 return -ENOTSUPP; 273 274 ret = pctrl->soc->padctl_val2arg(info, param, &arg); 275 if (ret) 276 return ret; 277 278 *config = pinconf_to_config_packed(param, arg); 279 280 return ret; 281 } 282 283 static int owl_pin_config_set(struct pinctrl_dev *pctrldev, 284 unsigned int pin, 285 unsigned long *configs, 286 unsigned int num_configs) 287 { 288 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 289 const struct owl_padinfo *info; 290 unsigned long flags; 291 unsigned int param; 292 u32 reg, bit, width, arg; 293 int ret = 0, i; 294 295 info = &pctrl->soc->padinfo[pin]; 296 297 for (i = 0; i < num_configs; i++) { 298 param = pinconf_to_config_param(configs[i]); 299 arg = pinconf_to_config_argument(configs[i]); 300 301 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); 302 if (ret) 303 return ret; 304 305 if (!pctrl->soc->padctl_arg2val) 306 return -ENOTSUPP; 307 308 ret = pctrl->soc->padctl_arg2val(info, param, &arg); 309 if (ret) 310 return ret; 311 312 raw_spin_lock_irqsave(&pctrl->lock, flags); 313 314 owl_write_field(pctrl, reg, arg, bit, width); 315 316 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 317 } 318 319 return ret; 320 } 321 322 static int owl_group_pinconf_reg(const struct owl_pingroup *g, 323 unsigned int param, 324 u32 *reg, 325 u32 *bit, 326 u32 *width) 327 { 328 switch (param) { 329 case PIN_CONFIG_DRIVE_STRENGTH: 330 if (g->drv_reg < 0) 331 return -EINVAL; 332 *reg = g->drv_reg; 333 *bit = g->drv_shift; 334 *width = g->drv_width; 335 break; 336 case PIN_CONFIG_SLEW_RATE: 337 if (g->sr_reg < 0) 338 return -EINVAL; 339 *reg = g->sr_reg; 340 *bit = g->sr_shift; 341 *width = g->sr_width; 342 break; 343 default: 344 return -ENOTSUPP; 345 } 346 347 return 0; 348 } 349 350 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g, 351 unsigned int param, 352 u32 *arg) 353 { 354 switch (param) { 355 case PIN_CONFIG_DRIVE_STRENGTH: 356 switch (*arg) { 357 case 2: 358 *arg = OWL_PINCONF_DRV_2MA; 359 break; 360 case 4: 361 *arg = OWL_PINCONF_DRV_4MA; 362 break; 363 case 8: 364 *arg = OWL_PINCONF_DRV_8MA; 365 break; 366 case 12: 367 *arg = OWL_PINCONF_DRV_12MA; 368 break; 369 default: 370 return -EINVAL; 371 } 372 break; 373 case PIN_CONFIG_SLEW_RATE: 374 if (*arg) 375 *arg = OWL_PINCONF_SLEW_FAST; 376 else 377 *arg = OWL_PINCONF_SLEW_SLOW; 378 break; 379 default: 380 return -ENOTSUPP; 381 } 382 383 return 0; 384 } 385 386 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g, 387 unsigned int param, 388 u32 *arg) 389 { 390 switch (param) { 391 case PIN_CONFIG_DRIVE_STRENGTH: 392 switch (*arg) { 393 case OWL_PINCONF_DRV_2MA: 394 *arg = 2; 395 break; 396 case OWL_PINCONF_DRV_4MA: 397 *arg = 4; 398 break; 399 case OWL_PINCONF_DRV_8MA: 400 *arg = 8; 401 break; 402 case OWL_PINCONF_DRV_12MA: 403 *arg = 12; 404 break; 405 default: 406 return -EINVAL; 407 } 408 break; 409 case PIN_CONFIG_SLEW_RATE: 410 if (*arg) 411 *arg = 1; 412 else 413 *arg = 0; 414 break; 415 default: 416 return -ENOTSUPP; 417 } 418 419 return 0; 420 } 421 422 static int owl_group_config_get(struct pinctrl_dev *pctrldev, 423 unsigned int group, 424 unsigned long *config) 425 { 426 const struct owl_pingroup *g; 427 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 428 unsigned int param = pinconf_to_config_param(*config); 429 u32 reg, bit, width, arg; 430 int ret; 431 432 g = &pctrl->soc->groups[group]; 433 434 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); 435 if (ret) 436 return ret; 437 438 arg = owl_read_field(pctrl, reg, bit, width); 439 440 ret = owl_group_pinconf_val2arg(g, param, &arg); 441 if (ret) 442 return ret; 443 444 *config = pinconf_to_config_packed(param, arg); 445 446 return ret; 447 448 } 449 450 static int owl_group_config_set(struct pinctrl_dev *pctrldev, 451 unsigned int group, 452 unsigned long *configs, 453 unsigned int num_configs) 454 { 455 const struct owl_pingroup *g; 456 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev); 457 unsigned long flags; 458 unsigned int param; 459 u32 reg, bit, width, arg; 460 int ret, i; 461 462 g = &pctrl->soc->groups[group]; 463 464 for (i = 0; i < num_configs; i++) { 465 param = pinconf_to_config_param(configs[i]); 466 arg = pinconf_to_config_argument(configs[i]); 467 468 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); 469 if (ret) 470 return ret; 471 472 ret = owl_group_pinconf_arg2val(g, param, &arg); 473 if (ret) 474 return ret; 475 476 /* Update register */ 477 raw_spin_lock_irqsave(&pctrl->lock, flags); 478 479 owl_write_field(pctrl, reg, arg, bit, width); 480 481 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 482 } 483 484 return 0; 485 } 486 487 static const struct pinconf_ops owl_pinconf_ops = { 488 .is_generic = true, 489 .pin_config_get = owl_pin_config_get, 490 .pin_config_set = owl_pin_config_set, 491 .pin_config_group_get = owl_group_config_get, 492 .pin_config_group_set = owl_group_config_set, 493 }; 494 495 static struct pinctrl_desc owl_pinctrl_desc = { 496 .pctlops = &owl_pinctrl_ops, 497 .pmxops = &owl_pinmux_ops, 498 .confops = &owl_pinconf_ops, 499 .owner = THIS_MODULE, 500 }; 501 502 static const struct owl_gpio_port * 503 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin) 504 { 505 unsigned int start = 0, i; 506 507 for (i = 0; i < pctrl->soc->nports; i++) { 508 const struct owl_gpio_port *port = &pctrl->soc->ports[i]; 509 510 if (*pin >= start && *pin < start + port->pins) { 511 *pin -= start; 512 return port; 513 } 514 515 start += port->pins; 516 } 517 518 return NULL; 519 } 520 521 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag) 522 { 523 u32 val; 524 525 val = readl_relaxed(base); 526 527 if (flag) 528 val |= BIT(pin); 529 else 530 val &= ~BIT(pin); 531 532 writel_relaxed(val, base); 533 } 534 535 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset) 536 { 537 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 538 const struct owl_gpio_port *port; 539 void __iomem *gpio_base; 540 unsigned long flags; 541 542 port = owl_gpio_get_port(pctrl, &offset); 543 if (WARN_ON(port == NULL)) 544 return -ENODEV; 545 546 gpio_base = pctrl->base + port->offset; 547 548 /* 549 * GPIOs have higher priority over other modules, so either setting 550 * them as OUT or IN is sufficient 551 */ 552 raw_spin_lock_irqsave(&pctrl->lock, flags); 553 owl_gpio_update_reg(gpio_base + port->outen, offset, true); 554 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 555 556 return 0; 557 } 558 559 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset) 560 { 561 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 562 const struct owl_gpio_port *port; 563 void __iomem *gpio_base; 564 unsigned long flags; 565 566 port = owl_gpio_get_port(pctrl, &offset); 567 if (WARN_ON(port == NULL)) 568 return; 569 570 gpio_base = pctrl->base + port->offset; 571 572 raw_spin_lock_irqsave(&pctrl->lock, flags); 573 /* disable gpio output */ 574 owl_gpio_update_reg(gpio_base + port->outen, offset, false); 575 576 /* disable gpio input */ 577 owl_gpio_update_reg(gpio_base + port->inen, offset, false); 578 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 579 } 580 581 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) 582 { 583 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 584 const struct owl_gpio_port *port; 585 void __iomem *gpio_base; 586 unsigned long flags; 587 u32 val; 588 589 port = owl_gpio_get_port(pctrl, &offset); 590 if (WARN_ON(port == NULL)) 591 return -ENODEV; 592 593 gpio_base = pctrl->base + port->offset; 594 595 raw_spin_lock_irqsave(&pctrl->lock, flags); 596 val = readl_relaxed(gpio_base + port->dat); 597 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 598 599 return !!(val & BIT(offset)); 600 } 601 602 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 603 { 604 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 605 const struct owl_gpio_port *port; 606 void __iomem *gpio_base; 607 unsigned long flags; 608 609 port = owl_gpio_get_port(pctrl, &offset); 610 if (WARN_ON(port == NULL)) 611 return; 612 613 gpio_base = pctrl->base + port->offset; 614 615 raw_spin_lock_irqsave(&pctrl->lock, flags); 616 owl_gpio_update_reg(gpio_base + port->dat, offset, value); 617 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 618 } 619 620 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 621 { 622 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 623 const struct owl_gpio_port *port; 624 void __iomem *gpio_base; 625 unsigned long flags; 626 627 port = owl_gpio_get_port(pctrl, &offset); 628 if (WARN_ON(port == NULL)) 629 return -ENODEV; 630 631 gpio_base = pctrl->base + port->offset; 632 633 raw_spin_lock_irqsave(&pctrl->lock, flags); 634 owl_gpio_update_reg(gpio_base + port->outen, offset, false); 635 owl_gpio_update_reg(gpio_base + port->inen, offset, true); 636 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 637 638 return 0; 639 } 640 641 static int owl_gpio_direction_output(struct gpio_chip *chip, 642 unsigned int offset, int value) 643 { 644 struct owl_pinctrl *pctrl = gpiochip_get_data(chip); 645 const struct owl_gpio_port *port; 646 void __iomem *gpio_base; 647 unsigned long flags; 648 649 port = owl_gpio_get_port(pctrl, &offset); 650 if (WARN_ON(port == NULL)) 651 return -ENODEV; 652 653 gpio_base = pctrl->base + port->offset; 654 655 raw_spin_lock_irqsave(&pctrl->lock, flags); 656 owl_gpio_update_reg(gpio_base + port->inen, offset, false); 657 owl_gpio_update_reg(gpio_base + port->outen, offset, true); 658 owl_gpio_update_reg(gpio_base + port->dat, offset, value); 659 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 660 661 return 0; 662 } 663 664 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type) 665 { 666 const struct owl_gpio_port *port; 667 void __iomem *gpio_base; 668 unsigned long flags; 669 unsigned int offset, value, irq_type = 0; 670 671 switch (type) { 672 case IRQ_TYPE_EDGE_BOTH: 673 /* 674 * Since the hardware doesn't support interrupts on both edges, 675 * emulate it in the software by setting the single edge 676 * interrupt and switching to the opposite edge while ACKing 677 * the interrupt 678 */ 679 if (owl_gpio_get(&pctrl->chip, gpio)) 680 irq_type = OWL_GPIO_INT_EDGE_FALLING; 681 else 682 irq_type = OWL_GPIO_INT_EDGE_RISING; 683 break; 684 685 case IRQ_TYPE_EDGE_RISING: 686 irq_type = OWL_GPIO_INT_EDGE_RISING; 687 break; 688 689 case IRQ_TYPE_EDGE_FALLING: 690 irq_type = OWL_GPIO_INT_EDGE_FALLING; 691 break; 692 693 case IRQ_TYPE_LEVEL_HIGH: 694 irq_type = OWL_GPIO_INT_LEVEL_HIGH; 695 break; 696 697 case IRQ_TYPE_LEVEL_LOW: 698 irq_type = OWL_GPIO_INT_LEVEL_LOW; 699 break; 700 701 default: 702 break; 703 } 704 705 port = owl_gpio_get_port(pctrl, &gpio); 706 if (WARN_ON(port == NULL)) 707 return; 708 709 gpio_base = pctrl->base + port->offset; 710 711 raw_spin_lock_irqsave(&pctrl->lock, flags); 712 713 offset = (gpio < 16) ? 4 : 0; 714 value = readl_relaxed(gpio_base + port->intc_type + offset); 715 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2)); 716 value |= irq_type << ((gpio % 16) * 2); 717 writel_relaxed(value, gpio_base + port->intc_type + offset); 718 719 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 720 } 721 722 static void owl_gpio_irq_mask(struct irq_data *data) 723 { 724 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 725 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 726 const struct owl_gpio_port *port; 727 void __iomem *gpio_base; 728 unsigned long flags; 729 unsigned int gpio = data->hwirq; 730 u32 val; 731 732 port = owl_gpio_get_port(pctrl, &gpio); 733 if (WARN_ON(port == NULL)) 734 return; 735 736 gpio_base = pctrl->base + port->offset; 737 738 raw_spin_lock_irqsave(&pctrl->lock, flags); 739 740 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false); 741 742 /* disable port interrupt if no interrupt pending bit is active */ 743 val = readl_relaxed(gpio_base + port->intc_msk); 744 if (val == 0) 745 owl_gpio_update_reg(gpio_base + port->intc_ctl, 746 OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false); 747 748 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 749 } 750 751 static void owl_gpio_irq_unmask(struct irq_data *data) 752 { 753 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 754 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 755 const struct owl_gpio_port *port; 756 void __iomem *gpio_base; 757 unsigned long flags; 758 unsigned int gpio = data->hwirq; 759 u32 value; 760 761 port = owl_gpio_get_port(pctrl, &gpio); 762 if (WARN_ON(port == NULL)) 763 return; 764 765 gpio_base = pctrl->base + port->offset; 766 raw_spin_lock_irqsave(&pctrl->lock, flags); 767 768 /* enable port interrupt */ 769 value = readl_relaxed(gpio_base + port->intc_ctl); 770 value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M)) 771 << port->shared_ctl_offset * 5); 772 writel_relaxed(value, gpio_base + port->intc_ctl); 773 774 /* enable GPIO interrupt */ 775 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true); 776 777 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 778 } 779 780 static void owl_gpio_irq_ack(struct irq_data *data) 781 { 782 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 783 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 784 const struct owl_gpio_port *port; 785 void __iomem *gpio_base; 786 unsigned long flags; 787 unsigned int gpio = data->hwirq; 788 789 /* 790 * Switch the interrupt edge to the opposite edge of the interrupt 791 * which got triggered for the case of emulating both edges 792 */ 793 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) { 794 if (owl_gpio_get(gc, gpio)) 795 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING); 796 else 797 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING); 798 } 799 800 port = owl_gpio_get_port(pctrl, &gpio); 801 if (WARN_ON(port == NULL)) 802 return; 803 804 gpio_base = pctrl->base + port->offset; 805 806 raw_spin_lock_irqsave(&pctrl->lock, flags); 807 808 owl_gpio_update_reg(gpio_base + port->intc_ctl, 809 OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true); 810 811 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 812 } 813 814 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type) 815 { 816 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 817 struct owl_pinctrl *pctrl = gpiochip_get_data(gc); 818 819 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 820 irq_set_handler_locked(data, handle_level_irq); 821 else 822 irq_set_handler_locked(data, handle_edge_irq); 823 824 irq_set_type(pctrl, data->hwirq, type); 825 826 return 0; 827 } 828 829 static void owl_gpio_irq_handler(struct irq_desc *desc) 830 { 831 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc); 832 struct irq_chip *chip = irq_desc_get_chip(desc); 833 struct irq_domain *domain = pctrl->chip.irq.domain; 834 unsigned int parent = irq_desc_get_irq(desc); 835 const struct owl_gpio_port *port; 836 void __iomem *base; 837 unsigned int pin, irq, offset = 0, i; 838 unsigned long pending_irq; 839 840 chained_irq_enter(chip, desc); 841 842 for (i = 0; i < pctrl->soc->nports; i++) { 843 port = &pctrl->soc->ports[i]; 844 base = pctrl->base + port->offset; 845 846 /* skip ports that are not associated with this irq */ 847 if (parent != pctrl->irq[i]) 848 goto skip; 849 850 pending_irq = readl_relaxed(base + port->intc_pd); 851 852 for_each_set_bit(pin, &pending_irq, port->pins) { 853 irq = irq_find_mapping(domain, offset + pin); 854 generic_handle_irq(irq); 855 856 /* clear pending interrupt */ 857 owl_gpio_update_reg(base + port->intc_pd, pin, true); 858 } 859 860 skip: 861 offset += port->pins; 862 } 863 864 chained_irq_exit(chip, desc); 865 } 866 867 static int owl_gpio_init(struct owl_pinctrl *pctrl) 868 { 869 struct gpio_chip *chip; 870 struct gpio_irq_chip *gpio_irq; 871 int ret, i, j, offset; 872 873 chip = &pctrl->chip; 874 chip->base = -1; 875 chip->ngpio = pctrl->soc->ngpios; 876 chip->label = dev_name(pctrl->dev); 877 chip->parent = pctrl->dev; 878 chip->owner = THIS_MODULE; 879 chip->of_node = pctrl->dev->of_node; 880 881 pctrl->irq_chip.name = chip->of_node->name; 882 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack; 883 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask; 884 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask; 885 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type; 886 887 gpio_irq = &chip->irq; 888 gpio_irq->chip = &pctrl->irq_chip; 889 gpio_irq->handler = handle_simple_irq; 890 gpio_irq->default_type = IRQ_TYPE_NONE; 891 gpio_irq->parent_handler = owl_gpio_irq_handler; 892 gpio_irq->parent_handler_data = pctrl; 893 gpio_irq->num_parents = pctrl->num_irq; 894 gpio_irq->parents = pctrl->irq; 895 896 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio, 897 sizeof(*gpio_irq->map), GFP_KERNEL); 898 if (!gpio_irq->map) 899 return -ENOMEM; 900 901 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) { 902 const struct owl_gpio_port *port = &pctrl->soc->ports[i]; 903 904 for (j = 0; j < port->pins; j++) 905 gpio_irq->map[offset + j] = gpio_irq->parents[i]; 906 907 offset += port->pins; 908 } 909 910 ret = gpiochip_add_data(&pctrl->chip, pctrl); 911 if (ret) { 912 dev_err(pctrl->dev, "failed to register gpiochip\n"); 913 return ret; 914 } 915 916 return 0; 917 } 918 919 int owl_pinctrl_probe(struct platform_device *pdev, 920 struct owl_pinctrl_soc_data *soc_data) 921 { 922 struct owl_pinctrl *pctrl; 923 int ret, i; 924 925 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 926 if (!pctrl) 927 return -ENOMEM; 928 929 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 930 if (IS_ERR(pctrl->base)) 931 return PTR_ERR(pctrl->base); 932 933 /* enable GPIO/MFP clock */ 934 pctrl->clk = devm_clk_get(&pdev->dev, NULL); 935 if (IS_ERR(pctrl->clk)) { 936 dev_err(&pdev->dev, "no clock defined\n"); 937 return PTR_ERR(pctrl->clk); 938 } 939 940 ret = clk_prepare_enable(pctrl->clk); 941 if (ret) { 942 dev_err(&pdev->dev, "clk enable failed\n"); 943 return ret; 944 } 945 946 raw_spin_lock_init(&pctrl->lock); 947 948 owl_pinctrl_desc.name = dev_name(&pdev->dev); 949 owl_pinctrl_desc.pins = soc_data->pins; 950 owl_pinctrl_desc.npins = soc_data->npins; 951 952 pctrl->chip.direction_input = owl_gpio_direction_input; 953 pctrl->chip.direction_output = owl_gpio_direction_output; 954 pctrl->chip.get = owl_gpio_get; 955 pctrl->chip.set = owl_gpio_set; 956 pctrl->chip.request = owl_gpio_request; 957 pctrl->chip.free = owl_gpio_free; 958 959 pctrl->soc = soc_data; 960 pctrl->dev = &pdev->dev; 961 962 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, 963 &owl_pinctrl_desc, pctrl); 964 if (IS_ERR(pctrl->pctrldev)) { 965 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n"); 966 ret = PTR_ERR(pctrl->pctrldev); 967 goto err_exit; 968 } 969 970 ret = platform_irq_count(pdev); 971 if (ret < 0) 972 goto err_exit; 973 974 pctrl->num_irq = ret; 975 976 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq, 977 sizeof(*pctrl->irq), GFP_KERNEL); 978 if (!pctrl->irq) { 979 ret = -ENOMEM; 980 goto err_exit; 981 } 982 983 for (i = 0; i < pctrl->num_irq ; i++) { 984 ret = platform_get_irq(pdev, i); 985 if (ret < 0) 986 goto err_exit; 987 pctrl->irq[i] = ret; 988 } 989 990 ret = owl_gpio_init(pctrl); 991 if (ret) 992 goto err_exit; 993 994 platform_set_drvdata(pdev, pctrl); 995 996 return 0; 997 998 err_exit: 999 clk_disable_unprepare(pctrl->clk); 1000 1001 return ret; 1002 } 1003