1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. 4 * 5 * Copyright (C) 2018-2020 Xilinx Inc. 6 * 7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com> 8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com> 9 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 * 11 * This driver is tested for USB, SGMII, SATA and Display Port currently. 12 * PCIe should also work but that is experimental as of now. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/slab.h> 25 26 #include <dt-bindings/phy/phy.h> 27 28 /* 29 * Lane Registers 30 */ 31 32 /* TX De-emphasis parameters */ 33 #define L0_TX_ANA_TM_18 0x0048 34 #define L0_TX_ANA_TM_118 0x01d8 35 #define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0) 36 37 /* DN Resistor calibration code parameters */ 38 #define L0_TXPMA_ST_3 0x0b0c 39 #define L0_DN_CALIB_CODE 0x3f 40 41 /* PMA control parameters */ 42 #define L0_TXPMD_TM_45 0x0cb4 43 #define L0_TXPMD_TM_48 0x0cc0 44 #define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0) 45 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) 46 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) 47 #define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) 48 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) 49 #define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) 50 51 /* PCS control parameters */ 52 #define L0_TM_DIG_6 0x106c 53 #define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f 54 #define L0_TX_DIG_61 0x00f4 55 #define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f 56 57 /* PLL Test Mode register parameters */ 58 #define L0_TM_PLL_DIG_37 0x2094 59 #define L0_TM_COARSE_CODE_LIMIT 0x10 60 61 /* PLL SSC step size offsets */ 62 #define L0_PLL_SS_STEPS_0_LSB 0x2368 63 #define L0_PLL_SS_STEPS_1_MSB 0x236c 64 #define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 65 #define L0_PLL_SS_STEP_SIZE_1 0x2374 66 #define L0_PLL_SS_STEP_SIZE_2 0x2378 67 #define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c 68 #define L0_PLL_STATUS_READ_1 0x23e4 69 70 /* SSC step size parameters */ 71 #define STEP_SIZE_0_MASK 0xff 72 #define STEP_SIZE_1_MASK 0xff 73 #define STEP_SIZE_2_MASK 0xff 74 #define STEP_SIZE_3_MASK 0x3 75 #define STEP_SIZE_SHIFT 8 76 #define FORCE_STEP_SIZE 0x10 77 #define FORCE_STEPS 0x20 78 #define STEPS_0_MASK 0xff 79 #define STEPS_1_MASK 0x07 80 81 /* Reference clock selection parameters */ 82 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) 83 #define L0_REF_CLK_LCL_SEL BIT(7) 84 #define L0_REF_CLK_SEL_MASK 0x9f 85 86 /* Calibration digital logic parameters */ 87 #define L3_TM_CALIB_DIG19 0xec4c 88 #define L3_CALIB_DONE_STATUS 0xef14 89 #define L3_TM_CALIB_DIG18 0xec48 90 #define L3_TM_CALIB_DIG19_NSW 0x07 91 #define L3_TM_CALIB_DIG18_NSW 0xe0 92 #define L3_TM_OVERRIDE_NSW_CODE 0x20 93 #define L3_CALIB_DONE 0x02 94 #define L3_NSW_SHIFT 5 95 #define L3_NSW_PIPE_SHIFT 4 96 #define L3_NSW_CALIB_SHIFT 3 97 98 #define PHY_REG_OFFSET 0x4000 99 100 /* 101 * Global Registers 102 */ 103 104 /* Refclk selection parameters */ 105 #define PLL_REF_SEL(n) (0x10000 + (n) * 4) 106 #define PLL_FREQ_MASK 0x1f 107 #define PLL_STATUS_LOCKED 0x10 108 109 /* Inter Connect Matrix parameters */ 110 #define ICM_CFG0 0x10010 111 #define ICM_CFG1 0x10014 112 #define ICM_CFG0_L0_MASK 0x07 113 #define ICM_CFG0_L1_MASK 0x70 114 #define ICM_CFG1_L2_MASK 0x07 115 #define ICM_CFG2_L3_MASK 0x70 116 #define ICM_CFG_SHIFT 4 117 118 /* Inter Connect Matrix allowed protocols */ 119 #define ICM_PROTOCOL_PD 0x0 120 #define ICM_PROTOCOL_PCIE 0x1 121 #define ICM_PROTOCOL_SATA 0x2 122 #define ICM_PROTOCOL_USB 0x3 123 #define ICM_PROTOCOL_DP 0x4 124 #define ICM_PROTOCOL_SGMII 0x5 125 126 /* Test Mode common reset control parameters */ 127 #define TM_CMN_RST 0x10018 128 #define TM_CMN_RST_EN 0x1 129 #define TM_CMN_RST_SET 0x2 130 #define TM_CMN_RST_MASK 0x3 131 132 /* Bus width parameters */ 133 #define TX_PROT_BUS_WIDTH 0x10040 134 #define RX_PROT_BUS_WIDTH 0x10044 135 #define PROT_BUS_WIDTH_10 0x0 136 #define PROT_BUS_WIDTH_20 0x1 137 #define PROT_BUS_WIDTH_40 0x2 138 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2) 139 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2) 140 141 /* Number of GT lanes */ 142 #define NUM_LANES 4 143 144 /* SIOU SATA control register */ 145 #define SATA_CONTROL_OFFSET 0x0100 146 147 /* Total number of controllers */ 148 #define CONTROLLERS_PER_LANE 5 149 150 /* Protocol Type parameters */ 151 #define XPSGTR_TYPE_USB0 0 /* USB controller 0 */ 152 #define XPSGTR_TYPE_USB1 1 /* USB controller 1 */ 153 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */ 154 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */ 155 #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */ 156 #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */ 157 #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */ 158 #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */ 159 #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */ 160 #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */ 161 #define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */ 162 #define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */ 163 #define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */ 164 #define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */ 165 166 /* Timeout values */ 167 #define TIMEOUT_US 1000 168 169 /* Lane 0/1/2/3 offset */ 170 #define DIG_8(n) ((0x4000 * (n)) + 0x1074) 171 #define ILL13(n) ((0x4000 * (n)) + 0x1994) 172 #define DIG_10(n) ((0x4000 * (n)) + 0x107c) 173 #define RST_DLY(n) ((0x4000 * (n)) + 0x19a4) 174 #define BYP_15(n) ((0x4000 * (n)) + 0x1038) 175 #define BYP_12(n) ((0x4000 * (n)) + 0x102c) 176 #define MISC3(n) ((0x4000 * (n)) + 0x19ac) 177 #define EQ11(n) ((0x4000 * (n)) + 0x1978) 178 179 static u32 save_reg_address[] = { 180 /* Lane 0/1/2/3 Register */ 181 DIG_8(0), ILL13(0), DIG_10(0), RST_DLY(0), BYP_15(0), BYP_12(0), MISC3(0), EQ11(0), 182 DIG_8(1), ILL13(1), DIG_10(1), RST_DLY(1), BYP_15(1), BYP_12(1), MISC3(1), EQ11(1), 183 DIG_8(2), ILL13(2), DIG_10(2), RST_DLY(2), BYP_15(2), BYP_12(2), MISC3(2), EQ11(2), 184 DIG_8(3), ILL13(3), DIG_10(3), RST_DLY(3), BYP_15(3), BYP_12(3), MISC3(3), EQ11(3), 185 }; 186 187 struct xpsgtr_dev; 188 189 /** 190 * struct xpsgtr_ssc - structure to hold SSC settings for a lane 191 * @refclk_rate: PLL reference clock frequency 192 * @pll_ref_clk: value to be written to register for corresponding ref clk rate 193 * @steps: number of steps of SSC (Spread Spectrum Clock) 194 * @step_size: step size of each step 195 */ 196 struct xpsgtr_ssc { 197 u32 refclk_rate; 198 u8 pll_ref_clk; 199 u32 steps; 200 u32 step_size; 201 }; 202 203 /** 204 * struct xpsgtr_phy - representation of a lane 205 * @phy: pointer to the kernel PHY device 206 * @type: controller which uses this lane 207 * @lane: lane number 208 * @protocol: protocol in which the lane operates 209 * @skip_phy_init: skip phy_init() if true 210 * @dev: pointer to the xpsgtr_dev instance 211 * @refclk: reference clock index 212 */ 213 struct xpsgtr_phy { 214 struct phy *phy; 215 u8 type; 216 u8 lane; 217 u8 protocol; 218 bool skip_phy_init; 219 struct xpsgtr_dev *dev; 220 unsigned int refclk; 221 }; 222 223 /** 224 * struct xpsgtr_dev - representation of a ZynMP GT device 225 * @dev: pointer to device 226 * @serdes: serdes base address 227 * @siou: siou base address 228 * @gtr_mutex: mutex for locking 229 * @phys: PHY lanes 230 * @refclk_sscs: spread spectrum settings for the reference clocks 231 * @clk: reference clocks 232 * @tx_term_fix: fix for GT issue 233 * @saved_icm_cfg0: stored value of ICM CFG0 register 234 * @saved_icm_cfg1: stored value of ICM CFG1 register 235 * @saved_regs: registers to be saved/restored during suspend/resume 236 */ 237 struct xpsgtr_dev { 238 struct device *dev; 239 void __iomem *serdes; 240 void __iomem *siou; 241 struct mutex gtr_mutex; /* mutex for locking */ 242 struct xpsgtr_phy phys[NUM_LANES]; 243 const struct xpsgtr_ssc *refclk_sscs[NUM_LANES]; 244 struct clk *clk[NUM_LANES]; 245 bool tx_term_fix; 246 unsigned int saved_icm_cfg0; 247 unsigned int saved_icm_cfg1; 248 u32 *saved_regs; 249 }; 250 251 /* 252 * Configuration Data 253 */ 254 255 /* lookup table to hold all settings needed for a ref clock frequency */ 256 static const struct xpsgtr_ssc ssc_lookup[] = { 257 { 19200000, 0x05, 608, 264020 }, 258 { 20000000, 0x06, 634, 243454 }, 259 { 24000000, 0x07, 760, 168973 }, 260 { 26000000, 0x08, 824, 143860 }, 261 { 27000000, 0x09, 856, 86551 }, 262 { 38400000, 0x0a, 1218, 65896 }, 263 { 40000000, 0x0b, 634, 243454 }, 264 { 52000000, 0x0c, 824, 143860 }, 265 { 100000000, 0x0d, 1058, 87533 }, 266 { 108000000, 0x0e, 856, 86551 }, 267 { 125000000, 0x0f, 992, 119497 }, 268 { 135000000, 0x10, 1070, 55393 }, 269 { 150000000, 0x11, 792, 187091 } 270 }; 271 272 /* 273 * I/O Accessors 274 */ 275 276 static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg) 277 { 278 return readl(gtr_dev->serdes + reg); 279 } 280 281 static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value) 282 { 283 writel(value, gtr_dev->serdes + reg); 284 } 285 286 static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg, 287 u32 clr, u32 set) 288 { 289 u32 value = xpsgtr_read(gtr_dev, reg); 290 291 value &= ~clr; 292 value |= set; 293 xpsgtr_write(gtr_dev, reg, value); 294 } 295 296 static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg) 297 { 298 void __iomem *addr = gtr_phy->dev->serdes 299 + gtr_phy->lane * PHY_REG_OFFSET + reg; 300 301 return readl(addr); 302 } 303 304 static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy, 305 u32 reg, u32 value) 306 { 307 void __iomem *addr = gtr_phy->dev->serdes 308 + gtr_phy->lane * PHY_REG_OFFSET + reg; 309 310 writel(value, addr); 311 } 312 313 static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy, 314 u32 reg, u32 clr, u32 set) 315 { 316 void __iomem *addr = gtr_phy->dev->serdes 317 + gtr_phy->lane * PHY_REG_OFFSET + reg; 318 319 writel((readl(addr) & ~clr) | set, addr); 320 } 321 322 /** 323 * xpsgtr_save_lane_regs - Saves registers on suspend 324 * @gtr_dev: pointer to phy controller context structure 325 */ 326 static void xpsgtr_save_lane_regs(struct xpsgtr_dev *gtr_dev) 327 { 328 int i; 329 330 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++) 331 gtr_dev->saved_regs[i] = xpsgtr_read(gtr_dev, 332 save_reg_address[i]); 333 } 334 335 /** 336 * xpsgtr_restore_lane_regs - Restores registers on resume 337 * @gtr_dev: pointer to phy controller context structure 338 */ 339 static void xpsgtr_restore_lane_regs(struct xpsgtr_dev *gtr_dev) 340 { 341 int i; 342 343 for (i = 0; i < ARRAY_SIZE(save_reg_address); i++) 344 xpsgtr_write(gtr_dev, save_reg_address[i], 345 gtr_dev->saved_regs[i]); 346 } 347 348 /* 349 * Hardware Configuration 350 */ 351 352 /* Wait for the PLL to lock (with a timeout). */ 353 static int xpsgtr_wait_pll_lock(struct phy *phy) 354 { 355 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); 356 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; 357 unsigned int timeout = TIMEOUT_US; 358 int ret; 359 360 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); 361 362 while (1) { 363 u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1); 364 365 if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) { 366 ret = 0; 367 break; 368 } 369 370 if (--timeout == 0) { 371 ret = -ETIMEDOUT; 372 break; 373 } 374 375 udelay(1); 376 } 377 378 if (ret == -ETIMEDOUT) 379 dev_err(gtr_dev->dev, 380 "lane %u (type %u, protocol %u): PLL lock timeout\n", 381 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); 382 383 return ret; 384 } 385 386 /* Configure PLL and spread-sprectrum clock. */ 387 static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy) 388 { 389 const struct xpsgtr_ssc *ssc; 390 u32 step_size; 391 392 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; 393 step_size = ssc->step_size; 394 395 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), 396 PLL_FREQ_MASK, ssc->pll_ref_clk); 397 398 /* Enable lane clock sharing, if required */ 399 if (gtr_phy->refclk == gtr_phy->lane) 400 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), 401 L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL); 402 else 403 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), 404 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); 405 406 /* SSC step size [7:0] */ 407 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB, 408 STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK); 409 410 /* SSC step size [15:8] */ 411 step_size >>= STEP_SIZE_SHIFT; 412 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1, 413 STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK); 414 415 /* SSC step size [23:16] */ 416 step_size >>= STEP_SIZE_SHIFT; 417 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2, 418 STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK); 419 420 /* SSC steps [7:0] */ 421 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB, 422 STEPS_0_MASK, ssc->steps & STEPS_0_MASK); 423 424 /* SSC steps [10:8] */ 425 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB, 426 STEPS_1_MASK, 427 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); 428 429 /* SSC step size [24:25] */ 430 step_size >>= STEP_SIZE_SHIFT; 431 xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB, 432 STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) | 433 FORCE_STEP_SIZE | FORCE_STEPS); 434 } 435 436 /* Configure the lane protocol. */ 437 static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy) 438 { 439 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; 440 u8 protocol = gtr_phy->protocol; 441 442 switch (gtr_phy->lane) { 443 case 0: 444 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol); 445 break; 446 case 1: 447 xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK, 448 protocol << ICM_CFG_SHIFT); 449 break; 450 case 2: 451 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol); 452 break; 453 case 3: 454 xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK, 455 protocol << ICM_CFG_SHIFT); 456 break; 457 default: 458 /* We already checked 0 <= lane <= 3 */ 459 break; 460 } 461 } 462 463 /* Bypass (de)scrambler and 8b/10b decoder and encoder. */ 464 static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy) 465 { 466 xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER); 467 xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER); 468 } 469 470 /* DP-specific initialization. */ 471 static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy) 472 { 473 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45, 474 L0_TXPMD_TM_45_OVER_DP_MAIN | 475 L0_TXPMD_TM_45_ENABLE_DP_MAIN | 476 L0_TXPMD_TM_45_OVER_DP_POST1 | 477 L0_TXPMD_TM_45_OVER_DP_POST2 | 478 L0_TXPMD_TM_45_ENABLE_DP_POST2); 479 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118, 480 L0_TX_ANA_TM_118_FORCE_17_0); 481 } 482 483 /* SATA-specific initialization. */ 484 static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy) 485 { 486 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; 487 488 xpsgtr_bypass_scrambler_8b10b(gtr_phy); 489 490 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); 491 } 492 493 /* SGMII-specific initialization. */ 494 static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) 495 { 496 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; 497 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); 498 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); 499 500 /* Set SGMII protocol TX and RX bus width to 10 bits. */ 501 xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val); 502 xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val); 503 504 xpsgtr_bypass_scrambler_8b10b(gtr_phy); 505 } 506 507 /* Configure TX de-emphasis and margining for DP. */ 508 static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre, 509 unsigned int voltage) 510 { 511 static const u8 voltage_swing[4][4] = { 512 { 0x2a, 0x27, 0x24, 0x20 }, 513 { 0x27, 0x23, 0x20, 0xff }, 514 { 0x24, 0x20, 0xff, 0xff }, 515 { 0xff, 0xff, 0xff, 0xff } 516 }; 517 static const u8 pre_emphasis[4][4] = { 518 { 0x02, 0x02, 0x02, 0x02 }, 519 { 0x01, 0x01, 0x01, 0xff }, 520 { 0x00, 0x00, 0xff, 0xff }, 521 { 0xff, 0xff, 0xff, 0xff } 522 }; 523 524 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]); 525 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]); 526 } 527 528 /* 529 * PHY Operations 530 */ 531 532 static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy) 533 { 534 /* 535 * As USB may save the snapshot of the states during hibernation, doing 536 * phy_init() will put the USB controller into reset, resulting in the 537 * losing of the saved snapshot. So try to avoid phy_init() for USB 538 * except when gtr_phy->skip_phy_init is false (this happens when FPD is 539 * shutdown during suspend or when gt lane is changed from current one) 540 */ 541 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init) 542 return false; 543 else 544 return true; 545 } 546 547 /* 548 * There is a functional issue in the GT. The TX termination resistance can be 549 * out of spec due to a issue in the calibration logic. This is the workaround 550 * to fix it, required for XCZU9EG silicon. 551 */ 552 static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy) 553 { 554 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; 555 u32 timeout = TIMEOUT_US; 556 u32 nsw; 557 558 /* Enabling Test Mode control for CMN Rest */ 559 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); 560 561 /* Set Test Mode reset */ 562 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN); 563 564 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00); 565 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE); 566 567 /* 568 * As a part of work around sequence for PMOS calibration fix, 569 * we need to configure any lane ICM_CFG to valid protocol. This 570 * will deassert the CMN_Resetn signal. 571 */ 572 xpsgtr_lane_set_protocol(gtr_phy); 573 574 /* Clear Test Mode reset */ 575 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); 576 577 dev_dbg(gtr_dev->dev, "calibrating...\n"); 578 579 do { 580 u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS); 581 582 if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE) 583 break; 584 585 if (!--timeout) { 586 dev_err(gtr_dev->dev, "calibration time out\n"); 587 return -ETIMEDOUT; 588 } 589 590 udelay(1); 591 } while (timeout > 0); 592 593 dev_dbg(gtr_dev->dev, "calibration done\n"); 594 595 /* Reading NMOS Register Code */ 596 nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE; 597 598 /* Set Test Mode reset */ 599 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN); 600 601 /* Writing NMOS register values back [5:3] */ 602 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT); 603 604 /* Writing NMOS register value [2:0] */ 605 xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 606 ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) | 607 (1 << L3_NSW_PIPE_SHIFT)); 608 609 /* Clear Test Mode reset */ 610 xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); 611 612 return 0; 613 } 614 615 static int xpsgtr_phy_init(struct phy *phy) 616 { 617 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); 618 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; 619 int ret = 0; 620 621 mutex_lock(>r_dev->gtr_mutex); 622 623 /* Configure and enable the clock when peripheral phy_init call */ 624 if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk])) 625 goto out; 626 627 /* Skip initialization if not required. */ 628 if (!xpsgtr_phy_init_required(gtr_phy)) 629 goto out; 630 631 if (gtr_dev->tx_term_fix) { 632 ret = xpsgtr_phy_tx_term_fix(gtr_phy); 633 if (ret < 0) 634 goto out; 635 636 gtr_dev->tx_term_fix = false; 637 } 638 639 /* Enable coarse code saturation limiting logic. */ 640 xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT); 641 642 /* 643 * Configure the PLL, the lane protocol, and perform protocol-specific 644 * initialization. 645 */ 646 xpsgtr_configure_pll(gtr_phy); 647 xpsgtr_lane_set_protocol(gtr_phy); 648 649 switch (gtr_phy->protocol) { 650 case ICM_PROTOCOL_DP: 651 xpsgtr_phy_init_dp(gtr_phy); 652 break; 653 654 case ICM_PROTOCOL_SATA: 655 xpsgtr_phy_init_sata(gtr_phy); 656 break; 657 658 case ICM_PROTOCOL_SGMII: 659 xpsgtr_phy_init_sgmii(gtr_phy); 660 break; 661 } 662 663 out: 664 mutex_unlock(>r_dev->gtr_mutex); 665 return ret; 666 } 667 668 static int xpsgtr_phy_exit(struct phy *phy) 669 { 670 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); 671 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; 672 673 gtr_phy->skip_phy_init = false; 674 675 /* Ensure that disable clock only, which configure for lane */ 676 clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]); 677 678 return 0; 679 } 680 681 static int xpsgtr_phy_power_on(struct phy *phy) 682 { 683 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); 684 int ret = 0; 685 686 /* Skip initialization if not required. */ 687 if (!xpsgtr_phy_init_required(gtr_phy)) 688 return ret; 689 /* 690 * Wait for the PLL to lock. For DP, only wait on DP0 to avoid 691 * cumulating waits for both lanes. The user is expected to initialize 692 * lane 0 last. 693 */ 694 if (gtr_phy->protocol != ICM_PROTOCOL_DP || 695 gtr_phy->type == XPSGTR_TYPE_DP_0) 696 ret = xpsgtr_wait_pll_lock(phy); 697 698 return ret; 699 } 700 701 static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts) 702 { 703 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); 704 705 if (gtr_phy->protocol != ICM_PROTOCOL_DP) 706 return 0; 707 708 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]); 709 710 return 0; 711 } 712 713 static const struct phy_ops xpsgtr_phyops = { 714 .init = xpsgtr_phy_init, 715 .exit = xpsgtr_phy_exit, 716 .power_on = xpsgtr_phy_power_on, 717 .configure = xpsgtr_phy_configure, 718 .owner = THIS_MODULE, 719 }; 720 721 /* 722 * OF Xlate Support 723 */ 724 725 /* Set the lane type and protocol based on the PHY type and instance number. */ 726 static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type, 727 unsigned int phy_instance) 728 { 729 unsigned int num_phy_types; 730 const int *phy_types; 731 732 switch (phy_type) { 733 case PHY_TYPE_SATA: { 734 static const int types[] = { 735 XPSGTR_TYPE_SATA_0, 736 XPSGTR_TYPE_SATA_1, 737 }; 738 739 phy_types = types; 740 num_phy_types = ARRAY_SIZE(types); 741 gtr_phy->protocol = ICM_PROTOCOL_SATA; 742 break; 743 } 744 case PHY_TYPE_USB3: { 745 static const int types[] = { 746 XPSGTR_TYPE_USB0, 747 XPSGTR_TYPE_USB1, 748 }; 749 750 phy_types = types; 751 num_phy_types = ARRAY_SIZE(types); 752 gtr_phy->protocol = ICM_PROTOCOL_USB; 753 break; 754 } 755 case PHY_TYPE_DP: { 756 static const int types[] = { 757 XPSGTR_TYPE_DP_0, 758 XPSGTR_TYPE_DP_1, 759 }; 760 761 phy_types = types; 762 num_phy_types = ARRAY_SIZE(types); 763 gtr_phy->protocol = ICM_PROTOCOL_DP; 764 break; 765 } 766 case PHY_TYPE_PCIE: { 767 static const int types[] = { 768 XPSGTR_TYPE_PCIE_0, 769 XPSGTR_TYPE_PCIE_1, 770 XPSGTR_TYPE_PCIE_2, 771 XPSGTR_TYPE_PCIE_3, 772 }; 773 774 phy_types = types; 775 num_phy_types = ARRAY_SIZE(types); 776 gtr_phy->protocol = ICM_PROTOCOL_PCIE; 777 break; 778 } 779 case PHY_TYPE_SGMII: { 780 static const int types[] = { 781 XPSGTR_TYPE_SGMII0, 782 XPSGTR_TYPE_SGMII1, 783 XPSGTR_TYPE_SGMII2, 784 XPSGTR_TYPE_SGMII3, 785 }; 786 787 phy_types = types; 788 num_phy_types = ARRAY_SIZE(types); 789 gtr_phy->protocol = ICM_PROTOCOL_SGMII; 790 break; 791 } 792 default: 793 return -EINVAL; 794 } 795 796 if (phy_instance >= num_phy_types) 797 return -EINVAL; 798 799 gtr_phy->type = phy_types[phy_instance]; 800 return 0; 801 } 802 803 /* 804 * Valid combinations of controllers and lanes (Interconnect Matrix). 805 */ 806 static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = { 807 { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, 808 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 }, 809 { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0, 810 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 }, 811 { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, 812 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 }, 813 { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1, 814 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 } 815 }; 816 817 /* Translate OF phandle and args to PHY instance. */ 818 static struct phy *xpsgtr_xlate(struct device *dev, 819 struct of_phandle_args *args) 820 { 821 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); 822 struct xpsgtr_phy *gtr_phy; 823 unsigned int phy_instance; 824 unsigned int phy_lane; 825 unsigned int phy_type; 826 unsigned int refclk; 827 unsigned int i; 828 int ret; 829 830 if (args->args_count != 4) { 831 dev_err(dev, "Invalid number of cells in 'phy' property\n"); 832 return ERR_PTR(-EINVAL); 833 } 834 835 /* 836 * Get the PHY parameters from the OF arguments and derive the lane 837 * type. 838 */ 839 phy_lane = args->args[0]; 840 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) { 841 dev_err(dev, "Invalid lane number %u\n", phy_lane); 842 return ERR_PTR(-ENODEV); 843 } 844 845 gtr_phy = >r_dev->phys[phy_lane]; 846 phy_type = args->args[1]; 847 phy_instance = args->args[2]; 848 849 guard(mutex)(>r_phy->phy->mutex); 850 ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance); 851 if (ret < 0) { 852 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); 853 return ERR_PTR(ret); 854 } 855 856 refclk = args->args[3]; 857 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || 858 !gtr_dev->refclk_sscs[refclk]) { 859 dev_err(dev, "Invalid reference clock number %u\n", refclk); 860 return ERR_PTR(-EINVAL); 861 } 862 863 gtr_phy->refclk = refclk; 864 865 /* 866 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type 867 * is allowed to operate on the lane. 868 */ 869 for (i = 0; i < CONTROLLERS_PER_LANE; i++) { 870 if (icm_matrix[phy_lane][i] == gtr_phy->type) 871 return gtr_phy->phy; 872 } 873 874 return ERR_PTR(-EINVAL); 875 } 876 877 /* 878 * Power Management 879 */ 880 881 static int xpsgtr_runtime_suspend(struct device *dev) 882 { 883 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); 884 885 /* Save the snapshot ICM_CFG registers. */ 886 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); 887 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); 888 889 xpsgtr_save_lane_regs(gtr_dev); 890 891 return 0; 892 } 893 894 static int xpsgtr_runtime_resume(struct device *dev) 895 { 896 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); 897 unsigned int icm_cfg0, icm_cfg1; 898 unsigned int i; 899 bool skip_phy_init; 900 901 xpsgtr_restore_lane_regs(gtr_dev); 902 903 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); 904 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); 905 906 /* Return if no GT lanes got configured before suspend. */ 907 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1) 908 return 0; 909 910 /* Check if the ICM configurations changed after suspend. */ 911 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 && 912 icm_cfg1 == gtr_dev->saved_icm_cfg1) 913 skip_phy_init = true; 914 else 915 skip_phy_init = false; 916 917 /* Update the skip_phy_init for all gtr_phy instances. */ 918 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++) 919 gtr_dev->phys[i].skip_phy_init = skip_phy_init; 920 921 return 0; 922 } 923 924 static DEFINE_RUNTIME_DEV_PM_OPS(xpsgtr_pm_ops, xpsgtr_runtime_suspend, 925 xpsgtr_runtime_resume, NULL); 926 /* 927 * Probe & Platform Driver 928 */ 929 930 static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev) 931 { 932 unsigned int refclk; 933 934 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { 935 unsigned long rate; 936 unsigned int i; 937 struct clk *clk; 938 char name[8]; 939 940 snprintf(name, sizeof(name), "ref%u", refclk); 941 clk = devm_clk_get_optional(gtr_dev->dev, name); 942 if (IS_ERR(clk)) { 943 return dev_err_probe(gtr_dev->dev, PTR_ERR(clk), 944 "Failed to get ref clock %u\n", 945 refclk); 946 } 947 948 if (!clk) 949 continue; 950 951 gtr_dev->clk[refclk] = clk; 952 953 /* 954 * Get the spread spectrum (SSC) settings for the reference 955 * clock rate. 956 */ 957 rate = clk_get_rate(clk); 958 959 for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) { 960 /* Allow an error of 100 ppm */ 961 unsigned long error = ssc_lookup[i].refclk_rate / 10000; 962 963 if (abs(rate - ssc_lookup[i].refclk_rate) < error) { 964 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; 965 break; 966 } 967 } 968 969 if (i == ARRAY_SIZE(ssc_lookup)) { 970 dev_err(gtr_dev->dev, 971 "Invalid rate %lu for reference clock %u\n", 972 rate, refclk); 973 return -EINVAL; 974 } 975 } 976 977 return 0; 978 } 979 980 static int xpsgtr_probe(struct platform_device *pdev) 981 { 982 struct device_node *np = pdev->dev.of_node; 983 struct xpsgtr_dev *gtr_dev; 984 struct phy_provider *provider; 985 unsigned int port; 986 int ret; 987 988 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); 989 if (!gtr_dev) 990 return -ENOMEM; 991 992 gtr_dev->dev = &pdev->dev; 993 platform_set_drvdata(pdev, gtr_dev); 994 995 mutex_init(>r_dev->gtr_mutex); 996 997 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr")) 998 gtr_dev->tx_term_fix = 999 of_property_read_bool(np, "xlnx,tx-termination-fix"); 1000 1001 /* Acquire resources. */ 1002 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); 1003 if (IS_ERR(gtr_dev->serdes)) 1004 return PTR_ERR(gtr_dev->serdes); 1005 1006 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou"); 1007 if (IS_ERR(gtr_dev->siou)) 1008 return PTR_ERR(gtr_dev->siou); 1009 1010 ret = xpsgtr_get_ref_clocks(gtr_dev); 1011 if (ret) 1012 return ret; 1013 1014 /* Create PHYs. */ 1015 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) { 1016 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port]; 1017 struct phy *phy; 1018 1019 gtr_phy->lane = port; 1020 gtr_phy->dev = gtr_dev; 1021 1022 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); 1023 if (IS_ERR(phy)) { 1024 dev_err(&pdev->dev, "failed to create PHY\n"); 1025 return PTR_ERR(phy); 1026 } 1027 1028 gtr_phy->phy = phy; 1029 phy_set_drvdata(phy, gtr_phy); 1030 } 1031 1032 /* Register the PHY provider. */ 1033 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); 1034 if (IS_ERR(provider)) { 1035 dev_err(&pdev->dev, "registering provider failed\n"); 1036 return PTR_ERR(provider); 1037 } 1038 1039 pm_runtime_set_active(gtr_dev->dev); 1040 pm_runtime_enable(gtr_dev->dev); 1041 1042 ret = pm_runtime_resume_and_get(gtr_dev->dev); 1043 if (ret < 0) { 1044 pm_runtime_disable(gtr_dev->dev); 1045 return ret; 1046 } 1047 1048 gtr_dev->saved_regs = devm_kmalloc(gtr_dev->dev, 1049 sizeof(save_reg_address), 1050 GFP_KERNEL); 1051 if (!gtr_dev->saved_regs) 1052 return -ENOMEM; 1053 1054 return 0; 1055 } 1056 1057 static int xpsgtr_remove(struct platform_device *pdev) 1058 { 1059 struct xpsgtr_dev *gtr_dev = platform_get_drvdata(pdev); 1060 1061 pm_runtime_disable(gtr_dev->dev); 1062 pm_runtime_put_noidle(gtr_dev->dev); 1063 pm_runtime_set_suspended(gtr_dev->dev); 1064 1065 return 0; 1066 } 1067 1068 static const struct of_device_id xpsgtr_of_match[] = { 1069 { .compatible = "xlnx,zynqmp-psgtr", }, 1070 { .compatible = "xlnx,zynqmp-psgtr-v1.1", }, 1071 {}, 1072 }; 1073 MODULE_DEVICE_TABLE(of, xpsgtr_of_match); 1074 1075 static struct platform_driver xpsgtr_driver = { 1076 .probe = xpsgtr_probe, 1077 .remove = xpsgtr_remove, 1078 .driver = { 1079 .name = "xilinx-psgtr", 1080 .of_match_table = xpsgtr_of_match, 1081 .pm = pm_ptr(&xpsgtr_pm_ops), 1082 }, 1083 }; 1084 1085 module_platform_driver(xpsgtr_driver); 1086 1087 MODULE_AUTHOR("Xilinx Inc."); 1088 MODULE_LICENSE("GPL v2"); 1089 MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver"); 1090