xref: /openbmc/linux/drivers/phy/xilinx/phy-zynqmp.c (revision 7eaa0696)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4  *
5  * Copyright (C) 2018-2020 Xilinx Inc.
6  *
7  * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8  * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
9  * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10  *
11  * This driver is tested for USB, SGMII, SATA and Display Port currently.
12  * PCIe should also work but that is experimental as of now.
13  */
14 
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/slab.h>
25 
26 #include <dt-bindings/phy/phy.h>
27 
28 /*
29  * Lane Registers
30  */
31 
32 /* TX De-emphasis parameters */
33 #define L0_TX_ANA_TM_18			0x0048
34 #define L0_TX_ANA_TM_118		0x01d8
35 #define L0_TX_ANA_TM_118_FORCE_17_0	BIT(0)
36 
37 /* DN Resistor calibration code parameters */
38 #define L0_TXPMA_ST_3			0x0b0c
39 #define L0_DN_CALIB_CODE		0x3f
40 
41 /* PMA control parameters */
42 #define L0_TXPMD_TM_45			0x0cb4
43 #define L0_TXPMD_TM_48			0x0cc0
44 #define L0_TXPMD_TM_45_OVER_DP_MAIN	BIT(0)
45 #define L0_TXPMD_TM_45_ENABLE_DP_MAIN	BIT(1)
46 #define L0_TXPMD_TM_45_OVER_DP_POST1	BIT(2)
47 #define L0_TXPMD_TM_45_ENABLE_DP_POST1	BIT(3)
48 #define L0_TXPMD_TM_45_OVER_DP_POST2	BIT(4)
49 #define L0_TXPMD_TM_45_ENABLE_DP_POST2	BIT(5)
50 
51 /* PCS control parameters */
52 #define L0_TM_DIG_6			0x106c
53 #define L0_TM_DIS_DESCRAMBLE_DECODER	0x0f
54 #define L0_TX_DIG_61			0x00f4
55 #define L0_TM_DISABLE_SCRAMBLE_ENCODER	0x0f
56 
57 /* PLL Test Mode register parameters */
58 #define L0_TM_PLL_DIG_37		0x2094
59 #define L0_TM_COARSE_CODE_LIMIT		0x10
60 
61 /* PLL SSC step size offsets */
62 #define L0_PLL_SS_STEPS_0_LSB		0x2368
63 #define L0_PLL_SS_STEPS_1_MSB		0x236c
64 #define L0_PLL_SS_STEP_SIZE_0_LSB	0x2370
65 #define L0_PLL_SS_STEP_SIZE_1		0x2374
66 #define L0_PLL_SS_STEP_SIZE_2		0x2378
67 #define L0_PLL_SS_STEP_SIZE_3_MSB	0x237c
68 #define L0_PLL_STATUS_READ_1		0x23e4
69 
70 /* SSC step size parameters */
71 #define STEP_SIZE_0_MASK		0xff
72 #define STEP_SIZE_1_MASK		0xff
73 #define STEP_SIZE_2_MASK		0xff
74 #define STEP_SIZE_3_MASK		0x3
75 #define STEP_SIZE_SHIFT			8
76 #define FORCE_STEP_SIZE			0x10
77 #define FORCE_STEPS			0x20
78 #define STEPS_0_MASK			0xff
79 #define STEPS_1_MASK			0x07
80 
81 /* Reference clock selection parameters */
82 #define L0_Ln_REF_CLK_SEL(n)		(0x2860 + (n) * 4)
83 #define L0_REF_CLK_LCL_SEL		BIT(7)
84 #define L0_REF_CLK_SEL_MASK		0x9f
85 
86 /* Calibration digital logic parameters */
87 #define L3_TM_CALIB_DIG19		0xec4c
88 #define L3_CALIB_DONE_STATUS		0xef14
89 #define L3_TM_CALIB_DIG18		0xec48
90 #define L3_TM_CALIB_DIG19_NSW		0x07
91 #define L3_TM_CALIB_DIG18_NSW		0xe0
92 #define L3_TM_OVERRIDE_NSW_CODE         0x20
93 #define L3_CALIB_DONE			0x02
94 #define L3_NSW_SHIFT			5
95 #define L3_NSW_PIPE_SHIFT		4
96 #define L3_NSW_CALIB_SHIFT		3
97 
98 #define PHY_REG_OFFSET			0x4000
99 
100 /*
101  * Global Registers
102  */
103 
104 /* Refclk selection parameters */
105 #define PLL_REF_SEL(n)			(0x10000 + (n) * 4)
106 #define PLL_FREQ_MASK			0x1f
107 #define PLL_STATUS_LOCKED		0x10
108 
109 /* Inter Connect Matrix parameters */
110 #define ICM_CFG0			0x10010
111 #define ICM_CFG1			0x10014
112 #define ICM_CFG0_L0_MASK		0x07
113 #define ICM_CFG0_L1_MASK		0x70
114 #define ICM_CFG1_L2_MASK		0x07
115 #define ICM_CFG2_L3_MASK		0x70
116 #define ICM_CFG_SHIFT			4
117 
118 /* Inter Connect Matrix allowed protocols */
119 #define ICM_PROTOCOL_PD			0x0
120 #define ICM_PROTOCOL_PCIE		0x1
121 #define ICM_PROTOCOL_SATA		0x2
122 #define ICM_PROTOCOL_USB		0x3
123 #define ICM_PROTOCOL_DP			0x4
124 #define ICM_PROTOCOL_SGMII		0x5
125 
126 /* Test Mode common reset control  parameters */
127 #define TM_CMN_RST			0x10018
128 #define TM_CMN_RST_EN			0x1
129 #define TM_CMN_RST_SET			0x2
130 #define TM_CMN_RST_MASK			0x3
131 
132 /* Bus width parameters */
133 #define TX_PROT_BUS_WIDTH		0x10040
134 #define RX_PROT_BUS_WIDTH		0x10044
135 #define PROT_BUS_WIDTH_10		0x0
136 #define PROT_BUS_WIDTH_20		0x1
137 #define PROT_BUS_WIDTH_40		0x2
138 #define PROT_BUS_WIDTH_SHIFT(n)		((n) * 2)
139 #define PROT_BUS_WIDTH_MASK(n)		GENMASK((n) * 2 + 1, (n) * 2)
140 
141 /* Number of GT lanes */
142 #define NUM_LANES			4
143 
144 /* SIOU SATA control register */
145 #define SATA_CONTROL_OFFSET		0x0100
146 
147 /* Total number of controllers */
148 #define CONTROLLERS_PER_LANE		5
149 
150 /* Protocol Type parameters */
151 #define XPSGTR_TYPE_USB0		0  /* USB controller 0 */
152 #define XPSGTR_TYPE_USB1		1  /* USB controller 1 */
153 #define XPSGTR_TYPE_SATA_0		2  /* SATA controller lane 0 */
154 #define XPSGTR_TYPE_SATA_1		3  /* SATA controller lane 1 */
155 #define XPSGTR_TYPE_PCIE_0		4  /* PCIe controller lane 0 */
156 #define XPSGTR_TYPE_PCIE_1		5  /* PCIe controller lane 1 */
157 #define XPSGTR_TYPE_PCIE_2		6  /* PCIe controller lane 2 */
158 #define XPSGTR_TYPE_PCIE_3		7  /* PCIe controller lane 3 */
159 #define XPSGTR_TYPE_DP_0		8  /* Display Port controller lane 0 */
160 #define XPSGTR_TYPE_DP_1		9  /* Display Port controller lane 1 */
161 #define XPSGTR_TYPE_SGMII0		10 /* Ethernet SGMII controller 0 */
162 #define XPSGTR_TYPE_SGMII1		11 /* Ethernet SGMII controller 1 */
163 #define XPSGTR_TYPE_SGMII2		12 /* Ethernet SGMII controller 2 */
164 #define XPSGTR_TYPE_SGMII3		13 /* Ethernet SGMII controller 3 */
165 
166 /* Timeout values */
167 #define TIMEOUT_US			1000
168 
169 struct xpsgtr_dev;
170 
171 /**
172  * struct xpsgtr_ssc - structure to hold SSC settings for a lane
173  * @refclk_rate: PLL reference clock frequency
174  * @pll_ref_clk: value to be written to register for corresponding ref clk rate
175  * @steps: number of steps of SSC (Spread Spectrum Clock)
176  * @step_size: step size of each step
177  */
178 struct xpsgtr_ssc {
179 	u32 refclk_rate;
180 	u8  pll_ref_clk;
181 	u32 steps;
182 	u32 step_size;
183 };
184 
185 /**
186  * struct xpsgtr_phy - representation of a lane
187  * @phy: pointer to the kernel PHY device
188  * @type: controller which uses this lane
189  * @lane: lane number
190  * @protocol: protocol in which the lane operates
191  * @skip_phy_init: skip phy_init() if true
192  * @dev: pointer to the xpsgtr_dev instance
193  * @refclk: reference clock index
194  */
195 struct xpsgtr_phy {
196 	struct phy *phy;
197 	u8 type;
198 	u8 lane;
199 	u8 protocol;
200 	bool skip_phy_init;
201 	struct xpsgtr_dev *dev;
202 	unsigned int refclk;
203 };
204 
205 /**
206  * struct xpsgtr_dev - representation of a ZynMP GT device
207  * @dev: pointer to device
208  * @serdes: serdes base address
209  * @siou: siou base address
210  * @gtr_mutex: mutex for locking
211  * @phys: PHY lanes
212  * @refclk_sscs: spread spectrum settings for the reference clocks
213  * @clk: reference clocks
214  * @tx_term_fix: fix for GT issue
215  * @saved_icm_cfg0: stored value of ICM CFG0 register
216  * @saved_icm_cfg1: stored value of ICM CFG1 register
217  */
218 struct xpsgtr_dev {
219 	struct device *dev;
220 	void __iomem *serdes;
221 	void __iomem *siou;
222 	struct mutex gtr_mutex; /* mutex for locking */
223 	struct xpsgtr_phy phys[NUM_LANES];
224 	const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
225 	struct clk *clk[NUM_LANES];
226 	bool tx_term_fix;
227 	unsigned int saved_icm_cfg0;
228 	unsigned int saved_icm_cfg1;
229 };
230 
231 /*
232  * Configuration Data
233  */
234 
235 /* lookup table to hold all settings needed for a ref clock frequency */
236 static const struct xpsgtr_ssc ssc_lookup[] = {
237 	{  19200000, 0x05,  608, 264020 },
238 	{  20000000, 0x06,  634, 243454 },
239 	{  24000000, 0x07,  760, 168973 },
240 	{  26000000, 0x08,  824, 143860 },
241 	{  27000000, 0x09,  856,  86551 },
242 	{  38400000, 0x0a, 1218,  65896 },
243 	{  40000000, 0x0b,  634, 243454 },
244 	{  52000000, 0x0c,  824, 143860 },
245 	{ 100000000, 0x0d, 1058,  87533 },
246 	{ 108000000, 0x0e,  856,  86551 },
247 	{ 125000000, 0x0f,  992, 119497 },
248 	{ 135000000, 0x10, 1070,  55393 },
249 	{ 150000000, 0x11,  792, 187091 }
250 };
251 
252 /*
253  * I/O Accessors
254  */
255 
256 static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
257 {
258 	return readl(gtr_dev->serdes + reg);
259 }
260 
261 static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
262 {
263 	writel(value, gtr_dev->serdes + reg);
264 }
265 
266 static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
267 				  u32 clr, u32 set)
268 {
269 	u32 value = xpsgtr_read(gtr_dev, reg);
270 
271 	value &= ~clr;
272 	value |= set;
273 	xpsgtr_write(gtr_dev, reg, value);
274 }
275 
276 static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
277 {
278 	void __iomem *addr = gtr_phy->dev->serdes
279 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;
280 
281 	return readl(addr);
282 }
283 
284 static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
285 				    u32 reg, u32 value)
286 {
287 	void __iomem *addr = gtr_phy->dev->serdes
288 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;
289 
290 	writel(value, addr);
291 }
292 
293 static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
294 				      u32 reg, u32 clr, u32 set)
295 {
296 	void __iomem *addr = gtr_phy->dev->serdes
297 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;
298 
299 	writel((readl(addr) & ~clr) | set, addr);
300 }
301 
302 /*
303  * Hardware Configuration
304  */
305 
306 /* Wait for the PLL to lock (with a timeout). */
307 static int xpsgtr_wait_pll_lock(struct phy *phy)
308 {
309 	struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
310 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
311 	unsigned int timeout = TIMEOUT_US;
312 	int ret;
313 
314 	dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
315 
316 	while (1) {
317 		u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
318 
319 		if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
320 			ret = 0;
321 			break;
322 		}
323 
324 		if (--timeout == 0) {
325 			ret = -ETIMEDOUT;
326 			break;
327 		}
328 
329 		udelay(1);
330 	}
331 
332 	if (ret == -ETIMEDOUT)
333 		dev_err(gtr_dev->dev,
334 			"lane %u (type %u, protocol %u): PLL lock timeout\n",
335 			gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
336 
337 	return ret;
338 }
339 
340 /* Configure PLL and spread-sprectrum clock. */
341 static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
342 {
343 	const struct xpsgtr_ssc *ssc;
344 	u32 step_size;
345 
346 	ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
347 	step_size = ssc->step_size;
348 
349 	xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
350 		       PLL_FREQ_MASK, ssc->pll_ref_clk);
351 
352 	/* Enable lane clock sharing, if required */
353 	if (gtr_phy->refclk == gtr_phy->lane)
354 		xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
355 			       L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL);
356 	else
357 		xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
358 			       L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
359 
360 	/* SSC step size [7:0] */
361 	xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
362 			   STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
363 
364 	/* SSC step size [15:8] */
365 	step_size >>= STEP_SIZE_SHIFT;
366 	xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
367 			   STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
368 
369 	/* SSC step size [23:16] */
370 	step_size >>= STEP_SIZE_SHIFT;
371 	xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
372 			   STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
373 
374 	/* SSC steps [7:0] */
375 	xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
376 			   STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
377 
378 	/* SSC steps [10:8] */
379 	xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
380 			   STEPS_1_MASK,
381 			   (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
382 
383 	/* SSC step size [24:25] */
384 	step_size >>= STEP_SIZE_SHIFT;
385 	xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
386 			   STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
387 			   FORCE_STEP_SIZE | FORCE_STEPS);
388 }
389 
390 /* Configure the lane protocol. */
391 static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
392 {
393 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
394 	u8 protocol = gtr_phy->protocol;
395 
396 	switch (gtr_phy->lane) {
397 	case 0:
398 		xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
399 		break;
400 	case 1:
401 		xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
402 			       protocol << ICM_CFG_SHIFT);
403 		break;
404 	case 2:
405 		xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
406 		break;
407 	case 3:
408 		xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
409 			       protocol << ICM_CFG_SHIFT);
410 		break;
411 	default:
412 		/* We already checked 0 <= lane <= 3 */
413 		break;
414 	}
415 }
416 
417 /* Bypass (de)scrambler and 8b/10b decoder and encoder. */
418 static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
419 {
420 	xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
421 	xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
422 }
423 
424 /* DP-specific initialization. */
425 static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
426 {
427 	xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
428 			 L0_TXPMD_TM_45_OVER_DP_MAIN |
429 			 L0_TXPMD_TM_45_ENABLE_DP_MAIN |
430 			 L0_TXPMD_TM_45_OVER_DP_POST1 |
431 			 L0_TXPMD_TM_45_OVER_DP_POST2 |
432 			 L0_TXPMD_TM_45_ENABLE_DP_POST2);
433 	xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
434 			 L0_TX_ANA_TM_118_FORCE_17_0);
435 }
436 
437 /* SATA-specific initialization. */
438 static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
439 {
440 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
441 
442 	xpsgtr_bypass_scrambler_8b10b(gtr_phy);
443 
444 	writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
445 }
446 
447 /* SGMII-specific initialization. */
448 static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
449 {
450 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
451 	u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
452 	u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
453 
454 	/* Set SGMII protocol TX and RX bus width to 10 bits. */
455 	xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
456 	xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
457 
458 	xpsgtr_bypass_scrambler_8b10b(gtr_phy);
459 }
460 
461 /* Configure TX de-emphasis and margining for DP. */
462 static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
463 				    unsigned int voltage)
464 {
465 	static const u8 voltage_swing[4][4] = {
466 		{ 0x2a, 0x27, 0x24, 0x20 },
467 		{ 0x27, 0x23, 0x20, 0xff },
468 		{ 0x24, 0x20, 0xff, 0xff },
469 		{ 0xff, 0xff, 0xff, 0xff }
470 	};
471 	static const u8 pre_emphasis[4][4] = {
472 		{ 0x02, 0x02, 0x02, 0x02 },
473 		{ 0x01, 0x01, 0x01, 0xff },
474 		{ 0x00, 0x00, 0xff, 0xff },
475 		{ 0xff, 0xff, 0xff, 0xff }
476 	};
477 
478 	xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
479 	xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
480 }
481 
482 /*
483  * PHY Operations
484  */
485 
486 static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
487 {
488 	/*
489 	 * As USB may save the snapshot of the states during hibernation, doing
490 	 * phy_init() will put the USB controller into reset, resulting in the
491 	 * losing of the saved snapshot. So try to avoid phy_init() for USB
492 	 * except when gtr_phy->skip_phy_init is false (this happens when FPD is
493 	 * shutdown during suspend or when gt lane is changed from current one)
494 	 */
495 	if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
496 		return false;
497 	else
498 		return true;
499 }
500 
501 /*
502  * There is a functional issue in the GT. The TX termination resistance can be
503  * out of spec due to a issue in the calibration logic. This is the workaround
504  * to fix it, required for XCZU9EG silicon.
505  */
506 static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
507 {
508 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
509 	u32 timeout = TIMEOUT_US;
510 	u32 nsw;
511 
512 	/* Enabling Test Mode control for CMN Rest */
513 	xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
514 
515 	/* Set Test Mode reset */
516 	xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
517 
518 	xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
519 	xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
520 
521 	/*
522 	 * As a part of work around sequence for PMOS calibration fix,
523 	 * we need to configure any lane ICM_CFG to valid protocol. This
524 	 * will deassert the CMN_Resetn signal.
525 	 */
526 	xpsgtr_lane_set_protocol(gtr_phy);
527 
528 	/* Clear Test Mode reset */
529 	xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
530 
531 	dev_dbg(gtr_dev->dev, "calibrating...\n");
532 
533 	do {
534 		u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
535 
536 		if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
537 			break;
538 
539 		if (!--timeout) {
540 			dev_err(gtr_dev->dev, "calibration time out\n");
541 			return -ETIMEDOUT;
542 		}
543 
544 		udelay(1);
545 	} while (timeout > 0);
546 
547 	dev_dbg(gtr_dev->dev, "calibration done\n");
548 
549 	/* Reading NMOS Register Code */
550 	nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
551 
552 	/* Set Test Mode reset */
553 	xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
554 
555 	/* Writing NMOS register values back [5:3] */
556 	xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
557 
558 	/* Writing NMOS register value [2:0] */
559 	xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
560 		     ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
561 		     (1 << L3_NSW_PIPE_SHIFT));
562 
563 	/* Clear Test Mode reset */
564 	xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
565 
566 	return 0;
567 }
568 
569 static int xpsgtr_phy_init(struct phy *phy)
570 {
571 	struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
572 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
573 	int ret = 0;
574 
575 	mutex_lock(&gtr_dev->gtr_mutex);
576 
577 	/* Configure and enable the clock when peripheral phy_init call */
578 	if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk]))
579 		goto out;
580 
581 	/* Skip initialization if not required. */
582 	if (!xpsgtr_phy_init_required(gtr_phy))
583 		goto out;
584 
585 	if (gtr_dev->tx_term_fix) {
586 		ret = xpsgtr_phy_tx_term_fix(gtr_phy);
587 		if (ret < 0)
588 			goto out;
589 
590 		gtr_dev->tx_term_fix = false;
591 	}
592 
593 	/* Enable coarse code saturation limiting logic. */
594 	xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
595 
596 	/*
597 	 * Configure the PLL, the lane protocol, and perform protocol-specific
598 	 * initialization.
599 	 */
600 	xpsgtr_configure_pll(gtr_phy);
601 	xpsgtr_lane_set_protocol(gtr_phy);
602 
603 	switch (gtr_phy->protocol) {
604 	case ICM_PROTOCOL_DP:
605 		xpsgtr_phy_init_dp(gtr_phy);
606 		break;
607 
608 	case ICM_PROTOCOL_SATA:
609 		xpsgtr_phy_init_sata(gtr_phy);
610 		break;
611 
612 	case ICM_PROTOCOL_SGMII:
613 		xpsgtr_phy_init_sgmii(gtr_phy);
614 		break;
615 	}
616 
617 out:
618 	mutex_unlock(&gtr_dev->gtr_mutex);
619 	return ret;
620 }
621 
622 static int xpsgtr_phy_exit(struct phy *phy)
623 {
624 	struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
625 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
626 
627 	gtr_phy->skip_phy_init = false;
628 
629 	/* Ensure that disable clock only, which configure for lane */
630 	clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]);
631 
632 	return 0;
633 }
634 
635 static int xpsgtr_phy_power_on(struct phy *phy)
636 {
637 	struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
638 	int ret = 0;
639 
640 	/* Skip initialization if not required. */
641 	if (!xpsgtr_phy_init_required(gtr_phy))
642 		return ret;
643 	/*
644 	 * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
645 	 * cumulating waits for both lanes. The user is expected to initialize
646 	 * lane 0 last.
647 	 */
648 	if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
649 	    gtr_phy->type == XPSGTR_TYPE_DP_0)
650 		ret = xpsgtr_wait_pll_lock(phy);
651 
652 	return ret;
653 }
654 
655 static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
656 {
657 	struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
658 
659 	if (gtr_phy->protocol != ICM_PROTOCOL_DP)
660 		return 0;
661 
662 	xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
663 
664 	return 0;
665 }
666 
667 static const struct phy_ops xpsgtr_phyops = {
668 	.init		= xpsgtr_phy_init,
669 	.exit		= xpsgtr_phy_exit,
670 	.power_on	= xpsgtr_phy_power_on,
671 	.configure	= xpsgtr_phy_configure,
672 	.owner		= THIS_MODULE,
673 };
674 
675 /*
676  * OF Xlate Support
677  */
678 
679 /* Set the lane type and protocol based on the PHY type and instance number. */
680 static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
681 				unsigned int phy_instance)
682 {
683 	unsigned int num_phy_types;
684 	const int *phy_types;
685 
686 	switch (phy_type) {
687 	case PHY_TYPE_SATA: {
688 		static const int types[] = {
689 			XPSGTR_TYPE_SATA_0,
690 			XPSGTR_TYPE_SATA_1,
691 		};
692 
693 		phy_types = types;
694 		num_phy_types = ARRAY_SIZE(types);
695 		gtr_phy->protocol = ICM_PROTOCOL_SATA;
696 		break;
697 	}
698 	case PHY_TYPE_USB3: {
699 		static const int types[] = {
700 			XPSGTR_TYPE_USB0,
701 			XPSGTR_TYPE_USB1,
702 		};
703 
704 		phy_types = types;
705 		num_phy_types = ARRAY_SIZE(types);
706 		gtr_phy->protocol = ICM_PROTOCOL_USB;
707 		break;
708 	}
709 	case PHY_TYPE_DP: {
710 		static const int types[] = {
711 			XPSGTR_TYPE_DP_0,
712 			XPSGTR_TYPE_DP_1,
713 		};
714 
715 		phy_types = types;
716 		num_phy_types = ARRAY_SIZE(types);
717 		gtr_phy->protocol = ICM_PROTOCOL_DP;
718 		break;
719 	}
720 	case PHY_TYPE_PCIE: {
721 		static const int types[] = {
722 			XPSGTR_TYPE_PCIE_0,
723 			XPSGTR_TYPE_PCIE_1,
724 			XPSGTR_TYPE_PCIE_2,
725 			XPSGTR_TYPE_PCIE_3,
726 		};
727 
728 		phy_types = types;
729 		num_phy_types = ARRAY_SIZE(types);
730 		gtr_phy->protocol = ICM_PROTOCOL_PCIE;
731 		break;
732 	}
733 	case PHY_TYPE_SGMII: {
734 		static const int types[] = {
735 			XPSGTR_TYPE_SGMII0,
736 			XPSGTR_TYPE_SGMII1,
737 			XPSGTR_TYPE_SGMII2,
738 			XPSGTR_TYPE_SGMII3,
739 		};
740 
741 		phy_types = types;
742 		num_phy_types = ARRAY_SIZE(types);
743 		gtr_phy->protocol = ICM_PROTOCOL_SGMII;
744 		break;
745 	}
746 	default:
747 		return -EINVAL;
748 	}
749 
750 	if (phy_instance >= num_phy_types)
751 		return -EINVAL;
752 
753 	gtr_phy->type = phy_types[phy_instance];
754 	return 0;
755 }
756 
757 /*
758  * Valid combinations of controllers and lanes (Interconnect Matrix).
759  */
760 static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
761 	{ XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
762 		XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
763 	{ XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
764 		XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
765 	{ XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
766 		XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
767 	{ XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
768 		XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
769 };
770 
771 /* Translate OF phandle and args to PHY instance. */
772 static struct phy *xpsgtr_xlate(struct device *dev,
773 				struct of_phandle_args *args)
774 {
775 	struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
776 	struct xpsgtr_phy *gtr_phy;
777 	unsigned int phy_instance;
778 	unsigned int phy_lane;
779 	unsigned int phy_type;
780 	unsigned int refclk;
781 	unsigned int i;
782 	int ret;
783 
784 	if (args->args_count != 4) {
785 		dev_err(dev, "Invalid number of cells in 'phy' property\n");
786 		return ERR_PTR(-EINVAL);
787 	}
788 
789 	/*
790 	 * Get the PHY parameters from the OF arguments and derive the lane
791 	 * type.
792 	 */
793 	phy_lane = args->args[0];
794 	if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
795 		dev_err(dev, "Invalid lane number %u\n", phy_lane);
796 		return ERR_PTR(-ENODEV);
797 	}
798 
799 	gtr_phy = &gtr_dev->phys[phy_lane];
800 	phy_type = args->args[1];
801 	phy_instance = args->args[2];
802 
803 	ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
804 	if (ret < 0) {
805 		dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
806 		return ERR_PTR(ret);
807 	}
808 
809 	refclk = args->args[3];
810 	if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
811 	    !gtr_dev->refclk_sscs[refclk]) {
812 		dev_err(dev, "Invalid reference clock number %u\n", refclk);
813 		return ERR_PTR(-EINVAL);
814 	}
815 
816 	gtr_phy->refclk = refclk;
817 
818 	/*
819 	 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
820 	 * is allowed to operate on the lane.
821 	 */
822 	for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
823 		if (icm_matrix[phy_lane][i] == gtr_phy->type)
824 			return gtr_phy->phy;
825 	}
826 
827 	return ERR_PTR(-EINVAL);
828 }
829 
830 /*
831  * Power Management
832  */
833 
834 static int xpsgtr_runtime_suspend(struct device *dev)
835 {
836 	struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
837 
838 	/* Save the snapshot ICM_CFG registers. */
839 	gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
840 	gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
841 
842 	return 0;
843 }
844 
845 static int xpsgtr_runtime_resume(struct device *dev)
846 {
847 	struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
848 	unsigned int icm_cfg0, icm_cfg1;
849 	unsigned int i;
850 	bool skip_phy_init;
851 
852 	icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
853 	icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
854 
855 	/* Return if no GT lanes got configured before suspend. */
856 	if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
857 		return 0;
858 
859 	/* Check if the ICM configurations changed after suspend. */
860 	if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
861 	    icm_cfg1 == gtr_dev->saved_icm_cfg1)
862 		skip_phy_init = true;
863 	else
864 		skip_phy_init = false;
865 
866 	/* Update the skip_phy_init for all gtr_phy instances. */
867 	for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
868 		gtr_dev->phys[i].skip_phy_init = skip_phy_init;
869 
870 	return 0;
871 }
872 
873 static DEFINE_RUNTIME_DEV_PM_OPS(xpsgtr_pm_ops, xpsgtr_runtime_suspend,
874 				 xpsgtr_runtime_resume, NULL);
875 /*
876  * Probe & Platform Driver
877  */
878 
879 static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
880 {
881 	unsigned int refclk;
882 
883 	for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {
884 		unsigned long rate;
885 		unsigned int i;
886 		struct clk *clk;
887 		char name[8];
888 
889 		snprintf(name, sizeof(name), "ref%u", refclk);
890 		clk = devm_clk_get_optional(gtr_dev->dev, name);
891 		if (IS_ERR(clk)) {
892 			return dev_err_probe(gtr_dev->dev, PTR_ERR(clk),
893 					     "Failed to get ref clock %u\n",
894 					     refclk);
895 		}
896 
897 		if (!clk)
898 			continue;
899 
900 		gtr_dev->clk[refclk] = clk;
901 
902 		/*
903 		 * Get the spread spectrum (SSC) settings for the reference
904 		 * clock rate.
905 		 */
906 		rate = clk_get_rate(clk);
907 
908 		for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
909 			/* Allow an error of 100 ppm */
910 			unsigned long error = ssc_lookup[i].refclk_rate / 10000;
911 
912 			if (abs(rate - ssc_lookup[i].refclk_rate) < error) {
913 				gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
914 				break;
915 			}
916 		}
917 
918 		if (i == ARRAY_SIZE(ssc_lookup)) {
919 			dev_err(gtr_dev->dev,
920 				"Invalid rate %lu for reference clock %u\n",
921 				rate, refclk);
922 			return -EINVAL;
923 		}
924 	}
925 
926 	return 0;
927 }
928 
929 static int xpsgtr_probe(struct platform_device *pdev)
930 {
931 	struct device_node *np = pdev->dev.of_node;
932 	struct xpsgtr_dev *gtr_dev;
933 	struct phy_provider *provider;
934 	unsigned int port;
935 	int ret;
936 
937 	gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
938 	if (!gtr_dev)
939 		return -ENOMEM;
940 
941 	gtr_dev->dev = &pdev->dev;
942 	platform_set_drvdata(pdev, gtr_dev);
943 
944 	mutex_init(&gtr_dev->gtr_mutex);
945 
946 	if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
947 		gtr_dev->tx_term_fix =
948 			of_property_read_bool(np, "xlnx,tx-termination-fix");
949 
950 	/* Acquire resources. */
951 	gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
952 	if (IS_ERR(gtr_dev->serdes))
953 		return PTR_ERR(gtr_dev->serdes);
954 
955 	gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
956 	if (IS_ERR(gtr_dev->siou))
957 		return PTR_ERR(gtr_dev->siou);
958 
959 	ret = xpsgtr_get_ref_clocks(gtr_dev);
960 	if (ret)
961 		return ret;
962 
963 	/* Create PHYs. */
964 	for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
965 		struct xpsgtr_phy *gtr_phy = &gtr_dev->phys[port];
966 		struct phy *phy;
967 
968 		gtr_phy->lane = port;
969 		gtr_phy->dev = gtr_dev;
970 
971 		phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
972 		if (IS_ERR(phy)) {
973 			dev_err(&pdev->dev, "failed to create PHY\n");
974 			return PTR_ERR(phy);
975 		}
976 
977 		gtr_phy->phy = phy;
978 		phy_set_drvdata(phy, gtr_phy);
979 	}
980 
981 	/* Register the PHY provider. */
982 	provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
983 	if (IS_ERR(provider)) {
984 		dev_err(&pdev->dev, "registering provider failed\n");
985 		return PTR_ERR(provider);
986 	}
987 
988 	pm_runtime_set_active(gtr_dev->dev);
989 	pm_runtime_enable(gtr_dev->dev);
990 
991 	ret = pm_runtime_resume_and_get(gtr_dev->dev);
992 	if (ret < 0) {
993 		pm_runtime_disable(gtr_dev->dev);
994 		return ret;
995 	}
996 
997 	return 0;
998 }
999 
1000 static int xpsgtr_remove(struct platform_device *pdev)
1001 {
1002 	struct xpsgtr_dev *gtr_dev = platform_get_drvdata(pdev);
1003 
1004 	pm_runtime_disable(gtr_dev->dev);
1005 	pm_runtime_put_noidle(gtr_dev->dev);
1006 	pm_runtime_set_suspended(gtr_dev->dev);
1007 
1008 	return 0;
1009 }
1010 
1011 static const struct of_device_id xpsgtr_of_match[] = {
1012 	{ .compatible = "xlnx,zynqmp-psgtr", },
1013 	{ .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1014 	{},
1015 };
1016 MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
1017 
1018 static struct platform_driver xpsgtr_driver = {
1019 	.probe = xpsgtr_probe,
1020 	.remove	= xpsgtr_remove,
1021 	.driver = {
1022 		.name = "xilinx-psgtr",
1023 		.of_match_table	= xpsgtr_of_match,
1024 		.pm =  pm_ptr(&xpsgtr_pm_ops),
1025 	},
1026 };
1027 
1028 module_platform_driver(xpsgtr_driver);
1029 
1030 MODULE_AUTHOR("Xilinx Inc.");
1031 MODULE_LICENSE("GPL v2");
1032 MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");
1033