1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * phy-ti-pipe3 - PIPE3 PHY driver. 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <linux/phy/phy.h> 13 #include <linux/of.h> 14 #include <linux/clk.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/delay.h> 19 #include <linux/phy/omap_control_phy.h> 20 #include <linux/of_platform.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 24 #define PLL_STATUS 0x00000004 25 #define PLL_GO 0x00000008 26 #define PLL_CONFIGURATION1 0x0000000C 27 #define PLL_CONFIGURATION2 0x00000010 28 #define PLL_CONFIGURATION3 0x00000014 29 #define PLL_CONFIGURATION4 0x00000020 30 31 #define PLL_REGM_MASK 0x001FFE00 32 #define PLL_REGM_SHIFT 0x9 33 #define PLL_REGM_F_MASK 0x0003FFFF 34 #define PLL_REGM_F_SHIFT 0x0 35 #define PLL_REGN_MASK 0x000001FE 36 #define PLL_REGN_SHIFT 0x1 37 #define PLL_SELFREQDCO_MASK 0x0000000E 38 #define PLL_SELFREQDCO_SHIFT 0x1 39 #define PLL_SD_MASK 0x0003FC00 40 #define PLL_SD_SHIFT 10 41 #define SET_PLL_GO 0x1 42 #define PLL_LDOPWDN BIT(15) 43 #define PLL_TICOPWDN BIT(16) 44 #define PLL_LOCK 0x2 45 #define PLL_IDLE 0x1 46 47 #define SATA_PLL_SOFT_RESET BIT(18) 48 49 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14) 50 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 51 52 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22) 53 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22 54 55 #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) 56 #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) 57 58 #define PCIE_PCS_MASK 0xFF0000 59 #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 60 61 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C 62 #define INTERFACE_MASK GENMASK(31, 27) 63 #define INTERFACE_SHIFT 27 64 #define INTERFACE_MODE_USBSS BIT(4) 65 #define INTERFACE_MODE_SATA_1P5 BIT(3) 66 #define INTERFACE_MODE_SATA_3P0 BIT(2) 67 #define INTERFACE_MODE_PCIE BIT(0) 68 69 #define LOSD_MASK GENMASK(17, 14) 70 #define LOSD_SHIFT 14 71 #define MEM_PLLDIV GENMASK(6, 5) 72 73 #define PIPE3_PHY_RX_TRIM 0x0000001C 74 #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30) 75 #define MEM_DLL_TRIM_SHIFT 30 76 77 #define PIPE3_PHY_RX_DLL 0x00000024 78 #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30) 79 #define MEM_DLL_PHINT_RATE_SHIFT 30 80 81 #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028 82 #define MEM_HS_RATE_MASK GENMASK(28, 27) 83 #define MEM_HS_RATE_SHIFT 27 84 #define MEM_OVRD_HS_RATE BIT(26) 85 #define MEM_OVRD_HS_RATE_SHIFT 26 86 #define MEM_CDR_FASTLOCK BIT(23) 87 #define MEM_CDR_FASTLOCK_SHIFT 23 88 #define MEM_CDR_LBW_MASK GENMASK(22, 21) 89 #define MEM_CDR_LBW_SHIFT 21 90 #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19) 91 #define MEM_CDR_STEPCNT_SHIFT 19 92 #define MEM_CDR_STL_MASK GENMASK(18, 16) 93 #define MEM_CDR_STL_SHIFT 16 94 #define MEM_CDR_THR_MASK GENMASK(15, 13) 95 #define MEM_CDR_THR_SHIFT 13 96 #define MEM_CDR_THR_MODE BIT(12) 97 #define MEM_CDR_THR_MODE_SHIFT 12 98 #define MEM_CDR_2NDO_SDM_MODE BIT(11) 99 #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11 100 101 #define PIPE3_PHY_RX_EQUALIZER 0x00000038 102 #define MEM_EQLEV_MASK GENMASK(31, 16) 103 #define MEM_EQLEV_SHIFT 16 104 #define MEM_EQFTC_MASK GENMASK(15, 11) 105 #define MEM_EQFTC_SHIFT 11 106 #define MEM_EQCTL_MASK GENMASK(10, 7) 107 #define MEM_EQCTL_SHIFT 7 108 #define MEM_OVRD_EQLEV BIT(2) 109 #define MEM_OVRD_EQLEV_SHIFT 2 110 #define MEM_OVRD_EQFTC BIT(1) 111 #define MEM_OVRD_EQFTC_SHIFT 1 112 113 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44 114 #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9) 115 #define MEM_CDR_LOS_SOURCE_SHIFT 9 116 117 /* 118 * This is an Empirical value that works, need to confirm the actual 119 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status 120 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register. 121 */ 122 #define PLL_IDLE_TIME 100 /* in milliseconds */ 123 #define PLL_LOCK_TIME 100 /* in milliseconds */ 124 125 enum pipe3_mode { PIPE3_MODE_PCIE = 1, 126 PIPE3_MODE_SATA, 127 PIPE3_MODE_USBSS }; 128 129 struct pipe3_dpll_params { 130 u16 m; 131 u8 n; 132 u8 freq:3; 133 u8 sd; 134 u32 mf; 135 }; 136 137 struct pipe3_dpll_map { 138 unsigned long rate; 139 struct pipe3_dpll_params params; 140 }; 141 142 struct pipe3_settings { 143 u8 ana_interface; 144 u8 ana_losd; 145 u8 dig_fastlock; 146 u8 dig_lbw; 147 u8 dig_stepcnt; 148 u8 dig_stl; 149 u8 dig_thr; 150 u8 dig_thr_mode; 151 u8 dig_2ndo_sdm_mode; 152 u8 dig_hs_rate; 153 u8 dig_ovrd_hs_rate; 154 u8 dll_trim_sel; 155 u8 dll_phint_rate; 156 u8 eq_lev; 157 u8 eq_ftc; 158 u8 eq_ctl; 159 u8 eq_ovrd_lev; 160 u8 eq_ovrd_ftc; 161 }; 162 163 struct ti_pipe3 { 164 void __iomem *pll_ctrl_base; 165 void __iomem *phy_rx; 166 void __iomem *phy_tx; 167 struct device *dev; 168 struct device *control_dev; 169 struct clk *wkupclk; 170 struct clk *sys_clk; 171 struct clk *refclk; 172 struct clk *div_clk; 173 struct pipe3_dpll_map *dpll_map; 174 struct regmap *phy_power_syscon; /* ctrl. reg. acces */ 175 struct regmap *pcs_syscon; /* ctrl. reg. acces */ 176 struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */ 177 unsigned int dpll_reset_reg; /* reg. index within syscon */ 178 unsigned int power_reg; /* power reg. index within syscon */ 179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ 180 bool sata_refclk_enabled; 181 enum pipe3_mode mode; 182 struct pipe3_settings settings; 183 }; 184 185 static struct pipe3_dpll_map dpll_map_usb[] = { 186 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ 187 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ 188 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ 189 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ 190 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ 191 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ 192 { }, /* Terminator */ 193 }; 194 195 static struct pipe3_dpll_map dpll_map_sata[] = { 196 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */ 197 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */ 198 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ 199 {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */ 200 {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */ 201 {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */ 202 { }, /* Terminator */ 203 }; 204 205 struct pipe3_data { 206 enum pipe3_mode mode; 207 struct pipe3_dpll_map *dpll_map; 208 struct pipe3_settings settings; 209 }; 210 211 static struct pipe3_data data_usb = { 212 .mode = PIPE3_MODE_USBSS, 213 .dpll_map = dpll_map_usb, 214 .settings = { 215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */ 216 .ana_interface = INTERFACE_MODE_USBSS, 217 .ana_losd = 0xa, 218 .dig_fastlock = 1, 219 .dig_lbw = 3, 220 .dig_stepcnt = 0, 221 .dig_stl = 0x3, 222 .dig_thr = 1, 223 .dig_thr_mode = 1, 224 .dig_2ndo_sdm_mode = 0, 225 .dig_hs_rate = 0, 226 .dig_ovrd_hs_rate = 1, 227 .dll_trim_sel = 0x2, 228 .dll_phint_rate = 0x3, 229 .eq_lev = 0, 230 .eq_ftc = 0, 231 .eq_ctl = 0x9, 232 .eq_ovrd_lev = 0, 233 .eq_ovrd_ftc = 0, 234 }, 235 }; 236 237 static struct pipe3_data data_sata = { 238 .mode = PIPE3_MODE_SATA, 239 .dpll_map = dpll_map_sata, 240 .settings = { 241 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */ 242 .ana_interface = INTERFACE_MODE_SATA_3P0, 243 .ana_losd = 0x5, 244 .dig_fastlock = 1, 245 .dig_lbw = 3, 246 .dig_stepcnt = 0, 247 .dig_stl = 0x3, 248 .dig_thr = 1, 249 .dig_thr_mode = 1, 250 .dig_2ndo_sdm_mode = 0, 251 .dig_hs_rate = 0, /* Not in TRM preferred settings */ 252 .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */ 253 .dll_trim_sel = 0x1, 254 .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */ 255 .eq_lev = 0, 256 .eq_ftc = 0x1f, 257 .eq_ctl = 0, 258 .eq_ovrd_lev = 1, 259 .eq_ovrd_ftc = 1, 260 }, 261 }; 262 263 static struct pipe3_data data_pcie = { 264 .mode = PIPE3_MODE_PCIE, 265 .settings = { 266 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */ 267 .ana_interface = INTERFACE_MODE_PCIE, 268 .ana_losd = 0xa, 269 .dig_fastlock = 1, 270 .dig_lbw = 3, 271 .dig_stepcnt = 0, 272 .dig_stl = 0x3, 273 .dig_thr = 1, 274 .dig_thr_mode = 1, 275 .dig_2ndo_sdm_mode = 0, 276 .dig_hs_rate = 0, 277 .dig_ovrd_hs_rate = 0, 278 .dll_trim_sel = 0x2, 279 .dll_phint_rate = 0x3, 280 .eq_lev = 0, 281 .eq_ftc = 0x1f, 282 .eq_ctl = 1, 283 .eq_ovrd_lev = 0, 284 .eq_ovrd_ftc = 0, 285 }, 286 }; 287 288 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) 289 { 290 return __raw_readl(addr + offset); 291 } 292 293 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset, 294 u32 data) 295 { 296 __raw_writel(data, addr + offset); 297 } 298 299 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) 300 { 301 unsigned long rate; 302 struct pipe3_dpll_map *dpll_map = phy->dpll_map; 303 304 rate = clk_get_rate(phy->sys_clk); 305 306 for (; dpll_map->rate; dpll_map++) { 307 if (rate == dpll_map->rate) 308 return &dpll_map->params; 309 } 310 311 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); 312 313 return NULL; 314 } 315 316 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy); 317 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy); 318 319 static int ti_pipe3_power_off(struct phy *x) 320 { 321 int ret; 322 struct ti_pipe3 *phy = phy_get_drvdata(x); 323 324 if (!phy->phy_power_syscon) { 325 omap_control_phy_power(phy->control_dev, 0); 326 return 0; 327 } 328 329 ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, 330 PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0); 331 return ret; 332 } 333 334 static void ti_pipe3_calibrate(struct ti_pipe3 *phy); 335 336 static int ti_pipe3_power_on(struct phy *x) 337 { 338 u32 val; 339 u32 mask; 340 unsigned long rate; 341 struct ti_pipe3 *phy = phy_get_drvdata(x); 342 bool rx_pending = false; 343 344 if (!phy->phy_power_syscon) { 345 omap_control_phy_power(phy->control_dev, 1); 346 return 0; 347 } 348 349 rate = clk_get_rate(phy->sys_clk); 350 if (!rate) { 351 dev_err(phy->dev, "Invalid clock rate\n"); 352 return -EINVAL; 353 } 354 rate = rate / 1000000; 355 mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; 356 val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; 357 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, 358 mask, val); 359 /* 360 * For PCIe, TX and RX must be powered on simultaneously. 361 * For USB and SATA, TX must be powered on before RX 362 */ 363 mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; 364 if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) { 365 val = PIPE3_PHY_TX_POWERON; 366 rx_pending = true; 367 } else { 368 val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; 369 } 370 371 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, 372 mask, val); 373 374 if (rx_pending) { 375 val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; 376 regmap_update_bits(phy->phy_power_syscon, phy->power_reg, 377 mask, val); 378 } 379 380 if (phy->mode == PIPE3_MODE_PCIE) 381 ti_pipe3_calibrate(phy); 382 383 return 0; 384 } 385 386 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) 387 { 388 u32 val; 389 unsigned long timeout; 390 391 timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME); 392 do { 393 cpu_relax(); 394 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); 395 if (val & PLL_LOCK) 396 return 0; 397 } while (!time_after(jiffies, timeout)); 398 399 dev_err(phy->dev, "DPLL failed to lock\n"); 400 return -EBUSY; 401 } 402 403 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) 404 { 405 u32 val; 406 struct pipe3_dpll_params *dpll_params; 407 408 dpll_params = ti_pipe3_get_dpll_params(phy); 409 if (!dpll_params) 410 return -EINVAL; 411 412 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); 413 val &= ~PLL_REGN_MASK; 414 val |= dpll_params->n << PLL_REGN_SHIFT; 415 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); 416 417 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); 418 val &= ~PLL_SELFREQDCO_MASK; 419 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; 420 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); 421 422 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); 423 val &= ~PLL_REGM_MASK; 424 val |= dpll_params->m << PLL_REGM_SHIFT; 425 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); 426 427 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); 428 val &= ~PLL_REGM_F_MASK; 429 val |= dpll_params->mf << PLL_REGM_F_SHIFT; 430 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); 431 432 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); 433 val &= ~PLL_SD_MASK; 434 val |= dpll_params->sd << PLL_SD_SHIFT; 435 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); 436 437 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); 438 439 return ti_pipe3_dpll_wait_lock(phy); 440 } 441 442 static void ti_pipe3_calibrate(struct ti_pipe3 *phy) 443 { 444 u32 val; 445 struct pipe3_settings *s = &phy->settings; 446 447 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); 448 val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); 449 val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); 450 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); 451 452 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); 453 val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK | 454 MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK | 455 MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE); 456 val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | 457 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT | 458 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT | 459 s->dig_lbw << MEM_CDR_LBW_SHIFT | 460 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT | 461 s->dig_stl << MEM_CDR_STL_SHIFT | 462 s->dig_thr << MEM_CDR_THR_SHIFT | 463 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT | 464 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT; 465 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); 466 467 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); 468 val &= ~MEM_DLL_TRIM_SEL_MASK; 469 val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; 470 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); 471 472 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); 473 val &= ~MEM_DLL_PHINT_RATE_MASK; 474 val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; 475 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); 476 477 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); 478 val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK | 479 MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); 480 val |= s->eq_lev << MEM_EQLEV_SHIFT | 481 s->eq_ftc << MEM_EQFTC_SHIFT | 482 s->eq_ctl << MEM_EQCTL_SHIFT | 483 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT | 484 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT; 485 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); 486 487 if (phy->mode == PIPE3_MODE_SATA) { 488 val = ti_pipe3_readl(phy->phy_rx, 489 SATA_PHY_RX_IO_AND_A2D_OVERRIDES); 490 val &= ~MEM_CDR_LOS_SOURCE_MASK; 491 ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES, 492 val); 493 } 494 } 495 496 static int ti_pipe3_init(struct phy *x) 497 { 498 struct ti_pipe3 *phy = phy_get_drvdata(x); 499 u32 val; 500 int ret = 0; 501 502 ti_pipe3_enable_clocks(phy); 503 /* 504 * Set pcie_pcs register to 0x96 for proper functioning of phy 505 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table 506 * 18-1804. 507 */ 508 if (phy->mode == PIPE3_MODE_PCIE) { 509 if (!phy->pcs_syscon) { 510 omap_control_pcie_pcs(phy->control_dev, 0x96); 511 return 0; 512 } 513 514 val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; 515 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, 516 PCIE_PCS_MASK, val); 517 return ret; 518 } 519 520 /* Bring it out of IDLE if it is IDLE */ 521 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); 522 if (val & PLL_IDLE) { 523 val &= ~PLL_IDLE; 524 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); 525 ret = ti_pipe3_dpll_wait_lock(phy); 526 } 527 528 /* SATA has issues if re-programmed when locked */ 529 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); 530 if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) 531 return ret; 532 533 /* Program the DPLL */ 534 ret = ti_pipe3_dpll_program(phy); 535 if (ret) { 536 ti_pipe3_disable_clocks(phy); 537 return -EINVAL; 538 } 539 540 ti_pipe3_calibrate(phy); 541 542 return ret; 543 } 544 545 static int ti_pipe3_exit(struct phy *x) 546 { 547 struct ti_pipe3 *phy = phy_get_drvdata(x); 548 u32 val; 549 unsigned long timeout; 550 551 /* If dpll_reset_syscon is not present we wont power down SATA DPLL 552 * due to Errata i783 553 */ 554 if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) 555 return 0; 556 557 /* PCIe doesn't have internal DPLL */ 558 if (phy->mode != PIPE3_MODE_PCIE) { 559 /* Put DPLL in IDLE mode */ 560 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); 561 val |= PLL_IDLE; 562 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); 563 564 /* wait for LDO and Oscillator to power down */ 565 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME); 566 do { 567 cpu_relax(); 568 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); 569 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) 570 break; 571 } while (!time_after(jiffies, timeout)); 572 573 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { 574 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", 575 val); 576 return -EBUSY; 577 } 578 } 579 580 /* i783: SATA needs control bit toggle after PLL unlock */ 581 if (phy->mode == PIPE3_MODE_SATA) { 582 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, 583 SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET); 584 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, 585 SATA_PLL_SOFT_RESET, 0); 586 } 587 588 ti_pipe3_disable_clocks(phy); 589 590 return 0; 591 } 592 static const struct phy_ops ops = { 593 .init = ti_pipe3_init, 594 .exit = ti_pipe3_exit, 595 .power_on = ti_pipe3_power_on, 596 .power_off = ti_pipe3_power_off, 597 .owner = THIS_MODULE, 598 }; 599 600 static const struct of_device_id ti_pipe3_id_table[]; 601 602 static int ti_pipe3_get_clk(struct ti_pipe3 *phy) 603 { 604 struct clk *clk; 605 struct device *dev = phy->dev; 606 607 phy->refclk = devm_clk_get(dev, "refclk"); 608 if (IS_ERR(phy->refclk)) { 609 dev_err(dev, "unable to get refclk\n"); 610 /* older DTBs have missing refclk in SATA PHY 611 * so don't bail out in case of SATA PHY. 612 */ 613 if (phy->mode != PIPE3_MODE_SATA) 614 return PTR_ERR(phy->refclk); 615 } 616 617 if (phy->mode != PIPE3_MODE_SATA) { 618 phy->wkupclk = devm_clk_get(dev, "wkupclk"); 619 if (IS_ERR(phy->wkupclk)) { 620 dev_err(dev, "unable to get wkupclk\n"); 621 return PTR_ERR(phy->wkupclk); 622 } 623 } else { 624 phy->wkupclk = ERR_PTR(-ENODEV); 625 } 626 627 if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) { 628 phy->sys_clk = devm_clk_get(dev, "sysclk"); 629 if (IS_ERR(phy->sys_clk)) { 630 dev_err(dev, "unable to get sysclk\n"); 631 return -EINVAL; 632 } 633 } 634 635 if (phy->mode == PIPE3_MODE_PCIE) { 636 clk = devm_clk_get(dev, "dpll_ref"); 637 if (IS_ERR(clk)) { 638 dev_err(dev, "unable to get dpll ref clk\n"); 639 return PTR_ERR(clk); 640 } 641 clk_set_rate(clk, 1500000000); 642 643 clk = devm_clk_get(dev, "dpll_ref_m2"); 644 if (IS_ERR(clk)) { 645 dev_err(dev, "unable to get dpll ref m2 clk\n"); 646 return PTR_ERR(clk); 647 } 648 clk_set_rate(clk, 100000000); 649 650 clk = devm_clk_get(dev, "phy-div"); 651 if (IS_ERR(clk)) { 652 dev_err(dev, "unable to get phy-div clk\n"); 653 return PTR_ERR(clk); 654 } 655 clk_set_rate(clk, 100000000); 656 657 phy->div_clk = devm_clk_get(dev, "div-clk"); 658 if (IS_ERR(phy->div_clk)) { 659 dev_err(dev, "unable to get div-clk\n"); 660 return PTR_ERR(phy->div_clk); 661 } 662 } else { 663 phy->div_clk = ERR_PTR(-ENODEV); 664 } 665 666 return 0; 667 } 668 669 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) 670 { 671 struct device *dev = phy->dev; 672 struct device_node *node = dev->of_node; 673 struct device_node *control_node; 674 struct platform_device *control_pdev; 675 676 phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node, 677 "syscon-phy-power"); 678 if (IS_ERR(phy->phy_power_syscon)) { 679 dev_dbg(dev, 680 "can't get syscon-phy-power, using control device\n"); 681 phy->phy_power_syscon = NULL; 682 } else { 683 if (of_property_read_u32_index(node, 684 "syscon-phy-power", 1, 685 &phy->power_reg)) { 686 dev_err(dev, "couldn't get power reg. offset\n"); 687 return -EINVAL; 688 } 689 } 690 691 if (!phy->phy_power_syscon) { 692 control_node = of_parse_phandle(node, "ctrl-module", 0); 693 if (!control_node) { 694 dev_err(dev, "Failed to get control device phandle\n"); 695 return -EINVAL; 696 } 697 698 control_pdev = of_find_device_by_node(control_node); 699 of_node_put(control_node); 700 if (!control_pdev) { 701 dev_err(dev, "Failed to get control device\n"); 702 return -EINVAL; 703 } 704 705 phy->control_dev = &control_pdev->dev; 706 } 707 708 if (phy->mode == PIPE3_MODE_PCIE) { 709 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node, 710 "syscon-pcs"); 711 if (IS_ERR(phy->pcs_syscon)) { 712 dev_dbg(dev, 713 "can't get syscon-pcs, using omap control\n"); 714 phy->pcs_syscon = NULL; 715 } else { 716 if (of_property_read_u32_index(node, 717 "syscon-pcs", 1, 718 &phy->pcie_pcs_reg)) { 719 dev_err(dev, 720 "couldn't get pcie pcs reg. offset\n"); 721 return -EINVAL; 722 } 723 } 724 } 725 726 if (phy->mode == PIPE3_MODE_SATA) { 727 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node, 728 "syscon-pllreset"); 729 if (IS_ERR(phy->dpll_reset_syscon)) { 730 dev_info(dev, 731 "can't get syscon-pllreset, sata dpll won't idle\n"); 732 phy->dpll_reset_syscon = NULL; 733 } else { 734 if (of_property_read_u32_index(node, 735 "syscon-pllreset", 1, 736 &phy->dpll_reset_reg)) { 737 dev_err(dev, 738 "couldn't get pllreset reg. offset\n"); 739 return -EINVAL; 740 } 741 } 742 } 743 744 return 0; 745 } 746 747 static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) 748 { 749 struct device *dev = phy->dev; 750 struct platform_device *pdev = to_platform_device(dev); 751 752 phy->phy_rx = devm_platform_ioremap_resource_byname(pdev, "phy_rx"); 753 if (IS_ERR(phy->phy_rx)) 754 return PTR_ERR(phy->phy_rx); 755 756 phy->phy_tx = devm_platform_ioremap_resource_byname(pdev, "phy_tx"); 757 758 return PTR_ERR_OR_ZERO(phy->phy_tx); 759 } 760 761 static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) 762 { 763 struct device *dev = phy->dev; 764 struct platform_device *pdev = to_platform_device(dev); 765 766 if (phy->mode == PIPE3_MODE_PCIE) 767 return 0; 768 769 phy->pll_ctrl_base = 770 devm_platform_ioremap_resource_byname(pdev, "pll_ctrl"); 771 return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); 772 } 773 774 static int ti_pipe3_probe(struct platform_device *pdev) 775 { 776 struct ti_pipe3 *phy; 777 struct phy *generic_phy; 778 struct phy_provider *phy_provider; 779 struct device *dev = &pdev->dev; 780 int ret; 781 const struct of_device_id *match; 782 struct pipe3_data *data; 783 784 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 785 if (!phy) 786 return -ENOMEM; 787 788 match = of_match_device(ti_pipe3_id_table, dev); 789 if (!match) 790 return -EINVAL; 791 792 data = (struct pipe3_data *)match->data; 793 if (!data) { 794 dev_err(dev, "no driver data\n"); 795 return -EINVAL; 796 } 797 798 phy->dev = dev; 799 phy->mode = data->mode; 800 phy->dpll_map = data->dpll_map; 801 phy->settings = data->settings; 802 803 ret = ti_pipe3_get_pll_base(phy); 804 if (ret) 805 return ret; 806 807 ret = ti_pipe3_get_tx_rx_base(phy); 808 if (ret) 809 return ret; 810 811 ret = ti_pipe3_get_sysctrl(phy); 812 if (ret) 813 return ret; 814 815 ret = ti_pipe3_get_clk(phy); 816 if (ret) 817 return ret; 818 819 platform_set_drvdata(pdev, phy); 820 pm_runtime_enable(dev); 821 822 /* 823 * Prevent auto-disable of refclk for SATA PHY due to Errata i783 824 */ 825 if (phy->mode == PIPE3_MODE_SATA) { 826 if (!IS_ERR(phy->refclk)) { 827 clk_prepare_enable(phy->refclk); 828 phy->sata_refclk_enabled = true; 829 } 830 } 831 832 generic_phy = devm_phy_create(dev, NULL, &ops); 833 if (IS_ERR(generic_phy)) 834 return PTR_ERR(generic_phy); 835 836 phy_set_drvdata(generic_phy, phy); 837 838 ti_pipe3_power_off(generic_phy); 839 840 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 841 return PTR_ERR_OR_ZERO(phy_provider); 842 } 843 844 static int ti_pipe3_remove(struct platform_device *pdev) 845 { 846 struct ti_pipe3 *phy = platform_get_drvdata(pdev); 847 848 if (phy->mode == PIPE3_MODE_SATA) { 849 clk_disable_unprepare(phy->refclk); 850 phy->sata_refclk_enabled = false; 851 } 852 pm_runtime_disable(&pdev->dev); 853 854 return 0; 855 } 856 857 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy) 858 { 859 int ret = 0; 860 861 if (!IS_ERR(phy->refclk)) { 862 ret = clk_prepare_enable(phy->refclk); 863 if (ret) { 864 dev_err(phy->dev, "Failed to enable refclk %d\n", ret); 865 return ret; 866 } 867 } 868 869 if (!IS_ERR(phy->wkupclk)) { 870 ret = clk_prepare_enable(phy->wkupclk); 871 if (ret) { 872 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); 873 goto disable_refclk; 874 } 875 } 876 877 if (!IS_ERR(phy->div_clk)) { 878 ret = clk_prepare_enable(phy->div_clk); 879 if (ret) { 880 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); 881 goto disable_wkupclk; 882 } 883 } 884 885 return 0; 886 887 disable_wkupclk: 888 if (!IS_ERR(phy->wkupclk)) 889 clk_disable_unprepare(phy->wkupclk); 890 891 disable_refclk: 892 if (!IS_ERR(phy->refclk)) 893 clk_disable_unprepare(phy->refclk); 894 895 return ret; 896 } 897 898 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) 899 { 900 if (!IS_ERR(phy->wkupclk)) 901 clk_disable_unprepare(phy->wkupclk); 902 if (!IS_ERR(phy->refclk)) 903 clk_disable_unprepare(phy->refclk); 904 if (!IS_ERR(phy->div_clk)) 905 clk_disable_unprepare(phy->div_clk); 906 } 907 908 static const struct of_device_id ti_pipe3_id_table[] = { 909 { 910 .compatible = "ti,phy-usb3", 911 .data = &data_usb, 912 }, 913 { 914 .compatible = "ti,omap-usb3", 915 .data = &data_usb, 916 }, 917 { 918 .compatible = "ti,phy-pipe3-sata", 919 .data = &data_sata, 920 }, 921 { 922 .compatible = "ti,phy-pipe3-pcie", 923 .data = &data_pcie, 924 }, 925 {} 926 }; 927 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table); 928 929 static struct platform_driver ti_pipe3_driver = { 930 .probe = ti_pipe3_probe, 931 .remove = ti_pipe3_remove, 932 .driver = { 933 .name = "ti-pipe3", 934 .of_match_table = ti_pipe3_id_table, 935 }, 936 }; 937 938 module_platform_driver(ti_pipe3_driver); 939 940 MODULE_ALIAS("platform:ti_pipe3"); 941 MODULE_AUTHOR("Texas Instruments Inc."); 942 MODULE_DESCRIPTION("TI PIPE3 phy driver"); 943 MODULE_LICENSE("GPL v2"); 944