1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * Copyright (C) 2015 Google, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/clk/tegra.h> 17 #include <linux/delay.h> 18 #include <linux/io.h> 19 #include <linux/mailbox_client.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/reset.h> 26 #include <linux/slab.h> 27 28 #include <soc/tegra/fuse.h> 29 30 #include "xusb.h" 31 32 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \ 33 ((x) ? (11 + ((x) - 1) * 6) : 0) 34 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f 35 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7 36 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf 37 38 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0 39 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f 40 41 #define XUSB_PADCTL_USB2_PAD_MUX 0x004 42 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 16 43 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3 44 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1 45 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 18 46 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3 47 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1 48 49 #define XUSB_PADCTL_USB2_PORT_CAP 0x008 50 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4)) 51 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4)) 52 53 #define XUSB_PADCTL_SS_PORT_MAP 0x014 54 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4)) 55 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5) 56 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5)) 57 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5)) 58 59 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024 60 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31) 61 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) 62 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29) 63 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3)) 64 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \ 65 (1 << (1 + (x) * 3)) 66 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3)) 67 68 #define XUSB_PADCTL_USB3_PAD_MUX 0x028 69 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x))) 70 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x))) 71 72 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40) 73 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7 74 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3 75 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6) 76 77 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40) 78 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29) 79 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27) 80 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26) 81 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0 82 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f 83 84 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40) 85 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26 86 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f 87 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3 88 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf 89 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 90 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1) 91 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0) 92 93 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11) 95 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3 96 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7 97 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7 98 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0 99 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7 100 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2 101 102 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288 103 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26) 104 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19 105 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f 106 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a 107 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12 108 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f 109 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e 110 111 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) 112 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18) 113 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17) 114 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16) 115 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15) 116 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14) 117 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13) 118 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9) 119 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8) 120 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7) 121 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6) 122 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5) 123 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4) 124 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3) 125 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2) 126 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1) 127 128 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20) 129 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0 130 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf 131 132 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20) 133 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8 134 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf 135 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0 136 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff 137 138 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340 139 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19) 140 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12 141 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f 142 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a 143 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5 144 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f 145 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e 146 147 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344 148 149 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 150 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20 151 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff 152 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19 153 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e 154 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16 155 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3 156 #define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15) 157 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4) 158 #define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3) 159 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1 160 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3 161 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0) 162 163 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 164 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4 165 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff 166 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136 167 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2) 168 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1) 169 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0) 170 171 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c 172 #define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19) 173 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15) 174 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12 175 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3 176 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2 177 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0 178 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8) 179 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4 180 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf 181 182 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 183 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16 184 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff 185 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a 186 187 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c 188 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31) 189 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15) 190 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13) 191 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12) 192 193 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40) 194 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20 195 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3 196 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1 197 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18) 198 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13) 199 200 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860 201 202 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864 203 204 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c 205 206 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870 207 208 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c 209 210 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960 211 212 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40) 213 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16 214 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3 215 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2 216 217 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40) 218 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0 219 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff 220 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc 221 222 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40) 223 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f 224 225 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40) 226 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16 227 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff 228 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7 229 230 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40) 231 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368 232 233 struct tegra210_xusb_fuse_calibration { 234 u32 hs_curr_level[4]; 235 u32 hs_term_range_adj; 236 u32 rpd_ctrl; 237 }; 238 239 struct tegra210_xusb_padctl { 240 struct tegra_xusb_padctl base; 241 242 struct tegra210_xusb_fuse_calibration fuse; 243 }; 244 245 static inline struct tegra210_xusb_padctl * 246 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl) 247 { 248 return container_of(padctl, struct tegra210_xusb_padctl, base); 249 } 250 251 /* must be called under padctl->lock */ 252 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl) 253 { 254 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); 255 unsigned long timeout; 256 u32 value; 257 int err; 258 259 if (pcie->enable > 0) { 260 pcie->enable++; 261 return 0; 262 } 263 264 err = clk_prepare_enable(pcie->pll); 265 if (err < 0) 266 return err; 267 268 err = reset_control_deassert(pcie->rst); 269 if (err < 0) 270 goto disable; 271 272 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 273 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << 274 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT); 275 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << 276 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT; 277 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 278 279 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 280 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << 281 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT); 282 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << 283 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT; 284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 285 286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 287 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 289 290 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 291 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 292 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 293 294 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 295 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 296 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 297 298 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 299 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << 300 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) | 301 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK << 302 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT)); 303 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << 304 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) | 305 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; 306 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 307 308 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 309 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << 310 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) | 311 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK << 312 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT)); 313 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << 314 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT; 315 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 316 317 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 318 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; 319 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 320 321 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 322 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << 323 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT); 324 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 325 326 usleep_range(10, 20); 327 328 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 329 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; 330 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 331 332 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 333 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 334 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 335 336 timeout = jiffies + msecs_to_jiffies(100); 337 338 while (time_before(jiffies, timeout)) { 339 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 340 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) 341 break; 342 343 usleep_range(10, 20); 344 } 345 346 if (time_after_eq(jiffies, timeout)) { 347 err = -ETIMEDOUT; 348 goto reset; 349 } 350 351 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 352 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 353 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 354 355 timeout = jiffies + msecs_to_jiffies(100); 356 357 while (time_before(jiffies, timeout)) { 358 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 359 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) 360 break; 361 362 usleep_range(10, 20); 363 } 364 365 if (time_after_eq(jiffies, timeout)) { 366 err = -ETIMEDOUT; 367 goto reset; 368 } 369 370 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 371 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; 372 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 373 374 timeout = jiffies + msecs_to_jiffies(100); 375 376 while (time_before(jiffies, timeout)) { 377 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 378 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) 379 break; 380 381 usleep_range(10, 20); 382 } 383 384 if (time_after_eq(jiffies, timeout)) { 385 err = -ETIMEDOUT; 386 goto reset; 387 } 388 389 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 390 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | 391 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 392 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 393 394 timeout = jiffies + msecs_to_jiffies(100); 395 396 while (time_before(jiffies, timeout)) { 397 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 398 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) 399 break; 400 401 usleep_range(10, 20); 402 } 403 404 if (time_after_eq(jiffies, timeout)) { 405 err = -ETIMEDOUT; 406 goto reset; 407 } 408 409 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 410 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; 411 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 412 413 timeout = jiffies + msecs_to_jiffies(100); 414 415 while (time_before(jiffies, timeout)) { 416 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 417 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) 418 break; 419 420 usleep_range(10, 20); 421 } 422 423 if (time_after_eq(jiffies, timeout)) { 424 err = -ETIMEDOUT; 425 goto reset; 426 } 427 428 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 429 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 430 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 431 432 tegra210_xusb_pll_hw_control_enable(); 433 434 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 435 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 436 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 437 438 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 439 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 440 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 441 442 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 443 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 444 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 445 446 usleep_range(10, 20); 447 448 tegra210_xusb_pll_hw_sequence_start(); 449 450 pcie->enable++; 451 452 return 0; 453 454 reset: 455 reset_control_assert(pcie->rst); 456 disable: 457 clk_disable_unprepare(pcie->pll); 458 return err; 459 } 460 461 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl) 462 { 463 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); 464 465 mutex_lock(&padctl->lock); 466 467 if (WARN_ON(pcie->enable == 0)) 468 goto unlock; 469 470 if (--pcie->enable > 0) 471 goto unlock; 472 473 reset_control_assert(pcie->rst); 474 clk_disable_unprepare(pcie->pll); 475 476 unlock: 477 mutex_unlock(&padctl->lock); 478 } 479 480 /* must be called under padctl->lock */ 481 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb) 482 { 483 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); 484 unsigned long timeout; 485 u32 value; 486 int err; 487 488 if (sata->enable > 0) { 489 sata->enable++; 490 return 0; 491 } 492 493 err = clk_prepare_enable(sata->pll); 494 if (err < 0) 495 return err; 496 497 err = reset_control_deassert(sata->rst); 498 if (err < 0) 499 goto disable; 500 501 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 502 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << 503 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT); 504 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << 505 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT; 506 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 507 508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); 509 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << 510 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT); 511 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << 512 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT; 513 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); 514 515 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 516 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 517 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 518 519 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 520 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 521 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 522 523 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 524 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 525 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 526 527 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 528 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << 529 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) | 530 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK << 531 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT)); 532 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; 533 534 if (usb) 535 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << 536 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT); 537 else 538 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL << 539 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT); 540 541 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN; 542 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 543 544 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 545 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << 546 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) | 547 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK << 548 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT)); 549 550 if (usb) 551 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << 552 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT; 553 else 554 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL << 555 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT; 556 557 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 558 559 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 560 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; 561 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 562 563 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 564 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << 565 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT); 566 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 567 568 usleep_range(10, 20); 569 570 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 571 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; 572 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 573 574 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 575 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 576 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 577 578 timeout = jiffies + msecs_to_jiffies(100); 579 580 while (time_before(jiffies, timeout)) { 581 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 582 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) 583 break; 584 585 usleep_range(10, 20); 586 } 587 588 if (time_after_eq(jiffies, timeout)) { 589 err = -ETIMEDOUT; 590 goto reset; 591 } 592 593 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 594 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 595 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 596 597 timeout = jiffies + msecs_to_jiffies(100); 598 599 while (time_before(jiffies, timeout)) { 600 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 601 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) 602 break; 603 604 usleep_range(10, 20); 605 } 606 607 if (time_after_eq(jiffies, timeout)) { 608 err = -ETIMEDOUT; 609 goto reset; 610 } 611 612 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 613 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; 614 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 615 616 timeout = jiffies + msecs_to_jiffies(100); 617 618 while (time_before(jiffies, timeout)) { 619 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 620 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) 621 break; 622 623 usleep_range(10, 20); 624 } 625 626 if (time_after_eq(jiffies, timeout)) { 627 err = -ETIMEDOUT; 628 goto reset; 629 } 630 631 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 632 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | 633 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 634 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 635 636 timeout = jiffies + msecs_to_jiffies(100); 637 638 while (time_before(jiffies, timeout)) { 639 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 640 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) 641 break; 642 643 usleep_range(10, 20); 644 } 645 646 if (time_after_eq(jiffies, timeout)) { 647 err = -ETIMEDOUT; 648 goto reset; 649 } 650 651 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 652 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; 653 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 654 655 timeout = jiffies + msecs_to_jiffies(100); 656 657 while (time_before(jiffies, timeout)) { 658 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 659 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) 660 break; 661 662 usleep_range(10, 20); 663 } 664 665 if (time_after_eq(jiffies, timeout)) { 666 err = -ETIMEDOUT; 667 goto reset; 668 } 669 670 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 671 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 672 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 673 674 tegra210_sata_pll_hw_control_enable(); 675 676 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 677 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 678 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 679 680 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 681 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 682 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 683 684 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 685 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 686 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 687 688 usleep_range(10, 20); 689 690 tegra210_sata_pll_hw_sequence_start(); 691 692 sata->enable++; 693 694 return 0; 695 696 reset: 697 reset_control_assert(sata->rst); 698 disable: 699 clk_disable_unprepare(sata->pll); 700 return err; 701 } 702 703 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl) 704 { 705 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); 706 707 mutex_lock(&padctl->lock); 708 709 if (WARN_ON(sata->enable == 0)) 710 goto unlock; 711 712 if (--sata->enable > 0) 713 goto unlock; 714 715 reset_control_assert(sata->rst); 716 clk_disable_unprepare(sata->pll); 717 718 unlock: 719 mutex_unlock(&padctl->lock); 720 } 721 722 static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) 723 { 724 u32 value; 725 726 mutex_lock(&padctl->lock); 727 728 if (padctl->enable++ > 0) 729 goto out; 730 731 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 732 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; 733 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 734 735 usleep_range(100, 200); 736 737 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 738 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; 739 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 740 741 usleep_range(100, 200); 742 743 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 744 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; 745 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 746 747 out: 748 mutex_unlock(&padctl->lock); 749 return 0; 750 } 751 752 static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) 753 { 754 u32 value; 755 756 mutex_lock(&padctl->lock); 757 758 if (WARN_ON(padctl->enable == 0)) 759 goto out; 760 761 if (--padctl->enable > 0) 762 goto out; 763 764 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 765 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; 766 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 767 768 usleep_range(100, 200); 769 770 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 771 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; 772 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 773 774 usleep_range(100, 200); 775 776 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 777 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; 778 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 779 780 out: 781 mutex_unlock(&padctl->lock); 782 return 0; 783 } 784 785 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl, 786 unsigned int index, bool idle) 787 { 788 u32 value; 789 790 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 791 792 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | 793 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 | 794 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE); 795 796 if (idle) 797 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | 798 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 | 799 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE; 800 else 801 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | 802 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 | 803 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE); 804 805 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 806 807 return 0; 808 } 809 810 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl, 811 unsigned int index, bool enable) 812 { 813 struct tegra_xusb_port *port; 814 struct tegra_xusb_lane *lane; 815 u32 value, offset; 816 817 port = tegra_xusb_find_port(padctl, "usb3", index); 818 if (!port) 819 return -ENODEV; 820 821 lane = port->lane; 822 823 if (lane->pad == padctl->pcie) 824 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); 825 else 826 offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1; 827 828 value = padctl_readl(padctl, offset); 829 830 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK << 831 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) | 832 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN | 833 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD); 834 835 if (!enable) { 836 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL << 837 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) | 838 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN | 839 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD; 840 } 841 842 padctl_writel(padctl, value, offset); 843 844 return 0; 845 } 846 847 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \ 848 { \ 849 .name = _name, \ 850 .offset = _offset, \ 851 .shift = _shift, \ 852 .mask = _mask, \ 853 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \ 854 .funcs = tegra210_##_type##_functions, \ 855 } 856 857 static const char *tegra210_usb2_functions[] = { 858 "snps", 859 "xusb", 860 "uart" 861 }; 862 863 static const struct tegra_xusb_lane_soc tegra210_usb2_lanes[] = { 864 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2), 865 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2), 866 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2), 867 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2), 868 }; 869 870 static struct tegra_xusb_lane * 871 tegra210_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 872 unsigned int index) 873 { 874 struct tegra_xusb_usb2_lane *usb2; 875 int err; 876 877 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 878 if (!usb2) 879 return ERR_PTR(-ENOMEM); 880 881 INIT_LIST_HEAD(&usb2->base.list); 882 usb2->base.soc = &pad->soc->lanes[index]; 883 usb2->base.index = index; 884 usb2->base.pad = pad; 885 usb2->base.np = np; 886 887 err = tegra_xusb_lane_parse_dt(&usb2->base, np); 888 if (err < 0) { 889 kfree(usb2); 890 return ERR_PTR(err); 891 } 892 893 return &usb2->base; 894 } 895 896 static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane) 897 { 898 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 899 900 kfree(usb2); 901 } 902 903 static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops = { 904 .probe = tegra210_usb2_lane_probe, 905 .remove = tegra210_usb2_lane_remove, 906 }; 907 908 static int tegra210_usb2_phy_init(struct phy *phy) 909 { 910 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 911 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 912 u32 value; 913 914 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); 915 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK << 916 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT); 917 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB << 918 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT; 919 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); 920 921 return tegra210_xusb_padctl_enable(padctl); 922 } 923 924 static int tegra210_usb2_phy_exit(struct phy *phy) 925 { 926 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 927 928 return tegra210_xusb_padctl_disable(lane->pad->padctl); 929 } 930 931 static int tegra210_usb2_phy_power_on(struct phy *phy) 932 { 933 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 934 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 935 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); 936 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 937 struct tegra210_xusb_padctl *priv; 938 struct tegra_xusb_usb2_port *port; 939 unsigned int index = lane->index; 940 u32 value; 941 int err; 942 943 port = tegra_xusb_find_usb2_port(padctl, index); 944 if (!port) { 945 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); 946 return -ENODEV; 947 } 948 949 priv = to_tegra210_xusb_padctl(padctl); 950 951 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 952 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK << 953 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) | 954 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK << 955 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT)); 956 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL << 957 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT); 958 959 if (tegra_sku_info.revision < TEGRA_REVISION_A02) 960 value |= 961 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL << 962 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT); 963 964 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 965 966 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); 967 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index); 968 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); 969 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); 970 971 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 972 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK << 973 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) | 974 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 975 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 976 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 977 value |= (priv->fuse.hs_curr_level[index] + 978 usb2->hs_curr_level_offset) << 979 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT; 980 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 981 982 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 983 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK << 984 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) | 985 (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK << 986 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT) | 987 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 988 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD | 989 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD); 990 value |= (priv->fuse.hs_term_range_adj << 991 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) | 992 (priv->fuse.rpd_ctrl << 993 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT); 994 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 995 996 value = padctl_readl(padctl, 997 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); 998 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK << 999 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT); 1000 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; 1001 padctl_writel(padctl, value, 1002 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); 1003 1004 err = regulator_enable(port->supply); 1005 if (err) 1006 return err; 1007 1008 mutex_lock(&padctl->lock); 1009 1010 if (pad->enable > 0) { 1011 pad->enable++; 1012 mutex_unlock(&padctl->lock); 1013 return 0; 1014 } 1015 1016 err = clk_prepare_enable(pad->clk); 1017 if (err) 1018 goto disable_regulator; 1019 1020 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1021 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << 1022 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | 1023 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK << 1024 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT)); 1025 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << 1026 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | 1027 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL << 1028 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT); 1029 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1030 1031 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1032 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; 1033 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1034 1035 udelay(1); 1036 1037 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1038 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; 1039 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1040 1041 udelay(50); 1042 1043 clk_disable_unprepare(pad->clk); 1044 1045 pad->enable++; 1046 mutex_unlock(&padctl->lock); 1047 1048 return 0; 1049 1050 disable_regulator: 1051 regulator_disable(port->supply); 1052 mutex_unlock(&padctl->lock); 1053 return err; 1054 } 1055 1056 static int tegra210_usb2_phy_power_off(struct phy *phy) 1057 { 1058 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1059 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); 1060 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1061 struct tegra_xusb_usb2_port *port; 1062 u32 value; 1063 1064 port = tegra_xusb_find_usb2_port(padctl, lane->index); 1065 if (!port) { 1066 dev_err(&phy->dev, "no port found for USB2 lane %u\n", 1067 lane->index); 1068 return -ENODEV; 1069 } 1070 1071 mutex_lock(&padctl->lock); 1072 1073 if (WARN_ON(pad->enable == 0)) 1074 goto out; 1075 1076 if (--pad->enable > 0) 1077 goto out; 1078 1079 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1080 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; 1081 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1082 1083 out: 1084 regulator_disable(port->supply); 1085 mutex_unlock(&padctl->lock); 1086 return 0; 1087 } 1088 1089 static const struct phy_ops tegra210_usb2_phy_ops = { 1090 .init = tegra210_usb2_phy_init, 1091 .exit = tegra210_usb2_phy_exit, 1092 .power_on = tegra210_usb2_phy_power_on, 1093 .power_off = tegra210_usb2_phy_power_off, 1094 .owner = THIS_MODULE, 1095 }; 1096 1097 static struct tegra_xusb_pad * 1098 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl, 1099 const struct tegra_xusb_pad_soc *soc, 1100 struct device_node *np) 1101 { 1102 struct tegra_xusb_usb2_pad *usb2; 1103 struct tegra_xusb_pad *pad; 1104 int err; 1105 1106 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 1107 if (!usb2) 1108 return ERR_PTR(-ENOMEM); 1109 1110 pad = &usb2->base; 1111 pad->ops = &tegra210_usb2_lane_ops; 1112 pad->soc = soc; 1113 1114 err = tegra_xusb_pad_init(pad, padctl, np); 1115 if (err < 0) { 1116 kfree(usb2); 1117 goto out; 1118 } 1119 1120 usb2->clk = devm_clk_get(&pad->dev, "trk"); 1121 if (IS_ERR(usb2->clk)) { 1122 err = PTR_ERR(usb2->clk); 1123 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); 1124 goto unregister; 1125 } 1126 1127 err = tegra_xusb_pad_register(pad, &tegra210_usb2_phy_ops); 1128 if (err < 0) 1129 goto unregister; 1130 1131 dev_set_drvdata(&pad->dev, pad); 1132 1133 return pad; 1134 1135 unregister: 1136 device_unregister(&pad->dev); 1137 out: 1138 return ERR_PTR(err); 1139 } 1140 1141 static void tegra210_usb2_pad_remove(struct tegra_xusb_pad *pad) 1142 { 1143 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); 1144 1145 kfree(usb2); 1146 } 1147 1148 static const struct tegra_xusb_pad_ops tegra210_usb2_ops = { 1149 .probe = tegra210_usb2_pad_probe, 1150 .remove = tegra210_usb2_pad_remove, 1151 }; 1152 1153 static const struct tegra_xusb_pad_soc tegra210_usb2_pad = { 1154 .name = "usb2", 1155 .num_lanes = ARRAY_SIZE(tegra210_usb2_lanes), 1156 .lanes = tegra210_usb2_lanes, 1157 .ops = &tegra210_usb2_ops, 1158 }; 1159 1160 static const char *tegra210_hsic_functions[] = { 1161 "snps", 1162 "xusb", 1163 }; 1164 1165 static const struct tegra_xusb_lane_soc tegra210_hsic_lanes[] = { 1166 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic), 1167 }; 1168 1169 static struct tegra_xusb_lane * 1170 tegra210_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 1171 unsigned int index) 1172 { 1173 struct tegra_xusb_hsic_lane *hsic; 1174 int err; 1175 1176 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL); 1177 if (!hsic) 1178 return ERR_PTR(-ENOMEM); 1179 1180 INIT_LIST_HEAD(&hsic->base.list); 1181 hsic->base.soc = &pad->soc->lanes[index]; 1182 hsic->base.index = index; 1183 hsic->base.pad = pad; 1184 hsic->base.np = np; 1185 1186 err = tegra_xusb_lane_parse_dt(&hsic->base, np); 1187 if (err < 0) { 1188 kfree(hsic); 1189 return ERR_PTR(err); 1190 } 1191 1192 return &hsic->base; 1193 } 1194 1195 static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane) 1196 { 1197 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); 1198 1199 kfree(hsic); 1200 } 1201 1202 static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops = { 1203 .probe = tegra210_hsic_lane_probe, 1204 .remove = tegra210_hsic_lane_remove, 1205 }; 1206 1207 static int tegra210_hsic_phy_init(struct phy *phy) 1208 { 1209 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1210 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1211 u32 value; 1212 1213 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); 1214 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK << 1215 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT); 1216 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB << 1217 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT; 1218 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); 1219 1220 return tegra210_xusb_padctl_enable(padctl); 1221 } 1222 1223 static int tegra210_hsic_phy_exit(struct phy *phy) 1224 { 1225 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1226 1227 return tegra210_xusb_padctl_disable(lane->pad->padctl); 1228 } 1229 1230 static int tegra210_hsic_phy_power_on(struct phy *phy) 1231 { 1232 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1233 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); 1234 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); 1235 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1236 struct tegra210_xusb_padctl *priv; 1237 unsigned int index = lane->index; 1238 u32 value; 1239 int err; 1240 1241 priv = to_tegra210_xusb_padctl(padctl); 1242 1243 err = regulator_enable(pad->supply); 1244 if (err) 1245 return err; 1246 1247 padctl_writel(padctl, hsic->strobe_trim, 1248 XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL); 1249 1250 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); 1251 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK << 1252 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT); 1253 value |= (hsic->tx_rtune_p << 1254 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT); 1255 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); 1256 1257 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); 1258 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK << 1259 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) | 1260 (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK << 1261 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT)); 1262 value |= (hsic->rx_strobe_trim << 1263 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) | 1264 (hsic->rx_data_trim << 1265 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT); 1266 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); 1267 1268 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 1269 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | 1270 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 | 1271 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE | 1272 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | 1273 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 | 1274 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE | 1275 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 | 1276 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 | 1277 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE | 1278 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 | 1279 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 | 1280 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE); 1281 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | 1282 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 | 1283 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE; 1284 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 1285 1286 err = clk_prepare_enable(pad->clk); 1287 if (err) 1288 goto disable; 1289 1290 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1291 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK << 1292 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) | 1293 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK << 1294 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT)); 1295 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL << 1296 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) | 1297 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL << 1298 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT); 1299 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1300 1301 udelay(1); 1302 1303 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1304 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK; 1305 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1306 1307 udelay(50); 1308 1309 clk_disable_unprepare(pad->clk); 1310 1311 return 0; 1312 1313 disable: 1314 regulator_disable(pad->supply); 1315 return err; 1316 } 1317 1318 static int tegra210_hsic_phy_power_off(struct phy *phy) 1319 { 1320 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1321 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); 1322 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1323 unsigned int index = lane->index; 1324 u32 value; 1325 1326 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 1327 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | 1328 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 | 1329 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE | 1330 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 | 1331 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 | 1332 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE | 1333 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 | 1334 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 | 1335 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE; 1336 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); 1337 1338 regulator_disable(pad->supply); 1339 1340 return 0; 1341 } 1342 1343 static const struct phy_ops tegra210_hsic_phy_ops = { 1344 .init = tegra210_hsic_phy_init, 1345 .exit = tegra210_hsic_phy_exit, 1346 .power_on = tegra210_hsic_phy_power_on, 1347 .power_off = tegra210_hsic_phy_power_off, 1348 .owner = THIS_MODULE, 1349 }; 1350 1351 static struct tegra_xusb_pad * 1352 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl, 1353 const struct tegra_xusb_pad_soc *soc, 1354 struct device_node *np) 1355 { 1356 struct tegra_xusb_hsic_pad *hsic; 1357 struct tegra_xusb_pad *pad; 1358 int err; 1359 1360 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL); 1361 if (!hsic) 1362 return ERR_PTR(-ENOMEM); 1363 1364 pad = &hsic->base; 1365 pad->ops = &tegra210_hsic_lane_ops; 1366 pad->soc = soc; 1367 1368 err = tegra_xusb_pad_init(pad, padctl, np); 1369 if (err < 0) { 1370 kfree(hsic); 1371 goto out; 1372 } 1373 1374 hsic->clk = devm_clk_get(&pad->dev, "trk"); 1375 if (IS_ERR(hsic->clk)) { 1376 err = PTR_ERR(hsic->clk); 1377 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); 1378 goto unregister; 1379 } 1380 1381 err = tegra_xusb_pad_register(pad, &tegra210_hsic_phy_ops); 1382 if (err < 0) 1383 goto unregister; 1384 1385 dev_set_drvdata(&pad->dev, pad); 1386 1387 return pad; 1388 1389 unregister: 1390 device_unregister(&pad->dev); 1391 out: 1392 return ERR_PTR(err); 1393 } 1394 1395 static void tegra210_hsic_pad_remove(struct tegra_xusb_pad *pad) 1396 { 1397 struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad); 1398 1399 kfree(hsic); 1400 } 1401 1402 static const struct tegra_xusb_pad_ops tegra210_hsic_ops = { 1403 .probe = tegra210_hsic_pad_probe, 1404 .remove = tegra210_hsic_pad_remove, 1405 }; 1406 1407 static const struct tegra_xusb_pad_soc tegra210_hsic_pad = { 1408 .name = "hsic", 1409 .num_lanes = ARRAY_SIZE(tegra210_hsic_lanes), 1410 .lanes = tegra210_hsic_lanes, 1411 .ops = &tegra210_hsic_ops, 1412 }; 1413 1414 static const char *tegra210_pcie_functions[] = { 1415 "pcie-x1", 1416 "usb3-ss", 1417 "sata", 1418 "pcie-x4", 1419 }; 1420 1421 static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = { 1422 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie), 1423 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie), 1424 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie), 1425 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie), 1426 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie), 1427 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie), 1428 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie), 1429 }; 1430 1431 static struct tegra_xusb_lane * 1432 tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 1433 unsigned int index) 1434 { 1435 struct tegra_xusb_pcie_lane *pcie; 1436 int err; 1437 1438 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); 1439 if (!pcie) 1440 return ERR_PTR(-ENOMEM); 1441 1442 INIT_LIST_HEAD(&pcie->base.list); 1443 pcie->base.soc = &pad->soc->lanes[index]; 1444 pcie->base.index = index; 1445 pcie->base.pad = pad; 1446 pcie->base.np = np; 1447 1448 err = tegra_xusb_lane_parse_dt(&pcie->base, np); 1449 if (err < 0) { 1450 kfree(pcie); 1451 return ERR_PTR(err); 1452 } 1453 1454 return &pcie->base; 1455 } 1456 1457 static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane) 1458 { 1459 struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane); 1460 1461 kfree(pcie); 1462 } 1463 1464 static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = { 1465 .probe = tegra210_pcie_lane_probe, 1466 .remove = tegra210_pcie_lane_remove, 1467 }; 1468 1469 static int tegra210_pcie_phy_init(struct phy *phy) 1470 { 1471 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1472 1473 return tegra210_xusb_padctl_enable(lane->pad->padctl); 1474 } 1475 1476 static int tegra210_pcie_phy_exit(struct phy *phy) 1477 { 1478 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1479 1480 return tegra210_xusb_padctl_disable(lane->pad->padctl); 1481 } 1482 1483 static int tegra210_pcie_phy_power_on(struct phy *phy) 1484 { 1485 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1486 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1487 u32 value; 1488 int err; 1489 1490 mutex_lock(&padctl->lock); 1491 1492 err = tegra210_pex_uphy_enable(padctl); 1493 if (err < 0) 1494 goto unlock; 1495 1496 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1497 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); 1498 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1499 1500 unlock: 1501 mutex_unlock(&padctl->lock); 1502 return err; 1503 } 1504 1505 static int tegra210_pcie_phy_power_off(struct phy *phy) 1506 { 1507 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1508 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1509 u32 value; 1510 1511 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1512 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); 1513 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1514 1515 tegra210_pex_uphy_disable(padctl); 1516 1517 return 0; 1518 } 1519 1520 static const struct phy_ops tegra210_pcie_phy_ops = { 1521 .init = tegra210_pcie_phy_init, 1522 .exit = tegra210_pcie_phy_exit, 1523 .power_on = tegra210_pcie_phy_power_on, 1524 .power_off = tegra210_pcie_phy_power_off, 1525 .owner = THIS_MODULE, 1526 }; 1527 1528 static struct tegra_xusb_pad * 1529 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl, 1530 const struct tegra_xusb_pad_soc *soc, 1531 struct device_node *np) 1532 { 1533 struct tegra_xusb_pcie_pad *pcie; 1534 struct tegra_xusb_pad *pad; 1535 int err; 1536 1537 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); 1538 if (!pcie) 1539 return ERR_PTR(-ENOMEM); 1540 1541 pad = &pcie->base; 1542 pad->ops = &tegra210_pcie_lane_ops; 1543 pad->soc = soc; 1544 1545 err = tegra_xusb_pad_init(pad, padctl, np); 1546 if (err < 0) { 1547 kfree(pcie); 1548 goto out; 1549 } 1550 1551 pcie->pll = devm_clk_get(&pad->dev, "pll"); 1552 if (IS_ERR(pcie->pll)) { 1553 err = PTR_ERR(pcie->pll); 1554 dev_err(&pad->dev, "failed to get PLL: %d\n", err); 1555 goto unregister; 1556 } 1557 1558 pcie->rst = devm_reset_control_get(&pad->dev, "phy"); 1559 if (IS_ERR(pcie->rst)) { 1560 err = PTR_ERR(pcie->rst); 1561 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err); 1562 goto unregister; 1563 } 1564 1565 err = tegra_xusb_pad_register(pad, &tegra210_pcie_phy_ops); 1566 if (err < 0) 1567 goto unregister; 1568 1569 dev_set_drvdata(&pad->dev, pad); 1570 1571 return pad; 1572 1573 unregister: 1574 device_unregister(&pad->dev); 1575 out: 1576 return ERR_PTR(err); 1577 } 1578 1579 static void tegra210_pcie_pad_remove(struct tegra_xusb_pad *pad) 1580 { 1581 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad); 1582 1583 kfree(pcie); 1584 } 1585 1586 static const struct tegra_xusb_pad_ops tegra210_pcie_ops = { 1587 .probe = tegra210_pcie_pad_probe, 1588 .remove = tegra210_pcie_pad_remove, 1589 }; 1590 1591 static const struct tegra_xusb_pad_soc tegra210_pcie_pad = { 1592 .name = "pcie", 1593 .num_lanes = ARRAY_SIZE(tegra210_pcie_lanes), 1594 .lanes = tegra210_pcie_lanes, 1595 .ops = &tegra210_pcie_ops, 1596 }; 1597 1598 static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = { 1599 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie), 1600 }; 1601 1602 static struct tegra_xusb_lane * 1603 tegra210_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 1604 unsigned int index) 1605 { 1606 struct tegra_xusb_sata_lane *sata; 1607 int err; 1608 1609 sata = kzalloc(sizeof(*sata), GFP_KERNEL); 1610 if (!sata) 1611 return ERR_PTR(-ENOMEM); 1612 1613 INIT_LIST_HEAD(&sata->base.list); 1614 sata->base.soc = &pad->soc->lanes[index]; 1615 sata->base.index = index; 1616 sata->base.pad = pad; 1617 sata->base.np = np; 1618 1619 err = tegra_xusb_lane_parse_dt(&sata->base, np); 1620 if (err < 0) { 1621 kfree(sata); 1622 return ERR_PTR(err); 1623 } 1624 1625 return &sata->base; 1626 } 1627 1628 static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane) 1629 { 1630 struct tegra_xusb_sata_lane *sata = to_sata_lane(lane); 1631 1632 kfree(sata); 1633 } 1634 1635 static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = { 1636 .probe = tegra210_sata_lane_probe, 1637 .remove = tegra210_sata_lane_remove, 1638 }; 1639 1640 static int tegra210_sata_phy_init(struct phy *phy) 1641 { 1642 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1643 1644 return tegra210_xusb_padctl_enable(lane->pad->padctl); 1645 } 1646 1647 static int tegra210_sata_phy_exit(struct phy *phy) 1648 { 1649 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1650 1651 return tegra210_xusb_padctl_disable(lane->pad->padctl); 1652 } 1653 1654 static int tegra210_sata_phy_power_on(struct phy *phy) 1655 { 1656 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1657 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1658 u32 value; 1659 int err; 1660 1661 mutex_lock(&padctl->lock); 1662 1663 err = tegra210_sata_uphy_enable(padctl, false); 1664 if (err < 0) 1665 goto unlock; 1666 1667 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1668 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); 1669 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1670 1671 unlock: 1672 mutex_unlock(&padctl->lock); 1673 return err; 1674 } 1675 1676 static int tegra210_sata_phy_power_off(struct phy *phy) 1677 { 1678 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1679 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1680 u32 value; 1681 1682 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); 1684 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1685 1686 tegra210_sata_uphy_disable(lane->pad->padctl); 1687 1688 return 0; 1689 } 1690 1691 static const struct phy_ops tegra210_sata_phy_ops = { 1692 .init = tegra210_sata_phy_init, 1693 .exit = tegra210_sata_phy_exit, 1694 .power_on = tegra210_sata_phy_power_on, 1695 .power_off = tegra210_sata_phy_power_off, 1696 .owner = THIS_MODULE, 1697 }; 1698 1699 static struct tegra_xusb_pad * 1700 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl, 1701 const struct tegra_xusb_pad_soc *soc, 1702 struct device_node *np) 1703 { 1704 struct tegra_xusb_sata_pad *sata; 1705 struct tegra_xusb_pad *pad; 1706 int err; 1707 1708 sata = kzalloc(sizeof(*sata), GFP_KERNEL); 1709 if (!sata) 1710 return ERR_PTR(-ENOMEM); 1711 1712 pad = &sata->base; 1713 pad->ops = &tegra210_sata_lane_ops; 1714 pad->soc = soc; 1715 1716 err = tegra_xusb_pad_init(pad, padctl, np); 1717 if (err < 0) { 1718 kfree(sata); 1719 goto out; 1720 } 1721 1722 sata->rst = devm_reset_control_get(&pad->dev, "phy"); 1723 if (IS_ERR(sata->rst)) { 1724 err = PTR_ERR(sata->rst); 1725 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err); 1726 goto unregister; 1727 } 1728 1729 err = tegra_xusb_pad_register(pad, &tegra210_sata_phy_ops); 1730 if (err < 0) 1731 goto unregister; 1732 1733 dev_set_drvdata(&pad->dev, pad); 1734 1735 return pad; 1736 1737 unregister: 1738 device_unregister(&pad->dev); 1739 out: 1740 return ERR_PTR(err); 1741 } 1742 1743 static void tegra210_sata_pad_remove(struct tegra_xusb_pad *pad) 1744 { 1745 struct tegra_xusb_sata_pad *sata = to_sata_pad(pad); 1746 1747 kfree(sata); 1748 } 1749 1750 static const struct tegra_xusb_pad_ops tegra210_sata_ops = { 1751 .probe = tegra210_sata_pad_probe, 1752 .remove = tegra210_sata_pad_remove, 1753 }; 1754 1755 static const struct tegra_xusb_pad_soc tegra210_sata_pad = { 1756 .name = "sata", 1757 .num_lanes = ARRAY_SIZE(tegra210_sata_lanes), 1758 .lanes = tegra210_sata_lanes, 1759 .ops = &tegra210_sata_ops, 1760 }; 1761 1762 static const struct tegra_xusb_pad_soc * const tegra210_pads[] = { 1763 &tegra210_usb2_pad, 1764 &tegra210_hsic_pad, 1765 &tegra210_pcie_pad, 1766 &tegra210_sata_pad, 1767 }; 1768 1769 static int tegra210_usb2_port_enable(struct tegra_xusb_port *port) 1770 { 1771 return 0; 1772 } 1773 1774 static void tegra210_usb2_port_disable(struct tegra_xusb_port *port) 1775 { 1776 } 1777 1778 static struct tegra_xusb_lane * 1779 tegra210_usb2_port_map(struct tegra_xusb_port *port) 1780 { 1781 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); 1782 } 1783 1784 static const struct tegra_xusb_port_ops tegra210_usb2_port_ops = { 1785 .enable = tegra210_usb2_port_enable, 1786 .disable = tegra210_usb2_port_disable, 1787 .map = tegra210_usb2_port_map, 1788 }; 1789 1790 static int tegra210_hsic_port_enable(struct tegra_xusb_port *port) 1791 { 1792 return 0; 1793 } 1794 1795 static void tegra210_hsic_port_disable(struct tegra_xusb_port *port) 1796 { 1797 } 1798 1799 static struct tegra_xusb_lane * 1800 tegra210_hsic_port_map(struct tegra_xusb_port *port) 1801 { 1802 return tegra_xusb_find_lane(port->padctl, "hsic", port->index); 1803 } 1804 1805 static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = { 1806 .enable = tegra210_hsic_port_enable, 1807 .disable = tegra210_hsic_port_disable, 1808 .map = tegra210_hsic_port_map, 1809 }; 1810 1811 static int tegra210_usb3_port_enable(struct tegra_xusb_port *port) 1812 { 1813 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port); 1814 struct tegra_xusb_padctl *padctl = port->padctl; 1815 struct tegra_xusb_lane *lane = usb3->base.lane; 1816 unsigned int index = port->index; 1817 u32 value; 1818 int err; 1819 1820 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); 1821 1822 if (!usb3->internal) 1823 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); 1824 else 1825 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); 1826 1827 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); 1828 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); 1829 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); 1830 1831 /* 1832 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks 1833 * and conditionalize based on mux function? This seems to work, but 1834 * might not be the exact proper sequence. 1835 */ 1836 err = regulator_enable(usb3->supply); 1837 if (err < 0) 1838 return err; 1839 1840 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); 1841 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK << 1842 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT); 1843 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL << 1844 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT; 1845 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); 1846 1847 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); 1848 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK << 1849 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT); 1850 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL << 1851 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT; 1852 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); 1853 1854 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL, 1855 XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index)); 1856 1857 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); 1858 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK << 1859 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT); 1860 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL << 1861 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT; 1862 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); 1863 1864 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL, 1865 XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index)); 1866 1867 if (lane->pad == padctl->sata) 1868 err = tegra210_sata_uphy_enable(padctl, true); 1869 else 1870 err = tegra210_pex_uphy_enable(padctl); 1871 1872 if (err) { 1873 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n", 1874 __func__, err); 1875 return err; 1876 } 1877 1878 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1879 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); 1880 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1881 1882 usleep_range(100, 200); 1883 1884 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1885 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); 1886 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1887 1888 usleep_range(100, 200); 1889 1890 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1891 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); 1892 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1893 1894 return 0; 1895 } 1896 1897 static void tegra210_usb3_port_disable(struct tegra_xusb_port *port) 1898 { 1899 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port); 1900 struct tegra_xusb_padctl *padctl = port->padctl; 1901 struct tegra_xusb_lane *lane = port->lane; 1902 unsigned int index = port->index; 1903 u32 value; 1904 1905 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1906 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); 1907 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1908 1909 usleep_range(100, 200); 1910 1911 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1912 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); 1913 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1914 1915 usleep_range(250, 350); 1916 1917 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1918 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); 1919 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1920 1921 if (lane->pad == padctl->sata) 1922 tegra210_sata_uphy_disable(padctl); 1923 else 1924 tegra210_pex_uphy_disable(padctl); 1925 1926 regulator_disable(usb3->supply); 1927 1928 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); 1929 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); 1930 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); 1931 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); 1932 } 1933 1934 static const struct tegra_xusb_lane_map tegra210_usb3_map[] = { 1935 { 0, "pcie", 6 }, 1936 { 1, "pcie", 5 }, 1937 { 2, "pcie", 0 }, 1938 { 2, "pcie", 3 }, 1939 { 3, "pcie", 4 }, 1940 { 3, "pcie", 4 }, 1941 { 0, NULL, 0 } 1942 }; 1943 1944 static struct tegra_xusb_lane * 1945 tegra210_usb3_port_map(struct tegra_xusb_port *port) 1946 { 1947 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss"); 1948 } 1949 1950 static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = { 1951 .enable = tegra210_usb3_port_enable, 1952 .disable = tegra210_usb3_port_disable, 1953 .map = tegra210_usb3_port_map, 1954 }; 1955 1956 static int 1957 tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse) 1958 { 1959 unsigned int i; 1960 u32 value; 1961 int err; 1962 1963 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); 1964 if (err < 0) 1965 return err; 1966 1967 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { 1968 fuse->hs_curr_level[i] = 1969 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) & 1970 FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK; 1971 } 1972 1973 fuse->hs_term_range_adj = 1974 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) & 1975 FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK; 1976 1977 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); 1978 if (err < 0) 1979 return err; 1980 1981 fuse->rpd_ctrl = 1982 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) & 1983 FUSE_USB_CALIB_EXT_RPD_CTRL_MASK; 1984 1985 return 0; 1986 } 1987 1988 static struct tegra_xusb_padctl * 1989 tegra210_xusb_padctl_probe(struct device *dev, 1990 const struct tegra_xusb_padctl_soc *soc) 1991 { 1992 struct tegra210_xusb_padctl *padctl; 1993 int err; 1994 1995 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL); 1996 if (!padctl) 1997 return ERR_PTR(-ENOMEM); 1998 1999 padctl->base.dev = dev; 2000 padctl->base.soc = soc; 2001 2002 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); 2003 if (err < 0) 2004 return ERR_PTR(err); 2005 2006 return &padctl->base; 2007 } 2008 2009 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) 2010 { 2011 } 2012 2013 static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = { 2014 .probe = tegra210_xusb_padctl_probe, 2015 .remove = tegra210_xusb_padctl_remove, 2016 .usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect, 2017 .hsic_set_idle = tegra210_hsic_set_idle, 2018 }; 2019 2020 const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = { 2021 .num_pads = ARRAY_SIZE(tegra210_pads), 2022 .pads = tegra210_pads, 2023 .ports = { 2024 .usb2 = { 2025 .ops = &tegra210_usb2_port_ops, 2026 .count = 4, 2027 }, 2028 .hsic = { 2029 .ops = &tegra210_hsic_port_ops, 2030 .count = 1, 2031 }, 2032 .usb3 = { 2033 .ops = &tegra210_usb3_port_ops, 2034 .count = 4, 2035 }, 2036 }, 2037 .ops = &tegra210_xusb_padctl_ops, 2038 }; 2039 EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc); 2040 2041 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 2042 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver"); 2043 MODULE_LICENSE("GPL v2"); 2044