1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (C) 2015 Google, Inc. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk/tegra.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/mailbox_client.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/reset.h> 18 #include <linux/slab.h> 19 20 #include <soc/tegra/fuse.h> 21 22 #include "xusb.h" 23 24 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \ 25 ((x) ? (11 + ((x) - 1) * 6) : 0) 26 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f 27 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7 28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf 29 30 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0 31 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f 32 33 #define XUSB_PADCTL_USB2_PAD_MUX 0x004 34 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 16 35 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3 36 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1 37 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 18 38 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3 39 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1 40 41 #define XUSB_PADCTL_USB2_PORT_CAP 0x008 42 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4)) 43 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4)) 44 45 #define XUSB_PADCTL_SS_PORT_MAP 0x014 46 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4)) 47 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5) 48 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5)) 49 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5)) 50 51 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024 52 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31) 53 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) 54 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29) 55 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3)) 56 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \ 57 (1 << (1 + (x) * 3)) 58 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3)) 59 60 #define XUSB_PADCTL_USB3_PAD_MUX 0x028 61 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x))) 62 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x))) 63 64 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40) 65 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7 66 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3 67 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6) 68 69 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40) 70 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29) 71 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27) 72 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26) 73 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0 74 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f 75 76 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40) 77 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26 78 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f 79 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3 80 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf 81 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 82 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1) 83 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0) 84 85 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 86 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11) 87 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3 88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7 89 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7 90 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0 91 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7 92 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2 93 94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288 95 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26) 96 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19 97 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f 98 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a 99 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12 100 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f 101 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e 102 103 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) 104 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18) 105 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17) 106 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16) 107 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15) 108 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14) 109 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13) 110 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9) 111 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8) 112 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7) 113 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6) 114 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5) 115 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4) 116 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3) 117 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2) 118 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1) 119 120 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20) 121 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0 122 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf 123 124 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20) 125 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8 126 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf 127 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0 128 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff 129 130 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340 131 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19) 132 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12 133 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f 134 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a 135 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5 136 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f 137 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e 138 139 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344 140 141 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 142 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20 143 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff 144 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19 145 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e 146 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16 147 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3 148 #define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15) 149 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4) 150 #define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3) 151 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1 152 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3 153 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0) 154 155 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 156 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4 157 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff 158 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136 159 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2) 160 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1) 161 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0) 162 163 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c 164 #define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19) 165 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15) 166 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12 167 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3 168 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2 169 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0 170 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8) 171 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4 172 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf 173 174 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 175 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16 176 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff 177 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a 178 179 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c 180 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31) 181 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15) 182 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13) 183 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12) 184 185 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40) 186 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20 187 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3 188 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1 189 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18) 190 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13) 191 192 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860 193 194 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864 195 196 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c 197 198 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870 199 200 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c 201 202 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960 203 204 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40) 205 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16 206 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3 207 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2 208 209 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40) 210 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0 211 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff 212 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc 213 214 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40) 215 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f 216 217 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40) 218 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16 219 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff 220 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7 221 222 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40) 223 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368 224 225 struct tegra210_xusb_fuse_calibration { 226 u32 hs_curr_level[4]; 227 u32 hs_term_range_adj; 228 u32 rpd_ctrl; 229 }; 230 231 struct tegra210_xusb_padctl { 232 struct tegra_xusb_padctl base; 233 234 struct tegra210_xusb_fuse_calibration fuse; 235 }; 236 237 static inline struct tegra210_xusb_padctl * 238 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl) 239 { 240 return container_of(padctl, struct tegra210_xusb_padctl, base); 241 } 242 243 /* must be called under padctl->lock */ 244 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl) 245 { 246 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); 247 unsigned long timeout; 248 u32 value; 249 int err; 250 251 if (pcie->enable > 0) { 252 pcie->enable++; 253 return 0; 254 } 255 256 err = clk_prepare_enable(pcie->pll); 257 if (err < 0) 258 return err; 259 260 err = reset_control_deassert(pcie->rst); 261 if (err < 0) 262 goto disable; 263 264 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 265 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << 266 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT); 267 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << 268 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT; 269 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 270 271 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 272 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << 273 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT); 274 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << 275 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT; 276 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 277 278 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 279 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 280 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 281 282 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 283 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 285 286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 287 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 288 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 289 290 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 291 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << 292 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) | 293 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK << 294 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT)); 295 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << 296 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) | 297 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; 298 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 299 300 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 301 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << 302 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) | 303 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK << 304 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT)); 305 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << 306 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT; 307 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 308 309 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 310 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; 311 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 312 313 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 314 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << 315 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT); 316 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 317 318 usleep_range(10, 20); 319 320 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 321 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; 322 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 323 324 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 325 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 326 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 327 328 timeout = jiffies + msecs_to_jiffies(100); 329 330 while (time_before(jiffies, timeout)) { 331 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 332 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) 333 break; 334 335 usleep_range(10, 20); 336 } 337 338 if (time_after_eq(jiffies, timeout)) { 339 err = -ETIMEDOUT; 340 goto reset; 341 } 342 343 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 344 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 345 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 346 347 timeout = jiffies + msecs_to_jiffies(100); 348 349 while (time_before(jiffies, timeout)) { 350 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 351 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) 352 break; 353 354 usleep_range(10, 20); 355 } 356 357 if (time_after_eq(jiffies, timeout)) { 358 err = -ETIMEDOUT; 359 goto reset; 360 } 361 362 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 363 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; 364 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 365 366 timeout = jiffies + msecs_to_jiffies(100); 367 368 while (time_before(jiffies, timeout)) { 369 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 370 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) 371 break; 372 373 usleep_range(10, 20); 374 } 375 376 if (time_after_eq(jiffies, timeout)) { 377 err = -ETIMEDOUT; 378 goto reset; 379 } 380 381 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 382 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | 383 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 384 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 385 386 timeout = jiffies + msecs_to_jiffies(100); 387 388 while (time_before(jiffies, timeout)) { 389 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 390 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) 391 break; 392 393 usleep_range(10, 20); 394 } 395 396 if (time_after_eq(jiffies, timeout)) { 397 err = -ETIMEDOUT; 398 goto reset; 399 } 400 401 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 402 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; 403 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 404 405 timeout = jiffies + msecs_to_jiffies(100); 406 407 while (time_before(jiffies, timeout)) { 408 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 409 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) 410 break; 411 412 usleep_range(10, 20); 413 } 414 415 if (time_after_eq(jiffies, timeout)) { 416 err = -ETIMEDOUT; 417 goto reset; 418 } 419 420 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 421 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 422 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 423 424 tegra210_xusb_pll_hw_control_enable(); 425 426 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 427 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 428 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 429 430 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 431 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 432 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 433 434 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 435 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 436 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 437 438 usleep_range(10, 20); 439 440 tegra210_xusb_pll_hw_sequence_start(); 441 442 pcie->enable++; 443 444 return 0; 445 446 reset: 447 reset_control_assert(pcie->rst); 448 disable: 449 clk_disable_unprepare(pcie->pll); 450 return err; 451 } 452 453 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl) 454 { 455 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); 456 457 mutex_lock(&padctl->lock); 458 459 if (WARN_ON(pcie->enable == 0)) 460 goto unlock; 461 462 if (--pcie->enable > 0) 463 goto unlock; 464 465 reset_control_assert(pcie->rst); 466 clk_disable_unprepare(pcie->pll); 467 468 unlock: 469 mutex_unlock(&padctl->lock); 470 } 471 472 /* must be called under padctl->lock */ 473 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb) 474 { 475 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); 476 unsigned long timeout; 477 u32 value; 478 int err; 479 480 if (sata->enable > 0) { 481 sata->enable++; 482 return 0; 483 } 484 485 err = clk_prepare_enable(sata->pll); 486 if (err < 0) 487 return err; 488 489 err = reset_control_deassert(sata->rst); 490 if (err < 0) 491 goto disable; 492 493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << 495 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT); 496 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << 497 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT; 498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 499 500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); 501 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << 502 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT); 503 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << 504 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT; 505 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); 506 507 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 508 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 509 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 510 511 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 512 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 513 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 514 515 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 516 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 517 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 518 519 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 520 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK << 521 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) | 522 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK << 523 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT)); 524 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN; 525 526 if (usb) 527 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL << 528 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT); 529 else 530 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL << 531 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT); 532 533 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN; 534 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 535 536 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 537 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << 538 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) | 539 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK << 540 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT)); 541 542 if (usb) 543 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL << 544 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT; 545 else 546 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL << 547 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT; 548 549 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 550 551 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 552 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ; 553 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 554 555 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 556 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK << 557 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT); 558 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 559 560 usleep_range(10, 20); 561 562 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 563 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN; 564 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 565 566 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 567 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 568 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 569 570 timeout = jiffies + msecs_to_jiffies(100); 571 572 while (time_before(jiffies, timeout)) { 573 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 574 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE) 575 break; 576 577 usleep_range(10, 20); 578 } 579 580 if (time_after_eq(jiffies, timeout)) { 581 err = -ETIMEDOUT; 582 goto reset; 583 } 584 585 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 586 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN; 587 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 588 589 timeout = jiffies + msecs_to_jiffies(100); 590 591 while (time_before(jiffies, timeout)) { 592 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 593 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)) 594 break; 595 596 usleep_range(10, 20); 597 } 598 599 if (time_after_eq(jiffies, timeout)) { 600 err = -ETIMEDOUT; 601 goto reset; 602 } 603 604 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 605 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE; 606 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 607 608 timeout = jiffies + msecs_to_jiffies(100); 609 610 while (time_before(jiffies, timeout)) { 611 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 612 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS) 613 break; 614 615 usleep_range(10, 20); 616 } 617 618 if (time_after_eq(jiffies, timeout)) { 619 err = -ETIMEDOUT; 620 goto reset; 621 } 622 623 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 624 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN | 625 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 626 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 627 628 timeout = jiffies + msecs_to_jiffies(100); 629 630 while (time_before(jiffies, timeout)) { 631 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 632 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE) 633 break; 634 635 usleep_range(10, 20); 636 } 637 638 if (time_after_eq(jiffies, timeout)) { 639 err = -ETIMEDOUT; 640 goto reset; 641 } 642 643 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 644 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN; 645 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 646 647 timeout = jiffies + msecs_to_jiffies(100); 648 649 while (time_before(jiffies, timeout)) { 650 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 651 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)) 652 break; 653 654 usleep_range(10, 20); 655 } 656 657 if (time_after_eq(jiffies, timeout)) { 658 err = -ETIMEDOUT; 659 goto reset; 660 } 661 662 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 663 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN; 664 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 665 666 tegra210_sata_pll_hw_control_enable(); 667 668 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 669 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD; 670 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 671 672 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 673 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD; 674 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 675 676 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 677 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD; 678 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 679 680 usleep_range(10, 20); 681 682 tegra210_sata_pll_hw_sequence_start(); 683 684 sata->enable++; 685 686 return 0; 687 688 reset: 689 reset_control_assert(sata->rst); 690 disable: 691 clk_disable_unprepare(sata->pll); 692 return err; 693 } 694 695 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl) 696 { 697 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); 698 699 mutex_lock(&padctl->lock); 700 701 if (WARN_ON(sata->enable == 0)) 702 goto unlock; 703 704 if (--sata->enable > 0) 705 goto unlock; 706 707 reset_control_assert(sata->rst); 708 clk_disable_unprepare(sata->pll); 709 710 unlock: 711 mutex_unlock(&padctl->lock); 712 } 713 714 static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) 715 { 716 u32 value; 717 718 mutex_lock(&padctl->lock); 719 720 if (padctl->enable++ > 0) 721 goto out; 722 723 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 724 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; 725 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 726 727 usleep_range(100, 200); 728 729 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 730 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; 731 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 732 733 usleep_range(100, 200); 734 735 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 736 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; 737 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 738 739 out: 740 mutex_unlock(&padctl->lock); 741 return 0; 742 } 743 744 static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) 745 { 746 u32 value; 747 748 mutex_lock(&padctl->lock); 749 750 if (WARN_ON(padctl->enable == 0)) 751 goto out; 752 753 if (--padctl->enable > 0) 754 goto out; 755 756 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 757 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; 758 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 759 760 usleep_range(100, 200); 761 762 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 763 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; 764 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 765 766 usleep_range(100, 200); 767 768 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 769 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; 770 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 771 772 out: 773 mutex_unlock(&padctl->lock); 774 return 0; 775 } 776 777 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl, 778 unsigned int index, bool idle) 779 { 780 u32 value; 781 782 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 783 784 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | 785 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 | 786 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE); 787 788 if (idle) 789 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | 790 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 | 791 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE; 792 else 793 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | 794 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 | 795 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE); 796 797 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 798 799 return 0; 800 } 801 802 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl, 803 unsigned int index, bool enable) 804 { 805 struct tegra_xusb_port *port; 806 struct tegra_xusb_lane *lane; 807 u32 value, offset; 808 809 port = tegra_xusb_find_port(padctl, "usb3", index); 810 if (!port) 811 return -ENODEV; 812 813 lane = port->lane; 814 815 if (lane->pad == padctl->pcie) 816 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); 817 else 818 offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1; 819 820 value = padctl_readl(padctl, offset); 821 822 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK << 823 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) | 824 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN | 825 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD); 826 827 if (!enable) { 828 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL << 829 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) | 830 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN | 831 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD; 832 } 833 834 padctl_writel(padctl, value, offset); 835 836 return 0; 837 } 838 839 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \ 840 { \ 841 .name = _name, \ 842 .offset = _offset, \ 843 .shift = _shift, \ 844 .mask = _mask, \ 845 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \ 846 .funcs = tegra210_##_type##_functions, \ 847 } 848 849 static const char *tegra210_usb2_functions[] = { 850 "snps", 851 "xusb", 852 "uart" 853 }; 854 855 static const struct tegra_xusb_lane_soc tegra210_usb2_lanes[] = { 856 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2), 857 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2), 858 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2), 859 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2), 860 }; 861 862 static struct tegra_xusb_lane * 863 tegra210_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 864 unsigned int index) 865 { 866 struct tegra_xusb_usb2_lane *usb2; 867 int err; 868 869 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 870 if (!usb2) 871 return ERR_PTR(-ENOMEM); 872 873 INIT_LIST_HEAD(&usb2->base.list); 874 usb2->base.soc = &pad->soc->lanes[index]; 875 usb2->base.index = index; 876 usb2->base.pad = pad; 877 usb2->base.np = np; 878 879 err = tegra_xusb_lane_parse_dt(&usb2->base, np); 880 if (err < 0) { 881 kfree(usb2); 882 return ERR_PTR(err); 883 } 884 885 return &usb2->base; 886 } 887 888 static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane) 889 { 890 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 891 892 kfree(usb2); 893 } 894 895 static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops = { 896 .probe = tegra210_usb2_lane_probe, 897 .remove = tegra210_usb2_lane_remove, 898 }; 899 900 static int tegra210_usb2_phy_init(struct phy *phy) 901 { 902 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 903 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 904 u32 value; 905 906 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); 907 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK << 908 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT); 909 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB << 910 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT; 911 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); 912 913 return tegra210_xusb_padctl_enable(padctl); 914 } 915 916 static int tegra210_usb2_phy_exit(struct phy *phy) 917 { 918 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 919 920 return tegra210_xusb_padctl_disable(lane->pad->padctl); 921 } 922 923 static int tegra210_usb2_phy_power_on(struct phy *phy) 924 { 925 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 926 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); 927 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); 928 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 929 struct tegra210_xusb_padctl *priv; 930 struct tegra_xusb_usb2_port *port; 931 unsigned int index = lane->index; 932 u32 value; 933 int err; 934 935 port = tegra_xusb_find_usb2_port(padctl, index); 936 if (!port) { 937 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); 938 return -ENODEV; 939 } 940 941 priv = to_tegra210_xusb_padctl(padctl); 942 943 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 944 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK << 945 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) | 946 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK << 947 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT)); 948 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL << 949 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT); 950 951 if (tegra_sku_info.revision < TEGRA_REVISION_A02) 952 value |= 953 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL << 954 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT); 955 956 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 957 958 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); 959 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index); 960 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index); 961 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); 962 963 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 964 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK << 965 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) | 966 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 967 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 968 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 969 value |= (priv->fuse.hs_curr_level[index] + 970 usb2->hs_curr_level_offset) << 971 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT; 972 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); 973 974 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 975 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK << 976 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) | 977 (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK << 978 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT) | 979 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 980 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD | 981 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD); 982 value |= (priv->fuse.hs_term_range_adj << 983 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) | 984 (priv->fuse.rpd_ctrl << 985 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT); 986 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); 987 988 value = padctl_readl(padctl, 989 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); 990 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK << 991 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT); 992 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; 993 padctl_writel(padctl, value, 994 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); 995 996 err = regulator_enable(port->supply); 997 if (err) 998 return err; 999 1000 mutex_lock(&padctl->lock); 1001 1002 if (pad->enable > 0) { 1003 pad->enable++; 1004 mutex_unlock(&padctl->lock); 1005 return 0; 1006 } 1007 1008 err = clk_prepare_enable(pad->clk); 1009 if (err) 1010 goto disable_regulator; 1011 1012 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1013 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK << 1014 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | 1015 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK << 1016 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT)); 1017 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL << 1018 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) | 1019 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL << 1020 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT); 1021 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1022 1023 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1024 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; 1025 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1026 1027 udelay(1); 1028 1029 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1030 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK; 1031 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1032 1033 udelay(50); 1034 1035 clk_disable_unprepare(pad->clk); 1036 1037 pad->enable++; 1038 mutex_unlock(&padctl->lock); 1039 1040 return 0; 1041 1042 disable_regulator: 1043 regulator_disable(port->supply); 1044 mutex_unlock(&padctl->lock); 1045 return err; 1046 } 1047 1048 static int tegra210_usb2_phy_power_off(struct phy *phy) 1049 { 1050 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1051 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); 1052 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1053 struct tegra_xusb_usb2_port *port; 1054 u32 value; 1055 1056 port = tegra_xusb_find_usb2_port(padctl, lane->index); 1057 if (!port) { 1058 dev_err(&phy->dev, "no port found for USB2 lane %u\n", 1059 lane->index); 1060 return -ENODEV; 1061 } 1062 1063 mutex_lock(&padctl->lock); 1064 1065 if (WARN_ON(pad->enable == 0)) 1066 goto out; 1067 1068 if (--pad->enable > 0) 1069 goto out; 1070 1071 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1072 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD; 1073 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1074 1075 out: 1076 regulator_disable(port->supply); 1077 mutex_unlock(&padctl->lock); 1078 return 0; 1079 } 1080 1081 static const struct phy_ops tegra210_usb2_phy_ops = { 1082 .init = tegra210_usb2_phy_init, 1083 .exit = tegra210_usb2_phy_exit, 1084 .power_on = tegra210_usb2_phy_power_on, 1085 .power_off = tegra210_usb2_phy_power_off, 1086 .owner = THIS_MODULE, 1087 }; 1088 1089 static struct tegra_xusb_pad * 1090 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl, 1091 const struct tegra_xusb_pad_soc *soc, 1092 struct device_node *np) 1093 { 1094 struct tegra_xusb_usb2_pad *usb2; 1095 struct tegra_xusb_pad *pad; 1096 int err; 1097 1098 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); 1099 if (!usb2) 1100 return ERR_PTR(-ENOMEM); 1101 1102 pad = &usb2->base; 1103 pad->ops = &tegra210_usb2_lane_ops; 1104 pad->soc = soc; 1105 1106 err = tegra_xusb_pad_init(pad, padctl, np); 1107 if (err < 0) { 1108 kfree(usb2); 1109 goto out; 1110 } 1111 1112 usb2->clk = devm_clk_get(&pad->dev, "trk"); 1113 if (IS_ERR(usb2->clk)) { 1114 err = PTR_ERR(usb2->clk); 1115 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); 1116 goto unregister; 1117 } 1118 1119 err = tegra_xusb_pad_register(pad, &tegra210_usb2_phy_ops); 1120 if (err < 0) 1121 goto unregister; 1122 1123 dev_set_drvdata(&pad->dev, pad); 1124 1125 return pad; 1126 1127 unregister: 1128 device_unregister(&pad->dev); 1129 out: 1130 return ERR_PTR(err); 1131 } 1132 1133 static void tegra210_usb2_pad_remove(struct tegra_xusb_pad *pad) 1134 { 1135 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); 1136 1137 kfree(usb2); 1138 } 1139 1140 static const struct tegra_xusb_pad_ops tegra210_usb2_ops = { 1141 .probe = tegra210_usb2_pad_probe, 1142 .remove = tegra210_usb2_pad_remove, 1143 }; 1144 1145 static const struct tegra_xusb_pad_soc tegra210_usb2_pad = { 1146 .name = "usb2", 1147 .num_lanes = ARRAY_SIZE(tegra210_usb2_lanes), 1148 .lanes = tegra210_usb2_lanes, 1149 .ops = &tegra210_usb2_ops, 1150 }; 1151 1152 static const char *tegra210_hsic_functions[] = { 1153 "snps", 1154 "xusb", 1155 }; 1156 1157 static const struct tegra_xusb_lane_soc tegra210_hsic_lanes[] = { 1158 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic), 1159 }; 1160 1161 static struct tegra_xusb_lane * 1162 tegra210_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 1163 unsigned int index) 1164 { 1165 struct tegra_xusb_hsic_lane *hsic; 1166 int err; 1167 1168 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL); 1169 if (!hsic) 1170 return ERR_PTR(-ENOMEM); 1171 1172 INIT_LIST_HEAD(&hsic->base.list); 1173 hsic->base.soc = &pad->soc->lanes[index]; 1174 hsic->base.index = index; 1175 hsic->base.pad = pad; 1176 hsic->base.np = np; 1177 1178 err = tegra_xusb_lane_parse_dt(&hsic->base, np); 1179 if (err < 0) { 1180 kfree(hsic); 1181 return ERR_PTR(err); 1182 } 1183 1184 return &hsic->base; 1185 } 1186 1187 static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane) 1188 { 1189 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); 1190 1191 kfree(hsic); 1192 } 1193 1194 static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops = { 1195 .probe = tegra210_hsic_lane_probe, 1196 .remove = tegra210_hsic_lane_remove, 1197 }; 1198 1199 static int tegra210_hsic_phy_init(struct phy *phy) 1200 { 1201 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1202 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1203 u32 value; 1204 1205 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); 1206 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK << 1207 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT); 1208 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB << 1209 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT; 1210 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); 1211 1212 return tegra210_xusb_padctl_enable(padctl); 1213 } 1214 1215 static int tegra210_hsic_phy_exit(struct phy *phy) 1216 { 1217 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1218 1219 return tegra210_xusb_padctl_disable(lane->pad->padctl); 1220 } 1221 1222 static int tegra210_hsic_phy_power_on(struct phy *phy) 1223 { 1224 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1225 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); 1226 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); 1227 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1228 struct tegra210_xusb_padctl *priv; 1229 unsigned int index = lane->index; 1230 u32 value; 1231 int err; 1232 1233 priv = to_tegra210_xusb_padctl(padctl); 1234 1235 err = regulator_enable(pad->supply); 1236 if (err) 1237 return err; 1238 1239 padctl_writel(padctl, hsic->strobe_trim, 1240 XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL); 1241 1242 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); 1243 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK << 1244 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT); 1245 value |= (hsic->tx_rtune_p << 1246 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT); 1247 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); 1248 1249 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); 1250 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK << 1251 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) | 1252 (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK << 1253 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT)); 1254 value |= (hsic->rx_strobe_trim << 1255 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) | 1256 (hsic->rx_data_trim << 1257 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT); 1258 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); 1259 1260 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 1261 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 | 1262 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 | 1263 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE | 1264 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | 1265 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 | 1266 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE | 1267 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 | 1268 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 | 1269 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE | 1270 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 | 1271 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 | 1272 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE); 1273 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 | 1274 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 | 1275 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE; 1276 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 1277 1278 err = clk_prepare_enable(pad->clk); 1279 if (err) 1280 goto disable; 1281 1282 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1283 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK << 1284 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) | 1285 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK << 1286 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT)); 1287 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL << 1288 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) | 1289 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL << 1290 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT); 1291 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1292 1293 udelay(1); 1294 1295 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1296 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK; 1297 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1298 1299 udelay(50); 1300 1301 clk_disable_unprepare(pad->clk); 1302 1303 return 0; 1304 1305 disable: 1306 regulator_disable(pad->supply); 1307 return err; 1308 } 1309 1310 static int tegra210_hsic_phy_power_off(struct phy *phy) 1311 { 1312 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1313 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); 1314 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1315 unsigned int index = lane->index; 1316 u32 value; 1317 1318 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); 1319 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 | 1320 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 | 1321 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE | 1322 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 | 1323 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 | 1324 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE | 1325 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 | 1326 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 | 1327 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE; 1328 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); 1329 1330 regulator_disable(pad->supply); 1331 1332 return 0; 1333 } 1334 1335 static const struct phy_ops tegra210_hsic_phy_ops = { 1336 .init = tegra210_hsic_phy_init, 1337 .exit = tegra210_hsic_phy_exit, 1338 .power_on = tegra210_hsic_phy_power_on, 1339 .power_off = tegra210_hsic_phy_power_off, 1340 .owner = THIS_MODULE, 1341 }; 1342 1343 static struct tegra_xusb_pad * 1344 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl, 1345 const struct tegra_xusb_pad_soc *soc, 1346 struct device_node *np) 1347 { 1348 struct tegra_xusb_hsic_pad *hsic; 1349 struct tegra_xusb_pad *pad; 1350 int err; 1351 1352 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL); 1353 if (!hsic) 1354 return ERR_PTR(-ENOMEM); 1355 1356 pad = &hsic->base; 1357 pad->ops = &tegra210_hsic_lane_ops; 1358 pad->soc = soc; 1359 1360 err = tegra_xusb_pad_init(pad, padctl, np); 1361 if (err < 0) { 1362 kfree(hsic); 1363 goto out; 1364 } 1365 1366 hsic->clk = devm_clk_get(&pad->dev, "trk"); 1367 if (IS_ERR(hsic->clk)) { 1368 err = PTR_ERR(hsic->clk); 1369 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); 1370 goto unregister; 1371 } 1372 1373 err = tegra_xusb_pad_register(pad, &tegra210_hsic_phy_ops); 1374 if (err < 0) 1375 goto unregister; 1376 1377 dev_set_drvdata(&pad->dev, pad); 1378 1379 return pad; 1380 1381 unregister: 1382 device_unregister(&pad->dev); 1383 out: 1384 return ERR_PTR(err); 1385 } 1386 1387 static void tegra210_hsic_pad_remove(struct tegra_xusb_pad *pad) 1388 { 1389 struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad); 1390 1391 kfree(hsic); 1392 } 1393 1394 static const struct tegra_xusb_pad_ops tegra210_hsic_ops = { 1395 .probe = tegra210_hsic_pad_probe, 1396 .remove = tegra210_hsic_pad_remove, 1397 }; 1398 1399 static const struct tegra_xusb_pad_soc tegra210_hsic_pad = { 1400 .name = "hsic", 1401 .num_lanes = ARRAY_SIZE(tegra210_hsic_lanes), 1402 .lanes = tegra210_hsic_lanes, 1403 .ops = &tegra210_hsic_ops, 1404 }; 1405 1406 static const char *tegra210_pcie_functions[] = { 1407 "pcie-x1", 1408 "usb3-ss", 1409 "sata", 1410 "pcie-x4", 1411 }; 1412 1413 static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = { 1414 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie), 1415 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie), 1416 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie), 1417 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie), 1418 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie), 1419 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie), 1420 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie), 1421 }; 1422 1423 static struct tegra_xusb_lane * 1424 tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 1425 unsigned int index) 1426 { 1427 struct tegra_xusb_pcie_lane *pcie; 1428 int err; 1429 1430 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); 1431 if (!pcie) 1432 return ERR_PTR(-ENOMEM); 1433 1434 INIT_LIST_HEAD(&pcie->base.list); 1435 pcie->base.soc = &pad->soc->lanes[index]; 1436 pcie->base.index = index; 1437 pcie->base.pad = pad; 1438 pcie->base.np = np; 1439 1440 err = tegra_xusb_lane_parse_dt(&pcie->base, np); 1441 if (err < 0) { 1442 kfree(pcie); 1443 return ERR_PTR(err); 1444 } 1445 1446 return &pcie->base; 1447 } 1448 1449 static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane) 1450 { 1451 struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane); 1452 1453 kfree(pcie); 1454 } 1455 1456 static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = { 1457 .probe = tegra210_pcie_lane_probe, 1458 .remove = tegra210_pcie_lane_remove, 1459 }; 1460 1461 static int tegra210_pcie_phy_init(struct phy *phy) 1462 { 1463 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1464 1465 return tegra210_xusb_padctl_enable(lane->pad->padctl); 1466 } 1467 1468 static int tegra210_pcie_phy_exit(struct phy *phy) 1469 { 1470 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1471 1472 return tegra210_xusb_padctl_disable(lane->pad->padctl); 1473 } 1474 1475 static int tegra210_pcie_phy_power_on(struct phy *phy) 1476 { 1477 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1478 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1479 u32 value; 1480 int err; 1481 1482 mutex_lock(&padctl->lock); 1483 1484 err = tegra210_pex_uphy_enable(padctl); 1485 if (err < 0) 1486 goto unlock; 1487 1488 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1489 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); 1490 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1491 1492 unlock: 1493 mutex_unlock(&padctl->lock); 1494 return err; 1495 } 1496 1497 static int tegra210_pcie_phy_power_off(struct phy *phy) 1498 { 1499 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1500 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1501 u32 value; 1502 1503 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1504 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); 1505 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1506 1507 tegra210_pex_uphy_disable(padctl); 1508 1509 return 0; 1510 } 1511 1512 static const struct phy_ops tegra210_pcie_phy_ops = { 1513 .init = tegra210_pcie_phy_init, 1514 .exit = tegra210_pcie_phy_exit, 1515 .power_on = tegra210_pcie_phy_power_on, 1516 .power_off = tegra210_pcie_phy_power_off, 1517 .owner = THIS_MODULE, 1518 }; 1519 1520 static struct tegra_xusb_pad * 1521 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl, 1522 const struct tegra_xusb_pad_soc *soc, 1523 struct device_node *np) 1524 { 1525 struct tegra_xusb_pcie_pad *pcie; 1526 struct tegra_xusb_pad *pad; 1527 int err; 1528 1529 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); 1530 if (!pcie) 1531 return ERR_PTR(-ENOMEM); 1532 1533 pad = &pcie->base; 1534 pad->ops = &tegra210_pcie_lane_ops; 1535 pad->soc = soc; 1536 1537 err = tegra_xusb_pad_init(pad, padctl, np); 1538 if (err < 0) { 1539 kfree(pcie); 1540 goto out; 1541 } 1542 1543 pcie->pll = devm_clk_get(&pad->dev, "pll"); 1544 if (IS_ERR(pcie->pll)) { 1545 err = PTR_ERR(pcie->pll); 1546 dev_err(&pad->dev, "failed to get PLL: %d\n", err); 1547 goto unregister; 1548 } 1549 1550 pcie->rst = devm_reset_control_get(&pad->dev, "phy"); 1551 if (IS_ERR(pcie->rst)) { 1552 err = PTR_ERR(pcie->rst); 1553 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err); 1554 goto unregister; 1555 } 1556 1557 err = tegra_xusb_pad_register(pad, &tegra210_pcie_phy_ops); 1558 if (err < 0) 1559 goto unregister; 1560 1561 dev_set_drvdata(&pad->dev, pad); 1562 1563 return pad; 1564 1565 unregister: 1566 device_unregister(&pad->dev); 1567 out: 1568 return ERR_PTR(err); 1569 } 1570 1571 static void tegra210_pcie_pad_remove(struct tegra_xusb_pad *pad) 1572 { 1573 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad); 1574 1575 kfree(pcie); 1576 } 1577 1578 static const struct tegra_xusb_pad_ops tegra210_pcie_ops = { 1579 .probe = tegra210_pcie_pad_probe, 1580 .remove = tegra210_pcie_pad_remove, 1581 }; 1582 1583 static const struct tegra_xusb_pad_soc tegra210_pcie_pad = { 1584 .name = "pcie", 1585 .num_lanes = ARRAY_SIZE(tegra210_pcie_lanes), 1586 .lanes = tegra210_pcie_lanes, 1587 .ops = &tegra210_pcie_ops, 1588 }; 1589 1590 static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = { 1591 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie), 1592 }; 1593 1594 static struct tegra_xusb_lane * 1595 tegra210_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, 1596 unsigned int index) 1597 { 1598 struct tegra_xusb_sata_lane *sata; 1599 int err; 1600 1601 sata = kzalloc(sizeof(*sata), GFP_KERNEL); 1602 if (!sata) 1603 return ERR_PTR(-ENOMEM); 1604 1605 INIT_LIST_HEAD(&sata->base.list); 1606 sata->base.soc = &pad->soc->lanes[index]; 1607 sata->base.index = index; 1608 sata->base.pad = pad; 1609 sata->base.np = np; 1610 1611 err = tegra_xusb_lane_parse_dt(&sata->base, np); 1612 if (err < 0) { 1613 kfree(sata); 1614 return ERR_PTR(err); 1615 } 1616 1617 return &sata->base; 1618 } 1619 1620 static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane) 1621 { 1622 struct tegra_xusb_sata_lane *sata = to_sata_lane(lane); 1623 1624 kfree(sata); 1625 } 1626 1627 static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = { 1628 .probe = tegra210_sata_lane_probe, 1629 .remove = tegra210_sata_lane_remove, 1630 }; 1631 1632 static int tegra210_sata_phy_init(struct phy *phy) 1633 { 1634 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1635 1636 return tegra210_xusb_padctl_enable(lane->pad->padctl); 1637 } 1638 1639 static int tegra210_sata_phy_exit(struct phy *phy) 1640 { 1641 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1642 1643 return tegra210_xusb_padctl_disable(lane->pad->padctl); 1644 } 1645 1646 static int tegra210_sata_phy_power_on(struct phy *phy) 1647 { 1648 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1649 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1650 u32 value; 1651 int err; 1652 1653 mutex_lock(&padctl->lock); 1654 1655 err = tegra210_sata_uphy_enable(padctl, false); 1656 if (err < 0) 1657 goto unlock; 1658 1659 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1660 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); 1661 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1662 1663 unlock: 1664 mutex_unlock(&padctl->lock); 1665 return err; 1666 } 1667 1668 static int tegra210_sata_phy_power_off(struct phy *phy) 1669 { 1670 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); 1671 struct tegra_xusb_padctl *padctl = lane->pad->padctl; 1672 u32 value; 1673 1674 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); 1675 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); 1676 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); 1677 1678 tegra210_sata_uphy_disable(lane->pad->padctl); 1679 1680 return 0; 1681 } 1682 1683 static const struct phy_ops tegra210_sata_phy_ops = { 1684 .init = tegra210_sata_phy_init, 1685 .exit = tegra210_sata_phy_exit, 1686 .power_on = tegra210_sata_phy_power_on, 1687 .power_off = tegra210_sata_phy_power_off, 1688 .owner = THIS_MODULE, 1689 }; 1690 1691 static struct tegra_xusb_pad * 1692 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl, 1693 const struct tegra_xusb_pad_soc *soc, 1694 struct device_node *np) 1695 { 1696 struct tegra_xusb_sata_pad *sata; 1697 struct tegra_xusb_pad *pad; 1698 int err; 1699 1700 sata = kzalloc(sizeof(*sata), GFP_KERNEL); 1701 if (!sata) 1702 return ERR_PTR(-ENOMEM); 1703 1704 pad = &sata->base; 1705 pad->ops = &tegra210_sata_lane_ops; 1706 pad->soc = soc; 1707 1708 err = tegra_xusb_pad_init(pad, padctl, np); 1709 if (err < 0) { 1710 kfree(sata); 1711 goto out; 1712 } 1713 1714 sata->rst = devm_reset_control_get(&pad->dev, "phy"); 1715 if (IS_ERR(sata->rst)) { 1716 err = PTR_ERR(sata->rst); 1717 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err); 1718 goto unregister; 1719 } 1720 1721 err = tegra_xusb_pad_register(pad, &tegra210_sata_phy_ops); 1722 if (err < 0) 1723 goto unregister; 1724 1725 dev_set_drvdata(&pad->dev, pad); 1726 1727 return pad; 1728 1729 unregister: 1730 device_unregister(&pad->dev); 1731 out: 1732 return ERR_PTR(err); 1733 } 1734 1735 static void tegra210_sata_pad_remove(struct tegra_xusb_pad *pad) 1736 { 1737 struct tegra_xusb_sata_pad *sata = to_sata_pad(pad); 1738 1739 kfree(sata); 1740 } 1741 1742 static const struct tegra_xusb_pad_ops tegra210_sata_ops = { 1743 .probe = tegra210_sata_pad_probe, 1744 .remove = tegra210_sata_pad_remove, 1745 }; 1746 1747 static const struct tegra_xusb_pad_soc tegra210_sata_pad = { 1748 .name = "sata", 1749 .num_lanes = ARRAY_SIZE(tegra210_sata_lanes), 1750 .lanes = tegra210_sata_lanes, 1751 .ops = &tegra210_sata_ops, 1752 }; 1753 1754 static const struct tegra_xusb_pad_soc * const tegra210_pads[] = { 1755 &tegra210_usb2_pad, 1756 &tegra210_hsic_pad, 1757 &tegra210_pcie_pad, 1758 &tegra210_sata_pad, 1759 }; 1760 1761 static int tegra210_usb2_port_enable(struct tegra_xusb_port *port) 1762 { 1763 return 0; 1764 } 1765 1766 static void tegra210_usb2_port_disable(struct tegra_xusb_port *port) 1767 { 1768 } 1769 1770 static struct tegra_xusb_lane * 1771 tegra210_usb2_port_map(struct tegra_xusb_port *port) 1772 { 1773 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); 1774 } 1775 1776 static const struct tegra_xusb_port_ops tegra210_usb2_port_ops = { 1777 .enable = tegra210_usb2_port_enable, 1778 .disable = tegra210_usb2_port_disable, 1779 .map = tegra210_usb2_port_map, 1780 }; 1781 1782 static int tegra210_hsic_port_enable(struct tegra_xusb_port *port) 1783 { 1784 return 0; 1785 } 1786 1787 static void tegra210_hsic_port_disable(struct tegra_xusb_port *port) 1788 { 1789 } 1790 1791 static struct tegra_xusb_lane * 1792 tegra210_hsic_port_map(struct tegra_xusb_port *port) 1793 { 1794 return tegra_xusb_find_lane(port->padctl, "hsic", port->index); 1795 } 1796 1797 static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = { 1798 .enable = tegra210_hsic_port_enable, 1799 .disable = tegra210_hsic_port_disable, 1800 .map = tegra210_hsic_port_map, 1801 }; 1802 1803 static int tegra210_usb3_port_enable(struct tegra_xusb_port *port) 1804 { 1805 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port); 1806 struct tegra_xusb_padctl *padctl = port->padctl; 1807 struct tegra_xusb_lane *lane = usb3->base.lane; 1808 unsigned int index = port->index; 1809 u32 value; 1810 int err; 1811 1812 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); 1813 1814 if (!usb3->internal) 1815 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); 1816 else 1817 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index); 1818 1819 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); 1820 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); 1821 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); 1822 1823 /* 1824 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks 1825 * and conditionalize based on mux function? This seems to work, but 1826 * might not be the exact proper sequence. 1827 */ 1828 err = regulator_enable(usb3->supply); 1829 if (err < 0) 1830 return err; 1831 1832 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); 1833 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK << 1834 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT); 1835 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL << 1836 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT; 1837 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); 1838 1839 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); 1840 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK << 1841 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT); 1842 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL << 1843 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT; 1844 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); 1845 1846 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL, 1847 XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index)); 1848 1849 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); 1850 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK << 1851 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT); 1852 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL << 1853 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT; 1854 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); 1855 1856 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL, 1857 XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index)); 1858 1859 if (lane->pad == padctl->sata) 1860 err = tegra210_sata_uphy_enable(padctl, true); 1861 else 1862 err = tegra210_pex_uphy_enable(padctl); 1863 1864 if (err) { 1865 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n", 1866 __func__, err); 1867 return err; 1868 } 1869 1870 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1871 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); 1872 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1873 1874 usleep_range(100, 200); 1875 1876 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1877 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); 1878 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1879 1880 usleep_range(100, 200); 1881 1882 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1883 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); 1884 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1885 1886 return 0; 1887 } 1888 1889 static void tegra210_usb3_port_disable(struct tegra_xusb_port *port) 1890 { 1891 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port); 1892 struct tegra_xusb_padctl *padctl = port->padctl; 1893 struct tegra_xusb_lane *lane = port->lane; 1894 unsigned int index = port->index; 1895 u32 value; 1896 1897 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1898 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index); 1899 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1900 1901 usleep_range(100, 200); 1902 1903 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1904 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index); 1905 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1906 1907 usleep_range(250, 350); 1908 1909 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); 1910 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index); 1911 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); 1912 1913 if (lane->pad == padctl->sata) 1914 tegra210_sata_uphy_disable(padctl); 1915 else 1916 tegra210_pex_uphy_disable(padctl); 1917 1918 regulator_disable(usb3->supply); 1919 1920 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); 1921 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index); 1922 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); 1923 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); 1924 } 1925 1926 static const struct tegra_xusb_lane_map tegra210_usb3_map[] = { 1927 { 0, "pcie", 6 }, 1928 { 1, "pcie", 5 }, 1929 { 2, "pcie", 0 }, 1930 { 2, "pcie", 3 }, 1931 { 3, "pcie", 4 }, 1932 { 3, "pcie", 4 }, 1933 { 0, NULL, 0 } 1934 }; 1935 1936 static struct tegra_xusb_lane * 1937 tegra210_usb3_port_map(struct tegra_xusb_port *port) 1938 { 1939 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss"); 1940 } 1941 1942 static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = { 1943 .enable = tegra210_usb3_port_enable, 1944 .disable = tegra210_usb3_port_disable, 1945 .map = tegra210_usb3_port_map, 1946 }; 1947 1948 static int 1949 tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse) 1950 { 1951 unsigned int i; 1952 u32 value; 1953 int err; 1954 1955 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); 1956 if (err < 0) 1957 return err; 1958 1959 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { 1960 fuse->hs_curr_level[i] = 1961 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) & 1962 FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK; 1963 } 1964 1965 fuse->hs_term_range_adj = 1966 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) & 1967 FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK; 1968 1969 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); 1970 if (err < 0) 1971 return err; 1972 1973 fuse->rpd_ctrl = 1974 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) & 1975 FUSE_USB_CALIB_EXT_RPD_CTRL_MASK; 1976 1977 return 0; 1978 } 1979 1980 static struct tegra_xusb_padctl * 1981 tegra210_xusb_padctl_probe(struct device *dev, 1982 const struct tegra_xusb_padctl_soc *soc) 1983 { 1984 struct tegra210_xusb_padctl *padctl; 1985 int err; 1986 1987 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL); 1988 if (!padctl) 1989 return ERR_PTR(-ENOMEM); 1990 1991 padctl->base.dev = dev; 1992 padctl->base.soc = soc; 1993 1994 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); 1995 if (err < 0) 1996 return ERR_PTR(err); 1997 1998 return &padctl->base; 1999 } 2000 2001 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) 2002 { 2003 } 2004 2005 static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = { 2006 .probe = tegra210_xusb_padctl_probe, 2007 .remove = tegra210_xusb_padctl_remove, 2008 .usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect, 2009 .hsic_set_idle = tegra210_hsic_set_idle, 2010 }; 2011 2012 static const char * const tegra210_xusb_padctl_supply_names[] = { 2013 "avdd-pll-utmip", 2014 "avdd-pll-uerefe", 2015 "dvdd-pex-pll", 2016 "hvdd-pex-pll-e", 2017 }; 2018 2019 const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = { 2020 .num_pads = ARRAY_SIZE(tegra210_pads), 2021 .pads = tegra210_pads, 2022 .ports = { 2023 .usb2 = { 2024 .ops = &tegra210_usb2_port_ops, 2025 .count = 4, 2026 }, 2027 .hsic = { 2028 .ops = &tegra210_hsic_port_ops, 2029 .count = 1, 2030 }, 2031 .usb3 = { 2032 .ops = &tegra210_usb3_port_ops, 2033 .count = 4, 2034 }, 2035 }, 2036 .ops = &tegra210_xusb_padctl_ops, 2037 .supply_names = tegra210_xusb_padctl_supply_names, 2038 .num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names), 2039 }; 2040 EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc); 2041 2042 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 2043 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver"); 2044 MODULE_LICENSE("GPL v2"); 2045