1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/delay.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/slab.h>
15 
16 #include <soc/tegra/fuse.h>
17 
18 #include "xusb.h"
19 
20 /* FUSE USB_CALIB registers */
21 #define HS_CURR_LEVEL_PADX_SHIFT(x)	((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK		0x3f
23 #define HS_TERM_RANGE_ADJ_SHIFT		7
24 #define HS_TERM_RANGE_ADJ_MASK		0xf
25 #define HS_SQUELCH_SHIFT		29
26 #define HS_SQUELCH_MASK			0x7
27 
28 #define RPD_CTRL_SHIFT			0
29 #define RPD_CTRL_MASK			0x1f
30 
31 /* XUSB PADCTL registers */
32 #define XUSB_PADCTL_USB2_PAD_MUX	0x4
33 #define  USB2_PORT_SHIFT(x)		((x) * 2)
34 #define  USB2_PORT_MASK			0x3
35 #define   PORT_XUSB			1
36 #define  HSIC_PORT_SHIFT(x)		((x) + 20)
37 #define  HSIC_PORT_MASK			0x1
38 #define   PORT_HSIC			0
39 
40 #define XUSB_PADCTL_USB2_PORT_CAP	0x8
41 #define XUSB_PADCTL_SS_PORT_CAP		0xc
42 #define  PORTX_CAP_SHIFT(x)		((x) * 4)
43 #define  PORT_CAP_MASK			0x3
44 #define   PORT_CAP_DISABLED		0x0
45 #define   PORT_CAP_HOST			0x1
46 #define   PORT_CAP_DEVICE		0x2
47 #define   PORT_CAP_OTG			0x3
48 
49 #define XUSB_PADCTL_ELPG_PROGRAM		0x20
50 #define  USB2_PORT_WAKE_INTERRUPT_ENABLE(x)		BIT(x)
51 #define  USB2_PORT_WAKEUP_EVENT(x)			BIT((x) +  7)
52 #define  SS_PORT_WAKE_INTERRUPT_ENABLE(x)		BIT((x) + 14)
53 #define  SS_PORT_WAKEUP_EVENT(x)			BIT((x) + 21)
54 #define  USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x)	BIT((x) + 28)
55 #define  USB2_HSIC_PORT_WAKEUP_EVENT(x)			BIT((x) + 30)
56 #define  ALL_WAKE_EVENTS						\
57 	(USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |	\
58 	USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) |		\
59 	SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) |		\
60 	USB2_HSIC_PORT_WAKEUP_EVENT(0))
61 
62 #define XUSB_PADCTL_ELPG_PROGRAM_1		0x24
63 #define  SSPX_ELPG_CLAMP_EN(x)			BIT(0 + (x) * 3)
64 #define  SSPX_ELPG_CLAMP_EN_EARLY(x)		BIT(1 + (x) * 3)
65 #define  SSPX_ELPG_VCORE_DOWN(x)		BIT(2 + (x) * 3)
66 #define XUSB_PADCTL_SS_PORT_CFG			0x2c
67 #define   PORTX_SPEED_SUPPORT_SHIFT(x)		((x) * 4)
68 #define   PORTX_SPEED_SUPPORT_MASK		(0x3)
69 #define     PORT_SPEED_SUPPORT_GEN1		(0x0)
70 
71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x)	(0x88 + (x) * 0x40)
72 #define  HS_CURR_LEVEL(x)			((x) & 0x3f)
73 #define  TERM_SEL				BIT(25)
74 #define  USB2_OTG_PD				BIT(26)
75 #define  USB2_OTG_PD2				BIT(27)
76 #define  USB2_OTG_PD2_OVRD_EN			BIT(28)
77 #define  USB2_OTG_PD_ZI				BIT(29)
78 
79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x)	(0x8c + (x) * 0x40)
80 #define  USB2_OTG_PD_DR				BIT(2)
81 #define  TERM_RANGE_ADJ(x)			(((x) & 0xf) << 3)
82 #define  RPD_CTRL(x)				(((x) & 0x1f) << 26)
83 
84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x284
85 #define  BIAS_PAD_PD				BIT(11)
86 #define  HS_SQUELCH_LEVEL(x)			(((x) & 0x7) << 0)
87 
88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1		0x288
89 #define  USB2_TRK_START_TIMER(x)		(((x) & 0x7f) << 12)
90 #define  USB2_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 19)
91 #define  USB2_PD_TRK				BIT(26)
92 
93 #define XUSB_PADCTL_HSIC_PADX_CTL0(x)		(0x300 + (x) * 0x20)
94 #define  HSIC_PD_TX_DATA0			BIT(1)
95 #define  HSIC_PD_TX_STROBE			BIT(3)
96 #define  HSIC_PD_RX_DATA0			BIT(4)
97 #define  HSIC_PD_RX_STROBE			BIT(6)
98 #define  HSIC_PD_ZI_DATA0			BIT(7)
99 #define  HSIC_PD_ZI_STROBE			BIT(9)
100 #define  HSIC_RPD_DATA0				BIT(13)
101 #define  HSIC_RPD_STROBE			BIT(15)
102 #define  HSIC_RPU_DATA0				BIT(16)
103 #define  HSIC_RPU_STROBE			BIT(18)
104 
105 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0		0x340
106 #define  HSIC_TRK_START_TIMER(x)		(((x) & 0x7f) << 5)
107 #define  HSIC_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 12)
108 #define  HSIC_PD_TRK				BIT(19)
109 
110 #define USB2_VBUS_ID				0x360
111 #define  VBUS_OVERRIDE				BIT(14)
112 #define  ID_OVERRIDE(x)				(((x) & 0xf) << 18)
113 #define  ID_OVERRIDE_FLOATING			ID_OVERRIDE(8)
114 #define  ID_OVERRIDE_GROUNDED			ID_OVERRIDE(0)
115 
116 /* XUSB AO registers */
117 #define XUSB_AO_USB_DEBOUNCE_DEL		(0x4)
118 #define   UHSIC_LINE_DEB_CNT(x)			(((x) & 0xf) << 4)
119 #define   UTMIP_LINE_DEB_CNT(x)			((x) & 0xf)
120 
121 #define XUSB_AO_UTMIP_TRIGGERS(x)		(0x40 + (x) * 4)
122 #define   CLR_WALK_PTR				BIT(0)
123 #define   CAP_CFG				BIT(1)
124 #define   CLR_WAKE_ALARM			BIT(3)
125 
126 #define XUSB_AO_UHSIC_TRIGGERS(x)		(0x60 + (x) * 4)
127 #define   HSIC_CLR_WALK_PTR			BIT(0)
128 #define   HSIC_CLR_WAKE_ALARM			BIT(3)
129 #define   HSIC_CAP_CFG				BIT(4)
130 
131 #define XUSB_AO_UTMIP_SAVED_STATE(x)		(0x70 + (x) * 4)
132 #define   SPEED(x)				((x) & 0x3)
133 #define     UTMI_HS				SPEED(0)
134 #define     UTMI_FS				SPEED(1)
135 #define     UTMI_LS				SPEED(2)
136 #define     UTMI_RST				SPEED(3)
137 
138 #define XUSB_AO_UHSIC_SAVED_STATE(x)		(0x90 + (x) * 4)
139 #define   MODE(x)				((x) & 0x1)
140 #define   MODE_HS				MODE(0)
141 #define   MODE_RST				MODE(1)
142 
143 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x)		(0xd0 + (x) * 4)
144 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x)		(0xf0 + (x) * 4)
145 #define   FAKE_USBOP_VAL			BIT(0)
146 #define   FAKE_USBON_VAL			BIT(1)
147 #define   FAKE_USBOP_EN				BIT(2)
148 #define   FAKE_USBON_EN				BIT(3)
149 #define   FAKE_STROBE_VAL			BIT(0)
150 #define   FAKE_DATA_VAL				BIT(1)
151 #define   FAKE_STROBE_EN			BIT(2)
152 #define   FAKE_DATA_EN				BIT(3)
153 #define   WAKE_WALK_EN				BIT(14)
154 #define   MASTER_ENABLE				BIT(15)
155 #define   LINEVAL_WALK_EN			BIT(16)
156 #define   WAKE_VAL(x)				(((x) & 0xf) << 17)
157 #define     WAKE_VAL_NONE			WAKE_VAL(12)
158 #define     WAKE_VAL_ANY			WAKE_VAL(15)
159 #define     WAKE_VAL_DS10			WAKE_VAL(2)
160 #define   LINE_WAKEUP_EN			BIT(21)
161 #define   MASTER_CFG_SEL			BIT(22)
162 
163 #define XUSB_AO_UTMIP_SLEEPWALK(x)		(0x100 + (x) * 4)
164 /* phase A */
165 #define   USBOP_RPD_A				BIT(0)
166 #define   USBON_RPD_A				BIT(1)
167 #define   AP_A					BIT(4)
168 #define   AN_A					BIT(5)
169 #define   HIGHZ_A				BIT(6)
170 /* phase B */
171 #define   USBOP_RPD_B				BIT(8)
172 #define   USBON_RPD_B				BIT(9)
173 #define   AP_B					BIT(12)
174 #define   AN_B					BIT(13)
175 #define   HIGHZ_B				BIT(14)
176 /* phase C */
177 #define   USBOP_RPD_C				BIT(16)
178 #define   USBON_RPD_C				BIT(17)
179 #define   AP_C					BIT(20)
180 #define   AN_C					BIT(21)
181 #define   HIGHZ_C				BIT(22)
182 /* phase D */
183 #define   USBOP_RPD_D				BIT(24)
184 #define   USBON_RPD_D				BIT(25)
185 #define   AP_D					BIT(28)
186 #define   AN_D					BIT(29)
187 #define   HIGHZ_D				BIT(30)
188 
189 #define XUSB_AO_UHSIC_SLEEPWALK(x)		(0x120 + (x) * 4)
190 /* phase A */
191 #define   RPD_STROBE_A				BIT(0)
192 #define   RPD_DATA0_A				BIT(1)
193 #define   RPU_STROBE_A				BIT(2)
194 #define   RPU_DATA0_A				BIT(3)
195 /* phase B */
196 #define   RPD_STROBE_B				BIT(8)
197 #define   RPD_DATA0_B				BIT(9)
198 #define   RPU_STROBE_B				BIT(10)
199 #define   RPU_DATA0_B				BIT(11)
200 /* phase C */
201 #define   RPD_STROBE_C				BIT(16)
202 #define   RPD_DATA0_C				BIT(17)
203 #define   RPU_STROBE_C				BIT(18)
204 #define   RPU_DATA0_C				BIT(19)
205 /* phase D */
206 #define   RPD_STROBE_D				BIT(24)
207 #define   RPD_DATA0_D				BIT(25)
208 #define   RPU_STROBE_D				BIT(26)
209 #define   RPU_DATA0_D				BIT(27)
210 
211 #define XUSB_AO_UTMIP_PAD_CFG(x)		(0x130 + (x) * 4)
212 #define   FSLS_USE_XUSB_AO			BIT(3)
213 #define   TRK_CTRL_USE_XUSB_AO			BIT(4)
214 #define   RPD_CTRL_USE_XUSB_AO			BIT(5)
215 #define   RPU_USE_XUSB_AO			BIT(6)
216 #define   VREG_USE_XUSB_AO			BIT(7)
217 #define   USBOP_VAL_PD				BIT(8)
218 #define   USBON_VAL_PD				BIT(9)
219 #define   E_DPD_OVRD_EN				BIT(10)
220 #define   E_DPD_OVRD_VAL			BIT(11)
221 
222 #define XUSB_AO_UHSIC_PAD_CFG(x)		(0x150 + (x) * 4)
223 #define   STROBE_VAL_PD				BIT(0)
224 #define   DATA0_VAL_PD				BIT(1)
225 #define   USE_XUSB_AO				BIT(4)
226 
227 #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type)		\
228 	{								\
229 		.name = _name,						\
230 		.offset = _offset,					\
231 		.shift = _shift,					\
232 		.mask = _mask,						\
233 		.num_funcs = ARRAY_SIZE(tegra186_##_type##_functions),	\
234 		.funcs = tegra186_##_type##_functions,			\
235 	}
236 
237 struct tegra_xusb_fuse_calibration {
238 	u32 *hs_curr_level;
239 	u32 hs_squelch;
240 	u32 hs_term_range_adj;
241 	u32 rpd_ctrl;
242 };
243 
244 struct tegra186_xusb_padctl_context {
245 	u32 vbus_id;
246 	u32 usb2_pad_mux;
247 	u32 usb2_port_cap;
248 	u32 ss_port_cap;
249 };
250 
251 struct tegra186_xusb_padctl {
252 	struct tegra_xusb_padctl base;
253 	void __iomem *ao_regs;
254 
255 	struct tegra_xusb_fuse_calibration calib;
256 
257 	/* UTMI bias and tracking */
258 	struct clk *usb2_trk_clk;
259 	unsigned int bias_pad_enable;
260 
261 	/* padctl context */
262 	struct tegra186_xusb_padctl_context context;
263 };
264 
265 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset)
266 {
267 	writel(value, priv->ao_regs + offset);
268 }
269 
270 static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset)
271 {
272 	return readl(priv->ao_regs + offset);
273 }
274 
275 static inline struct tegra186_xusb_padctl *
276 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
277 {
278 	return container_of(padctl, struct tegra186_xusb_padctl, base);
279 }
280 
281 /* USB 2.0 UTMI PHY support */
282 static struct tegra_xusb_lane *
283 tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
284 			 unsigned int index)
285 {
286 	struct tegra_xusb_usb2_lane *usb2;
287 	int err;
288 
289 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
290 	if (!usb2)
291 		return ERR_PTR(-ENOMEM);
292 
293 	INIT_LIST_HEAD(&usb2->base.list);
294 	usb2->base.soc = &pad->soc->lanes[index];
295 	usb2->base.index = index;
296 	usb2->base.pad = pad;
297 	usb2->base.np = np;
298 
299 	err = tegra_xusb_lane_parse_dt(&usb2->base, np);
300 	if (err < 0) {
301 		kfree(usb2);
302 		return ERR_PTR(err);
303 	}
304 
305 	return &usb2->base;
306 }
307 
308 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
309 {
310 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
311 
312 	kfree(usb2);
313 }
314 
315 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
316 					      enum usb_device_speed speed)
317 {
318 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
319 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
320 	unsigned int index = lane->index;
321 	u32 value;
322 
323 	mutex_lock(&padctl->lock);
324 
325 	/* ensure sleepwalk logic is disabled */
326 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
327 	value &= ~MASTER_ENABLE;
328 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
329 
330 	/* ensure sleepwalk logics are in low power mode */
331 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
332 	value |= MASTER_CFG_SEL;
333 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
334 
335 	/* set debounce time */
336 	value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
337 	value &= ~UTMIP_LINE_DEB_CNT(~0);
338 	value |= UTMIP_LINE_DEB_CNT(1);
339 	ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
340 
341 	/* ensure fake events of sleepwalk logic are desiabled */
342 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
343 	value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
344 		FAKE_USBOP_EN | FAKE_USBON_EN);
345 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
346 
347 	/* ensure wake events of sleepwalk logic are not latched */
348 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
349 	value &= ~LINE_WAKEUP_EN;
350 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
351 
352 	/* disable wake event triggers of sleepwalk logic */
353 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
354 	value &= ~WAKE_VAL(~0);
355 	value |= WAKE_VAL_NONE;
356 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
357 
358 	/* power down the line state detectors of the pad */
359 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
360 	value |= (USBOP_VAL_PD | USBON_VAL_PD);
361 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
362 
363 	/* save state per speed */
364 	value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
365 	value &= ~SPEED(~0);
366 
367 	switch (speed) {
368 	case USB_SPEED_HIGH:
369 		value |= UTMI_HS;
370 		break;
371 
372 	case USB_SPEED_FULL:
373 		value |= UTMI_FS;
374 		break;
375 
376 	case USB_SPEED_LOW:
377 		value |= UTMI_LS;
378 		break;
379 
380 	default:
381 		value |= UTMI_RST;
382 		break;
383 	}
384 
385 	ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
386 
387 	/* enable the trigger of the sleepwalk logic */
388 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
389 	value |= LINEVAL_WALK_EN;
390 	value &= ~WAKE_WALK_EN;
391 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
392 
393 	/* reset the walk pointer and clear the alarm of the sleepwalk logic,
394 	 * as well as capture the configuration of the USB2.0 pad
395 	 */
396 	value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
397 	value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
398 	ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
399 
400 	/* setup the pull-ups and pull-downs of the signals during the four
401 	 * stages of sleepwalk.
402 	 * if device is connected, program sleepwalk logic to maintain a J and
403 	 * keep driving K upon seeing remote wake.
404 	 */
405 	value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D;
406 	value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D;
407 
408 	switch (speed) {
409 	case USB_SPEED_HIGH:
410 	case USB_SPEED_FULL:
411 		/* J state: D+/D- = high/low, K state: D+/D- = low/high */
412 		value |= HIGHZ_A;
413 		value |= AP_A;
414 		value |= AN_B | AN_C | AN_D;
415 		break;
416 
417 	case USB_SPEED_LOW:
418 		/* J state: D+/D- = low/high, K state: D+/D- = high/low */
419 		value |= HIGHZ_A;
420 		value |= AN_A;
421 		value |= AP_B | AP_C | AP_D;
422 		break;
423 
424 	default:
425 		value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D;
426 		break;
427 	}
428 
429 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
430 
431 	/* power up the line state detectors of the pad */
432 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
433 	value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
434 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
435 
436 	usleep_range(150, 200);
437 
438 	/* switch the electric control of the USB2.0 pad to XUSB_AO */
439 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
440 	value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
441 		 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO;
442 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
443 
444 	/* set the wake signaling trigger events */
445 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
446 	value &= ~WAKE_VAL(~0);
447 	value |= WAKE_VAL_ANY;
448 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
449 
450 	/* enable the wake detection */
451 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
452 	value |= MASTER_ENABLE | LINE_WAKEUP_EN;
453 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
454 
455 	mutex_unlock(&padctl->lock);
456 
457 	return 0;
458 }
459 
460 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
461 {
462 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
463 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
464 	unsigned int index = lane->index;
465 	u32 value;
466 
467 	mutex_lock(&padctl->lock);
468 
469 	/* disable the wake detection */
470 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
471 	value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
472 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
473 
474 	/* switch the electric control of the USB2.0 pad to XUSB vcore logic */
475 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
476 	value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
477 		   RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
478 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
479 
480 	/* disable wake event triggers of sleepwalk logic */
481 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
482 	value &= ~WAKE_VAL(~0);
483 	value |= WAKE_VAL_NONE;
484 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
485 
486 	/* power down the line state detectors of the port */
487 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
488 	value |= USBOP_VAL_PD | USBON_VAL_PD;
489 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
490 
491 	/* clear alarm of the sleepwalk logic */
492 	value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
493 	value |= CLR_WAKE_ALARM;
494 	ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
495 
496 	mutex_unlock(&padctl->lock);
497 
498 	return 0;
499 }
500 
501 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
502 {
503 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
504 	unsigned int index = lane->index;
505 	u32 value;
506 
507 	mutex_lock(&padctl->lock);
508 
509 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
510 	value &= ~ALL_WAKE_EVENTS;
511 	value |= USB2_PORT_WAKEUP_EVENT(index);
512 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
513 
514 	usleep_range(10, 20);
515 
516 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
517 	value &= ~ALL_WAKE_EVENTS;
518 	value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
519 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
520 
521 	mutex_unlock(&padctl->lock);
522 
523 	return 0;
524 }
525 
526 static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
527 {
528 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
529 	unsigned int index = lane->index;
530 	u32 value;
531 
532 	mutex_lock(&padctl->lock);
533 
534 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
535 	value &= ~ALL_WAKE_EVENTS;
536 	value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
537 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
538 
539 	usleep_range(10, 20);
540 
541 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
542 	value &= ~ALL_WAKE_EVENTS;
543 	value |= USB2_PORT_WAKEUP_EVENT(index);
544 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
545 
546 	mutex_unlock(&padctl->lock);
547 
548 	return 0;
549 }
550 
551 static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
552 {
553 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
554 	unsigned int index = lane->index;
555 	u32 value;
556 
557 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
558 	if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
559 	    (value & USB2_PORT_WAKEUP_EVENT(index)))
560 		return true;
561 
562 	return false;
563 }
564 
565 static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
566 	.probe = tegra186_usb2_lane_probe,
567 	.remove = tegra186_usb2_lane_remove,
568 	.enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk,
569 	.disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk,
570 	.enable_phy_wake = tegra186_utmi_enable_phy_wake,
571 	.disable_phy_wake = tegra186_utmi_disable_phy_wake,
572 	.remote_wake_detected = tegra186_utmi_phy_remote_wake_detected,
573 };
574 
575 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
576 {
577 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
578 	struct device *dev = padctl->dev;
579 	u32 value;
580 	int err;
581 
582 	mutex_lock(&padctl->lock);
583 
584 	if (priv->bias_pad_enable++ > 0) {
585 		mutex_unlock(&padctl->lock);
586 		return;
587 	}
588 
589 	err = clk_prepare_enable(priv->usb2_trk_clk);
590 	if (err < 0)
591 		dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
592 
593 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
594 	value &= ~USB2_TRK_START_TIMER(~0);
595 	value |= USB2_TRK_START_TIMER(0x1e);
596 	value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
597 	value |= USB2_TRK_DONE_RESET_TIMER(0xa);
598 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
599 
600 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
601 	value &= ~BIAS_PAD_PD;
602 	value &= ~HS_SQUELCH_LEVEL(~0);
603 	value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
604 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
605 
606 	udelay(1);
607 
608 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
609 	value &= ~USB2_PD_TRK;
610 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
611 
612 	mutex_unlock(&padctl->lock);
613 }
614 
615 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
616 {
617 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
618 	u32 value;
619 
620 	mutex_lock(&padctl->lock);
621 
622 	if (WARN_ON(priv->bias_pad_enable == 0)) {
623 		mutex_unlock(&padctl->lock);
624 		return;
625 	}
626 
627 	if (--priv->bias_pad_enable > 0) {
628 		mutex_unlock(&padctl->lock);
629 		return;
630 	}
631 
632 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
633 	value |= USB2_PD_TRK;
634 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
635 
636 	clk_disable_unprepare(priv->usb2_trk_clk);
637 
638 	mutex_unlock(&padctl->lock);
639 }
640 
641 static void tegra186_utmi_pad_power_on(struct phy *phy)
642 {
643 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
644 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
645 	struct tegra_xusb_usb2_port *port;
646 	struct device *dev = padctl->dev;
647 	unsigned int index = lane->index;
648 	u32 value;
649 
650 	if (!phy)
651 		return;
652 
653 	port = tegra_xusb_find_usb2_port(padctl, index);
654 	if (!port) {
655 		dev_err(dev, "no port found for USB2 lane %u\n", index);
656 		return;
657 	}
658 
659 	dev_dbg(dev, "power on UTMI pad %u\n", index);
660 
661 	tegra186_utmi_bias_pad_power_on(padctl);
662 
663 	udelay(2);
664 
665 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
666 	value &= ~USB2_OTG_PD;
667 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
668 
669 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
670 	value &= ~USB2_OTG_PD_DR;
671 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
672 }
673 
674 static void tegra186_utmi_pad_power_down(struct phy *phy)
675 {
676 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
677 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
678 	unsigned int index = lane->index;
679 	u32 value;
680 
681 	if (!phy)
682 		return;
683 
684 	dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);
685 
686 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
687 	value |= USB2_OTG_PD;
688 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
689 
690 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
691 	value |= USB2_OTG_PD_DR;
692 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
693 
694 	udelay(2);
695 
696 	tegra186_utmi_bias_pad_power_off(padctl);
697 }
698 
699 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
700 					       bool status)
701 {
702 	u32 value;
703 
704 	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
705 
706 	value = padctl_readl(padctl, USB2_VBUS_ID);
707 
708 	if (status) {
709 		value |= VBUS_OVERRIDE;
710 		value &= ~ID_OVERRIDE(~0);
711 		value |= ID_OVERRIDE_FLOATING;
712 	} else {
713 		value &= ~VBUS_OVERRIDE;
714 	}
715 
716 	padctl_writel(padctl, value, USB2_VBUS_ID);
717 
718 	return 0;
719 }
720 
721 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
722 					    bool status)
723 {
724 	u32 value;
725 
726 	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
727 
728 	value = padctl_readl(padctl, USB2_VBUS_ID);
729 
730 	if (status) {
731 		if (value & VBUS_OVERRIDE) {
732 			value &= ~VBUS_OVERRIDE;
733 			padctl_writel(padctl, value, USB2_VBUS_ID);
734 			usleep_range(1000, 2000);
735 
736 			value = padctl_readl(padctl, USB2_VBUS_ID);
737 		}
738 
739 		value &= ~ID_OVERRIDE(~0);
740 		value |= ID_OVERRIDE_GROUNDED;
741 	} else {
742 		value &= ~ID_OVERRIDE(~0);
743 		value |= ID_OVERRIDE_FLOATING;
744 	}
745 
746 	padctl_writel(padctl, value, USB2_VBUS_ID);
747 
748 	return 0;
749 }
750 
751 static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
752 				      int submode)
753 {
754 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
755 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
756 	struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
757 								lane->index);
758 	int err = 0;
759 
760 	mutex_lock(&padctl->lock);
761 
762 	dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
763 
764 	if (mode == PHY_MODE_USB_OTG) {
765 		if (submode == USB_ROLE_HOST) {
766 			tegra186_xusb_padctl_id_override(padctl, true);
767 
768 			err = regulator_enable(port->supply);
769 		} else if (submode == USB_ROLE_DEVICE) {
770 			tegra186_xusb_padctl_vbus_override(padctl, true);
771 		} else if (submode == USB_ROLE_NONE) {
772 			/*
773 			 * When port is peripheral only or role transitions to
774 			 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
775 			 * enabled.
776 			 */
777 			if (regulator_is_enabled(port->supply))
778 				regulator_disable(port->supply);
779 
780 			tegra186_xusb_padctl_id_override(padctl, false);
781 			tegra186_xusb_padctl_vbus_override(padctl, false);
782 		}
783 	}
784 
785 	mutex_unlock(&padctl->lock);
786 
787 	return err;
788 }
789 
790 static int tegra186_utmi_phy_power_on(struct phy *phy)
791 {
792 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
793 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
794 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
795 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
796 	struct tegra_xusb_usb2_port *port;
797 	unsigned int index = lane->index;
798 	struct device *dev = padctl->dev;
799 	u32 value;
800 
801 	port = tegra_xusb_find_usb2_port(padctl, index);
802 	if (!port) {
803 		dev_err(dev, "no port found for USB2 lane %u\n", index);
804 		return -ENODEV;
805 	}
806 
807 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
808 	value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
809 	value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
810 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
811 
812 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
813 	value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
814 
815 	if (port->mode == USB_DR_MODE_UNKNOWN)
816 		value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
817 	else if (port->mode == USB_DR_MODE_PERIPHERAL)
818 		value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
819 	else if (port->mode == USB_DR_MODE_HOST)
820 		value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
821 	else if (port->mode == USB_DR_MODE_OTG)
822 		value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
823 
824 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
825 
826 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
827 	value &= ~USB2_OTG_PD_ZI;
828 	value |= TERM_SEL;
829 	value &= ~HS_CURR_LEVEL(~0);
830 
831 	if (usb2->hs_curr_level_offset) {
832 		int hs_current_level;
833 
834 		hs_current_level = (int)priv->calib.hs_curr_level[index] +
835 						usb2->hs_curr_level_offset;
836 
837 		if (hs_current_level < 0)
838 			hs_current_level = 0;
839 		if (hs_current_level > 0x3f)
840 			hs_current_level = 0x3f;
841 
842 		value |= HS_CURR_LEVEL(hs_current_level);
843 	} else {
844 		value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
845 	}
846 
847 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
848 
849 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
850 	value &= ~TERM_RANGE_ADJ(~0);
851 	value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
852 	value &= ~RPD_CTRL(~0);
853 	value |= RPD_CTRL(priv->calib.rpd_ctrl);
854 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
855 
856 	tegra186_utmi_pad_power_on(phy);
857 
858 	return 0;
859 }
860 
861 static int tegra186_utmi_phy_power_off(struct phy *phy)
862 {
863 	tegra186_utmi_pad_power_down(phy);
864 
865 	return 0;
866 }
867 
868 static int tegra186_utmi_phy_init(struct phy *phy)
869 {
870 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
871 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
872 	struct tegra_xusb_usb2_port *port;
873 	unsigned int index = lane->index;
874 	struct device *dev = padctl->dev;
875 	int err;
876 
877 	port = tegra_xusb_find_usb2_port(padctl, index);
878 	if (!port) {
879 		dev_err(dev, "no port found for USB2 lane %u\n", index);
880 		return -ENODEV;
881 	}
882 
883 	if (port->supply && port->mode == USB_DR_MODE_HOST) {
884 		err = regulator_enable(port->supply);
885 		if (err) {
886 			dev_err(dev, "failed to enable port %u VBUS: %d\n",
887 				index, err);
888 			return err;
889 		}
890 	}
891 
892 	return 0;
893 }
894 
895 static int tegra186_utmi_phy_exit(struct phy *phy)
896 {
897 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
898 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
899 	struct tegra_xusb_usb2_port *port;
900 	unsigned int index = lane->index;
901 	struct device *dev = padctl->dev;
902 	int err;
903 
904 	port = tegra_xusb_find_usb2_port(padctl, index);
905 	if (!port) {
906 		dev_err(dev, "no port found for USB2 lane %u\n", index);
907 		return -ENODEV;
908 	}
909 
910 	if (port->supply && port->mode == USB_DR_MODE_HOST) {
911 		err = regulator_disable(port->supply);
912 		if (err) {
913 			dev_err(dev, "failed to disable port %u VBUS: %d\n",
914 				index, err);
915 			return err;
916 		}
917 	}
918 
919 	return 0;
920 }
921 
922 static const struct phy_ops utmi_phy_ops = {
923 	.init = tegra186_utmi_phy_init,
924 	.exit = tegra186_utmi_phy_exit,
925 	.power_on = tegra186_utmi_phy_power_on,
926 	.power_off = tegra186_utmi_phy_power_off,
927 	.set_mode = tegra186_utmi_phy_set_mode,
928 	.owner = THIS_MODULE,
929 };
930 
931 static struct tegra_xusb_pad *
932 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
933 			const struct tegra_xusb_pad_soc *soc,
934 			struct device_node *np)
935 {
936 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
937 	struct tegra_xusb_usb2_pad *usb2;
938 	struct tegra_xusb_pad *pad;
939 	int err;
940 
941 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
942 	if (!usb2)
943 		return ERR_PTR(-ENOMEM);
944 
945 	pad = &usb2->base;
946 	pad->ops = &tegra186_usb2_lane_ops;
947 	pad->soc = soc;
948 
949 	err = tegra_xusb_pad_init(pad, padctl, np);
950 	if (err < 0) {
951 		kfree(usb2);
952 		goto out;
953 	}
954 
955 	priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
956 	if (IS_ERR(priv->usb2_trk_clk)) {
957 		err = PTR_ERR(priv->usb2_trk_clk);
958 		dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
959 		goto unregister;
960 	}
961 
962 	err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
963 	if (err < 0)
964 		goto unregister;
965 
966 	dev_set_drvdata(&pad->dev, pad);
967 
968 	return pad;
969 
970 unregister:
971 	device_unregister(&pad->dev);
972 out:
973 	return ERR_PTR(err);
974 }
975 
976 static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
977 {
978 	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
979 
980 	kfree(usb2);
981 }
982 
983 static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
984 	.probe = tegra186_usb2_pad_probe,
985 	.remove = tegra186_usb2_pad_remove,
986 };
987 
988 static const char * const tegra186_usb2_functions[] = {
989 	"xusb",
990 };
991 
992 static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
993 {
994 	return 0;
995 }
996 
997 static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
998 {
999 }
1000 
1001 static struct tegra_xusb_lane *
1002 tegra186_usb2_port_map(struct tegra_xusb_port *port)
1003 {
1004 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1005 }
1006 
1007 static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
1008 	.release = tegra_xusb_usb2_port_release,
1009 	.remove = tegra_xusb_usb2_port_remove,
1010 	.enable = tegra186_usb2_port_enable,
1011 	.disable = tegra186_usb2_port_disable,
1012 	.map = tegra186_usb2_port_map,
1013 };
1014 
1015 /* SuperSpeed PHY support */
1016 static struct tegra_xusb_lane *
1017 tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1018 			 unsigned int index)
1019 {
1020 	struct tegra_xusb_usb3_lane *usb3;
1021 	int err;
1022 
1023 	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1024 	if (!usb3)
1025 		return ERR_PTR(-ENOMEM);
1026 
1027 	INIT_LIST_HEAD(&usb3->base.list);
1028 	usb3->base.soc = &pad->soc->lanes[index];
1029 	usb3->base.index = index;
1030 	usb3->base.pad = pad;
1031 	usb3->base.np = np;
1032 
1033 	err = tegra_xusb_lane_parse_dt(&usb3->base, np);
1034 	if (err < 0) {
1035 		kfree(usb3);
1036 		return ERR_PTR(err);
1037 	}
1038 
1039 	return &usb3->base;
1040 }
1041 
1042 static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
1043 {
1044 	struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
1045 
1046 	kfree(usb3);
1047 }
1048 
1049 static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1050 					      enum usb_device_speed speed)
1051 {
1052 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1053 	unsigned int index = lane->index;
1054 	u32 value;
1055 
1056 	mutex_lock(&padctl->lock);
1057 
1058 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1059 	value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1060 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1061 
1062 	usleep_range(100, 200);
1063 
1064 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1065 	value |= SSPX_ELPG_CLAMP_EN(index);
1066 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1067 
1068 	usleep_range(250, 350);
1069 
1070 	mutex_unlock(&padctl->lock);
1071 
1072 	return 0;
1073 }
1074 
1075 static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1076 {
1077 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1078 	unsigned int index = lane->index;
1079 	u32 value;
1080 
1081 	mutex_lock(&padctl->lock);
1082 
1083 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1084 	value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1085 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1086 
1087 	usleep_range(100, 200);
1088 
1089 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1090 	value &= ~SSPX_ELPG_CLAMP_EN(index);
1091 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1092 
1093 	mutex_unlock(&padctl->lock);
1094 
1095 	return 0;
1096 }
1097 
1098 static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1099 {
1100 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1101 	unsigned int index = lane->index;
1102 	u32 value;
1103 
1104 	mutex_lock(&padctl->lock);
1105 
1106 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1107 	value &= ~ALL_WAKE_EVENTS;
1108 	value |= SS_PORT_WAKEUP_EVENT(index);
1109 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1110 
1111 	usleep_range(10, 20);
1112 
1113 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1114 	value &= ~ALL_WAKE_EVENTS;
1115 	value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1116 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1117 
1118 	mutex_unlock(&padctl->lock);
1119 
1120 	return 0;
1121 }
1122 
1123 static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1124 {
1125 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1126 	unsigned int index = lane->index;
1127 	u32 value;
1128 
1129 	mutex_lock(&padctl->lock);
1130 
1131 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1132 	value &= ~ALL_WAKE_EVENTS;
1133 	value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1134 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1135 
1136 	usleep_range(10, 20);
1137 
1138 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1139 	value &= ~ALL_WAKE_EVENTS;
1140 	value |= SS_PORT_WAKEUP_EVENT(index);
1141 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1142 
1143 	mutex_unlock(&padctl->lock);
1144 
1145 	return 0;
1146 }
1147 
1148 static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1149 {
1150 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1151 	unsigned int index = lane->index;
1152 	u32 value;
1153 
1154 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1155 	if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1156 		return true;
1157 
1158 	return false;
1159 }
1160 
1161 static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
1162 	.probe = tegra186_usb3_lane_probe,
1163 	.remove = tegra186_usb3_lane_remove,
1164 	.enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk,
1165 	.disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk,
1166 	.enable_phy_wake = tegra186_usb3_enable_phy_wake,
1167 	.disable_phy_wake = tegra186_usb3_disable_phy_wake,
1168 	.remote_wake_detected = tegra186_usb3_phy_remote_wake_detected,
1169 };
1170 
1171 static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
1172 {
1173 	return 0;
1174 }
1175 
1176 static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
1177 {
1178 }
1179 
1180 static struct tegra_xusb_lane *
1181 tegra186_usb3_port_map(struct tegra_xusb_port *port)
1182 {
1183 	return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1184 }
1185 
1186 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
1187 	.release = tegra_xusb_usb3_port_release,
1188 	.remove = tegra_xusb_usb3_port_remove,
1189 	.enable = tegra186_usb3_port_enable,
1190 	.disable = tegra186_usb3_port_disable,
1191 	.map = tegra186_usb3_port_map,
1192 };
1193 
1194 static int tegra186_usb3_phy_power_on(struct phy *phy)
1195 {
1196 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1197 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1198 	struct tegra_xusb_usb3_port *port;
1199 	struct tegra_xusb_usb2_port *usb2;
1200 	unsigned int index = lane->index;
1201 	struct device *dev = padctl->dev;
1202 	u32 value;
1203 
1204 	port = tegra_xusb_find_usb3_port(padctl, index);
1205 	if (!port) {
1206 		dev_err(dev, "no port found for USB3 lane %u\n", index);
1207 		return -ENODEV;
1208 	}
1209 
1210 	usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1211 	if (!usb2) {
1212 		dev_err(dev, "no companion port found for USB3 lane %u\n",
1213 			index);
1214 		return -ENODEV;
1215 	}
1216 
1217 	mutex_lock(&padctl->lock);
1218 
1219 	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1220 	value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
1221 
1222 	if (usb2->mode == USB_DR_MODE_UNKNOWN)
1223 		value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
1224 	else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
1225 		value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
1226 	else if (usb2->mode == USB_DR_MODE_HOST)
1227 		value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
1228 	else if (usb2->mode == USB_DR_MODE_OTG)
1229 		value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
1230 
1231 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1232 
1233 	if (padctl->soc->supports_gen2 && port->disable_gen2) {
1234 		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1235 		value &= ~(PORTX_SPEED_SUPPORT_MASK <<
1236 			PORTX_SPEED_SUPPORT_SHIFT(index));
1237 		value |= (PORT_SPEED_SUPPORT_GEN1 <<
1238 			PORTX_SPEED_SUPPORT_SHIFT(index));
1239 		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1240 	}
1241 
1242 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1243 	value &= ~SSPX_ELPG_VCORE_DOWN(index);
1244 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1245 
1246 	usleep_range(100, 200);
1247 
1248 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1249 	value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1250 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1251 
1252 	usleep_range(100, 200);
1253 
1254 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1255 	value &= ~SSPX_ELPG_CLAMP_EN(index);
1256 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1257 
1258 	mutex_unlock(&padctl->lock);
1259 
1260 	return 0;
1261 }
1262 
1263 static int tegra186_usb3_phy_power_off(struct phy *phy)
1264 {
1265 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1266 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1267 	struct tegra_xusb_usb3_port *port;
1268 	unsigned int index = lane->index;
1269 	struct device *dev = padctl->dev;
1270 	u32 value;
1271 
1272 	port = tegra_xusb_find_usb3_port(padctl, index);
1273 	if (!port) {
1274 		dev_err(dev, "no port found for USB3 lane %u\n", index);
1275 		return -ENODEV;
1276 	}
1277 
1278 	mutex_lock(&padctl->lock);
1279 
1280 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1281 	value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1282 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1283 
1284 	usleep_range(100, 200);
1285 
1286 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1287 	value |= SSPX_ELPG_CLAMP_EN(index);
1288 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1289 
1290 	usleep_range(250, 350);
1291 
1292 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1293 	value |= SSPX_ELPG_VCORE_DOWN(index);
1294 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1295 
1296 	mutex_unlock(&padctl->lock);
1297 
1298 	return 0;
1299 }
1300 
1301 static int tegra186_usb3_phy_init(struct phy *phy)
1302 {
1303 	return 0;
1304 }
1305 
1306 static int tegra186_usb3_phy_exit(struct phy *phy)
1307 {
1308 	return 0;
1309 }
1310 
1311 static const struct phy_ops usb3_phy_ops = {
1312 	.init = tegra186_usb3_phy_init,
1313 	.exit = tegra186_usb3_phy_exit,
1314 	.power_on = tegra186_usb3_phy_power_on,
1315 	.power_off = tegra186_usb3_phy_power_off,
1316 	.owner = THIS_MODULE,
1317 };
1318 
1319 static struct tegra_xusb_pad *
1320 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1321 			const struct tegra_xusb_pad_soc *soc,
1322 			struct device_node *np)
1323 {
1324 	struct tegra_xusb_usb3_pad *usb3;
1325 	struct tegra_xusb_pad *pad;
1326 	int err;
1327 
1328 	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1329 	if (!usb3)
1330 		return ERR_PTR(-ENOMEM);
1331 
1332 	pad = &usb3->base;
1333 	pad->ops = &tegra186_usb3_lane_ops;
1334 	pad->soc = soc;
1335 
1336 	err = tegra_xusb_pad_init(pad, padctl, np);
1337 	if (err < 0) {
1338 		kfree(usb3);
1339 		goto out;
1340 	}
1341 
1342 	err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
1343 	if (err < 0)
1344 		goto unregister;
1345 
1346 	dev_set_drvdata(&pad->dev, pad);
1347 
1348 	return pad;
1349 
1350 unregister:
1351 	device_unregister(&pad->dev);
1352 out:
1353 	return ERR_PTR(err);
1354 }
1355 
1356 static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
1357 {
1358 	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1359 
1360 	kfree(usb2);
1361 }
1362 
1363 static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
1364 	.probe = tegra186_usb3_pad_probe,
1365 	.remove = tegra186_usb3_pad_remove,
1366 };
1367 
1368 static const char * const tegra186_usb3_functions[] = {
1369 	"xusb",
1370 };
1371 
1372 static int
1373 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1374 {
1375 	struct device *dev = padctl->base.dev;
1376 	unsigned int i, count;
1377 	u32 value, *level;
1378 	int err;
1379 
1380 	count = padctl->base.soc->ports.usb2.count;
1381 
1382 	level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
1383 	if (!level)
1384 		return -ENOMEM;
1385 
1386 	err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
1387 	if (err)
1388 		return dev_err_probe(dev, err,
1389 				     "failed to read calibration fuse\n");
1390 
1391 	dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
1392 
1393 	for (i = 0; i < count; i++)
1394 		level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
1395 				HS_CURR_LEVEL_PAD_MASK;
1396 
1397 	padctl->calib.hs_curr_level = level;
1398 
1399 	padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1400 					HS_SQUELCH_MASK;
1401 	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1402 						HS_TERM_RANGE_ADJ_MASK;
1403 
1404 	err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
1405 	if (err) {
1406 		dev_err(dev, "failed to read calibration fuse: %d\n", err);
1407 		return err;
1408 	}
1409 
1410 	dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
1411 
1412 	padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1413 
1414 	return 0;
1415 }
1416 
1417 static struct tegra_xusb_padctl *
1418 tegra186_xusb_padctl_probe(struct device *dev,
1419 			   const struct tegra_xusb_padctl_soc *soc)
1420 {
1421 	struct platform_device *pdev = to_platform_device(dev);
1422 	struct tegra186_xusb_padctl *priv;
1423 	struct resource *res;
1424 	int err;
1425 
1426 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1427 	if (!priv)
1428 		return ERR_PTR(-ENOMEM);
1429 
1430 	priv->base.dev = dev;
1431 	priv->base.soc = soc;
1432 
1433 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
1434 	priv->ao_regs = devm_ioremap_resource(dev, res);
1435 	if (IS_ERR(priv->ao_regs))
1436 		return ERR_CAST(priv->ao_regs);
1437 
1438 	err = tegra186_xusb_read_fuse_calibration(priv);
1439 	if (err < 0)
1440 		return ERR_PTR(err);
1441 
1442 	return &priv->base;
1443 }
1444 
1445 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1446 {
1447 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1448 
1449 	priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1450 	priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1451 	priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1452 	priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1453 }
1454 
1455 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1456 {
1457 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1458 
1459 	padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1460 	padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1461 	padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1462 	padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1463 }
1464 
1465 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1466 {
1467 	tegra186_xusb_padctl_save(padctl);
1468 
1469 	return 0;
1470 }
1471 
1472 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1473 {
1474 	tegra186_xusb_padctl_restore(padctl);
1475 
1476 	return 0;
1477 }
1478 
1479 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
1480 {
1481 }
1482 
1483 static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
1484 	.probe = tegra186_xusb_padctl_probe,
1485 	.remove = tegra186_xusb_padctl_remove,
1486 	.suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
1487 	.resume_noirq = tegra186_xusb_padctl_resume_noirq,
1488 	.vbus_override = tegra186_xusb_padctl_vbus_override,
1489 	.utmi_pad_power_on = tegra186_utmi_pad_power_on,
1490 	.utmi_pad_power_down = tegra186_utmi_pad_power_down,
1491 };
1492 
1493 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1494 static const char * const tegra186_xusb_padctl_supply_names[] = {
1495 	"avdd-pll-erefeut",
1496 	"avdd-usb",
1497 	"vclamp-usb",
1498 	"vddio-hsic",
1499 };
1500 
1501 static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
1502 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1503 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1504 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1505 };
1506 
1507 static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
1508 	.name = "usb2",
1509 	.num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
1510 	.lanes = tegra186_usb2_lanes,
1511 	.ops = &tegra186_usb2_pad_ops,
1512 };
1513 
1514 static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
1515 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1516 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1517 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1518 };
1519 
1520 static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
1521 	.name = "usb3",
1522 	.num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
1523 	.lanes = tegra186_usb3_lanes,
1524 	.ops = &tegra186_usb3_pad_ops,
1525 };
1526 
1527 static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
1528 	&tegra186_usb2_pad,
1529 	&tegra186_usb3_pad,
1530 #if 0 /* TODO implement */
1531 	&tegra186_hsic_pad,
1532 #endif
1533 };
1534 
1535 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
1536 	.num_pads = ARRAY_SIZE(tegra186_pads),
1537 	.pads = tegra186_pads,
1538 	.ports = {
1539 		.usb2 = {
1540 			.ops = &tegra186_usb2_port_ops,
1541 			.count = 3,
1542 		},
1543 #if 0 /* TODO implement */
1544 		.hsic = {
1545 			.ops = &tegra186_hsic_port_ops,
1546 			.count = 1,
1547 		},
1548 #endif
1549 		.usb3 = {
1550 			.ops = &tegra186_usb3_port_ops,
1551 			.count = 3,
1552 		},
1553 	},
1554 	.ops = &tegra186_xusb_padctl_ops,
1555 	.supply_names = tegra186_xusb_padctl_supply_names,
1556 	.num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1557 };
1558 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1559 #endif
1560 
1561 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
1562 static const char * const tegra194_xusb_padctl_supply_names[] = {
1563 	"avdd-usb",
1564 	"vclamp-usb",
1565 };
1566 
1567 static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1568 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1569 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1570 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1571 	TEGRA186_LANE("usb2-3", 0,  0, 0, usb2),
1572 };
1573 
1574 static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1575 	.name = "usb2",
1576 	.num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1577 	.lanes = tegra194_usb2_lanes,
1578 	.ops = &tegra186_usb2_pad_ops,
1579 };
1580 
1581 static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1582 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1583 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1584 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1585 	TEGRA186_LANE("usb3-3", 0,  0, 0, usb3),
1586 };
1587 
1588 static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1589 	.name = "usb3",
1590 	.num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1591 	.lanes = tegra194_usb3_lanes,
1592 	.ops = &tegra186_usb3_pad_ops,
1593 };
1594 
1595 static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1596 	&tegra194_usb2_pad,
1597 	&tegra194_usb3_pad,
1598 };
1599 
1600 const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1601 	.num_pads = ARRAY_SIZE(tegra194_pads),
1602 	.pads = tegra194_pads,
1603 	.ports = {
1604 		.usb2 = {
1605 			.ops = &tegra186_usb2_port_ops,
1606 			.count = 4,
1607 		},
1608 		.usb3 = {
1609 			.ops = &tegra186_usb3_port_ops,
1610 			.count = 4,
1611 		},
1612 	},
1613 	.ops = &tegra186_xusb_padctl_ops,
1614 	.supply_names = tegra194_xusb_padctl_supply_names,
1615 	.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1616 	.supports_gen2 = true,
1617 };
1618 EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1619 #endif
1620 
1621 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1622 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1623 MODULE_LICENSE("GPL v2");
1624